1/* 2 * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a35.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14cpu_reset_prologue cortex_a35 15 /* --------------------------------------------- 16 * Disable intra-cluster coherency 17 * --------------------------------------------- 18 */ 19func cortex_a35_disable_smp 20 sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT 21 isb 22 dsb sy 23 ret 24endfunc cortex_a35_disable_smp 25 26workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472 27 sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI 28workaround_reset_end cortex_a35, ERRATUM(855472) 29 30check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0) 31 32 /* ------------------------------------------------- 33 * The CPU Ops reset function for Cortex-A35. 34 * ------------------------------------------------- 35 */ 36cpu_reset_func_start cortex_a35 37 /* --------------------------------------------- 38 * Enable the SMP bit. 39 * --------------------------------------------- 40 */ 41 sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT 42cpu_reset_func_end cortex_a35 43 44func cortex_a35_core_pwr_dwn 45 mov x18, x30 46 47 /* --------------------------------------------- 48 * Flush L1 caches. 49 * --------------------------------------------- 50 */ 51 mov x0, #DCCISW 52 bl dcsw_op_level1 53 54 /* --------------------------------------------- 55 * Come out of intra cluster coherency 56 * --------------------------------------------- 57 */ 58 mov x30, x18 59 b cortex_a35_disable_smp 60endfunc cortex_a35_core_pwr_dwn 61 62func cortex_a35_cluster_pwr_dwn 63 mov x18, x30 64 65 /* --------------------------------------------- 66 * Flush L1 caches. 67 * --------------------------------------------- 68 */ 69 mov x0, #DCCISW 70 bl dcsw_op_level1 71 72 /* --------------------------------------------- 73 * Disable the optional ACP. 74 * --------------------------------------------- 75 */ 76 bl plat_disable_acp 77 78 /* --------------------------------------------- 79 * Flush L2 caches. 80 * --------------------------------------------- 81 */ 82 mov x0, #DCCISW 83 bl dcsw_op_level2 84 85 /* --------------------------------------------- 86 * Come out of intra cluster coherency 87 * --------------------------------------------- 88 */ 89 mov x30, x18 90 b cortex_a35_disable_smp 91endfunc cortex_a35_cluster_pwr_dwn 92 93 /* --------------------------------------------- 94 * This function provides cortex_a35 specific 95 * register information for crash reporting. 96 * It needs to return with x6 pointing to 97 * a list of register names in ascii and 98 * x8 - x15 having values of registers to be 99 * reported. 100 * --------------------------------------------- 101 */ 102.section .rodata.cortex_a35_regs, "aS" 103cortex_a35_regs: /* The ascii list of register names to be reported */ 104 .asciz "cpuectlr_el1", "" 105 106func cortex_a35_cpu_reg_dump 107 adr x6, cortex_a35_regs 108 mrs x8, CORTEX_A35_CPUECTLR_EL1 109 ret 110endfunc cortex_a35_cpu_reg_dump 111 112declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \ 113 cortex_a35_reset_func, \ 114 cortex_a35_core_pwr_dwn, \ 115 cortex_a35_cluster_pwr_dwn 116