1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ 8 #define PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ 9 10 #include <lib/utils_def.h> 11 #include <mtcmos_common.h> 12 #include <platform_def.h> 13 14 #define RTFF_SAVE BIT(24) 15 #define RTFF_NRESTORE BIT(25) 16 #define RTFF_CLK_DIS BIT(26) 17 #define RTFF_SAVE_FLAG BIT(27) 18 19 #define POWERON_CONFIG_EN (SPM_BASE + 0x0) 20 #define UFS0_PWR_CON (SPM_BASE + 0xE2C) 21 #define UFS0_PHY_PWR_CON (SPM_BASE + 0xE30) 22 23 #define SPM_BUS_PROTECT_EN_SET (SPM_BASE + 0x90DC) 24 #define SPM_BUS_PROTECT_EN_CLR (SPM_BASE + 0x90E0) 25 #define SPM_BUS_PROTECT_CG_EN_SET (SPM_BASE + 0x90F4) 26 #define SPM_BUS_PROTECT_CG_EN_CLR (SPM_BASE + 0x90F8) 27 #define SPM_BUS_PROTECT_RDY_STA (SPM_BASE + 0x9208) 28 29 #define UFS0_PROT_STEP1_MASK BIT(11) 30 #define UFS0_PHY_PROT_STEP1_MASK BIT(12) 31 32 static const struct bus_protect ufs0_bus_prot_set_table[] = { 33 {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PROT_STEP1_MASK}, 34 {SPM_BUS_PROTECT_EN_SET, SPM_BUS_PROTECT_RDY_STA, UFS0_PROT_STEP1_MASK}, 35 {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK}, 36 }; 37 38 static const struct bus_protect ufs0_bus_prot_clr_table[] = { 39 {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PROT_STEP1_MASK}, 40 {SPM_BUS_PROTECT_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK}, 41 {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK}, 42 }; 43 44 static const struct bus_protect ufs0_phy_bus_prot_set_table[] = { 45 {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 46 {SPM_BUS_PROTECT_EN_SET, SPM_BUS_PROTECT_RDY_STA, UFS0_PHY_PROT_STEP1_MASK}, 47 {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 48 }; 49 50 static const struct bus_protect ufs0_phy_bus_prot_clr_table[] = { 51 {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 52 {SPM_BUS_PROTECT_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 53 {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 54 }; 55 56 #endif /* PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ */ 57