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/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/clock/
H A Drockchip.txt57 clocks = <&xin24m>, <&xin24m>,
58 <&xin24m>, <&dummy>,
59 <&dummy>, <&xin24m>,
60 <&xin24m>, <&dummy>,
61 <&xin24m>, <&dummy>,
62 <&xin24m>, <&dummy>,
63 <&xin24m>, <&dummy>,
64 <&xin24m>, <&dummy>;
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3562.c80 PNAME(mux_pll_p) = { "xin24m" };
84 PNAME(gpll_cpll_hpll_xin24m_p) = { "gpll", "cpll", "hpll", "xin24m" };
87 PNAME(gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
88 PNAME(gpll_cpll_xin24m_dmyapll_p) = { "gpll", "cpll", "xin24m", "dummy_apll" };
89 PNAME(gpll_cpll_xin24m_dmyhpll_p) = { "gpll", "cpll", "xin24m", "dummy_hpll" };
91 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
92 PNAME(mux_50m_xin24m_p) = { "clk_matrix_50m_src", "xin24m" };
93 PNAME(mux_100m_50m_xin24m_p) = { "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" };
94 PNAME(mux_125m_xin24m_p) = { "clk_matrix_125m_src", "xin24m" };
95 PNAME(mux_200m_xin24m_32k_p) = { "clk_200m_pmu", "xin24m", "clk_rtc_32k" };
[all …]
H A Dclk-rv1106.c216 PNAME(mux_pll_p) = { "xin24m" };
217 PNAME(mux_24m_32k_p) = { "xin24m", "clk_rtc_32k" };
219 PNAME(mux_gpll_24m_p) = { "gpll", "xin24m" };
220 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
221 PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
222 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
226 PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
227 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
228 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
229 PNAME(mux_500m_300m_200m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_200m_src", "xin24m" };
[all …]
H A Dclk-rk3568.c213 PNAME(mux_pll_p) = { "xin24m" };
214 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
224 PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
225 PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
226 PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
227 PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
228 PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
229 PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
230 PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
231 PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
[all …]
H A Dclk-rk3528.c137 PNAME(mux_pll_p) = { "xin24m" };
138 PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
140 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
141 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
142 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" };
143 PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src", "xin24m" };
144 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m"…
145 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m…
146 PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", "clk_100m_src", "xin24m…
147 PNAME(mux_500m_200m_100m_24m_p) = { "clk_500m_src", "clk_200m_src", "clk_100m_src", "xin24m…
[all …]
H A Dclk-rk3588.c423 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
424 PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" };
425 PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",};
426 PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",};
428 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
433 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"};
437 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
446 PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" };
447 PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" };
448 PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" };
[all …]
H A Dclk-rk1808.c131 PNAME(mux_pll_p) = { "xin24m", "xin32k"};
132 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "xin32k" };
139 PNAME(mux_dclk_vopraw_p) = { "dclk_vopraw_src", "dclk_vopraw_frac", "xin24m" };
140 PNAME(mux_dclk_voplite_p) = { "dclk_voplite_src", "dclk_voplite_frac", "xin24m" };
141 PNAME(mux_24m_npll_gpll_usb480m_p) = { "xin24m", "npll", "gpll", "usb480m" };
142 PNAME(mux_usb3_otg0_suspend_p) = { "xin32k", "xin24m" };
143 PNAME(mux_pcie_aux_p) = { "xin24m", "clk_pcie_src" };
144 PNAME(mux_gpll_cpll_npll_24m_p) = { "gpll", "cpll", "npll", "xin24m" };
154 PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac", "xin24m" };
155 PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac", "xin24m" };
[all …]
H A Dclk-rv1126.c152 PNAME(mux_pll_p) = { "xin24m" };
156 PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
157 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
158 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
159 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
163 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
165 PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
166 PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
167 PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
168 PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
[all …]
H A Dclk-rk3368.c110 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
135 PNAME(mux_edp_24m_p) = { "xin24m", "dummy" };
136 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
137 PNAME(mux_usbphy480m_p) = { "usbotg_out", "xin24m" };
140 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
141 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
142 PNAME(mux_uart2_p) = { "uart2_src", "xin24m" };
143 PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
144 PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
146 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "usbphy_480m", "xin24m" };
[all …]
H A Dclk-rk3399.c128 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
158 "xin24m" };
164 "upll", "xin24m" };
166 "ppll", "upll", "xin24m" };
176 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
212 "xin24m" };
218 "upll", "xin24m" };
220 "ppll", "upll", "xin24m" };
230 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
253 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
[all …]
H A Dclk-rk3288.c197 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
207 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
212 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
213 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
214 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
215 PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
216 PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
217 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
220 PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
226 "xin24m", "xin27m", "xin32k", "clk_wifi",
[all …]
H A Dclk-rk3128.c133 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
136 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
144 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
145 PNAME(mux_clk_cif_out_src_p) = { "sclk_cif_src", "xin24m" };
153 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
154 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
155 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
158 PNAME(mux_sclk_sfc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
207 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
292 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
[all …]
H A Dclk-rv1108.c121 PNAME(mux_pll_p) = { "xin24m", "xin24m"};
123 PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
124 PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
131 PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
133 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
134 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
135 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
141 PNAME(mux_wifi_src_p) = { "gpll", "xin24m" };
143 PNAME(mux_cifout_p) = { "sclk_cifout_src", "xin24m" };
149 PNAME(mux_dclk_hdmiphy_p) = { "hdmiphy", "xin24m" };
[all …]
H A Dclk-rk3228.c134 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
138 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
139 PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
145 PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
147 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
161 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
162 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
163 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
217 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
330 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
[all …]
H A Dclk-px30.c141 PNAME(mux_pll_p) = { "xin24m"};
142 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
151 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
152 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll"};
154 PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "dummy_npll", "xin24m" };
155 PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "dummy_npll"};
167 PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "dummy_npll" };
173 PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "dummy_npll", "usb480m" };
174 PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
175 PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
[all …]
H A Dclk-rk3308.c125 PNAME(mux_pll_p) = { "xin24m" };
126 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
128 PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
130 PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = { "dpll", "vpll0", "vpll1", "xin24m" };
131 PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
133 PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" };
139 PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
148 PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_usbphy_ref_src" };
180 PNAME(mux_uart_src_p) = { "usb480m", "xin24m", "dpll", "vpll0", "vpll1" };
290 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
[all …]
H A Dclk-rk3328.c145 PNAME(mux_pll_p) = { "xin24m" };
150 PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
159 "xin24m", "usb480m" };
166 PNAME(mux_hdmiphy_p) = { "hdmi_phy", "xin24m" };
168 "xin24m" };
190 "xin24m" };
193 "xin24m" };
196 "xin24m" };
199 "xin24m" };
205 PNAME(mux_ref_usb3otg_src_p) = { "xin24m",
[all …]
H A Dclk-rk3188.c200 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
205 PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
208 PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
209 PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" };
210 PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" };
211 PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" };
344 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
350 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
352 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
373 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
[all …]
H A Dclk-rk3036.c120 PNAME(mux_pll_p) = { "xin24m", "xin24m" };
127 PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
130 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
132 PNAME(mux_mmc_src_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
136 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
137 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
138 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
183 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
392 /* xin24m gates */
393 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk1808-fpga.dts33 clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>;
48 clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>;
H A Drk3399-fpga.dts26 clocks = <&xin24m>, <&xin24m>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drv1109-fpga.dts95 clocks = <&xin24m>, <&xin24m>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1108.dtsi117 xin24m: oscillator { label
120 clock-output-names = "xin24m";
407 clocks = <&xin24m>;
420 clocks = <&xin24m>;
433 clocks = <&xin24m>;
446 clocks = <&xin24m>;
H A Drk3308.dtsi119 xin24m: xin24m { label
123 clock-output-names = "xin24m";
567 clocks = <&xin24m>;
580 clocks = <&xin24m>;
593 clocks = <&xin24m>;
606 clocks = <&xin24m>;
619 clocks = <&xin24m>;
H A D.rk3308-evb.dtb.dts.tmp

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