Lines Matching full:xin24m
216 PNAME(mux_pll_p) = { "xin24m" };
217 PNAME(mux_24m_32k_p) = { "xin24m", "clk_rtc_32k" };
219 PNAME(mux_gpll_24m_p) = { "gpll", "xin24m" };
220 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
221 PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
222 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
226 PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
227 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
228 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
229 PNAME(mux_500m_300m_200m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_200m_src", "xin24m" };
230 PNAME(mux_50m_24m_p) = { "clk_50m_src", "xin24m" };
231 PNAME(mux_400m_24m_p) = { "clk_400m_src", "xin24m" };
233 PNAME(mux_200m_100m_24m_32k_p) = { "clk_200m_src", "clk_100m_src", "xin24m", "clk_rtc_32k" };
234 PNAME(mux_100m_pmu_24m_p) = { "clk_100m_pmu", "xin24m" };
235 PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_pmu", "xin24m" };
236 PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", "clk_100m_pmu", "xin24m" };
241 PNAME(clk_ref_mipi0_p) = { "clk_ref_mipi0_src", "clk_ref_mipi0_frac", "xin24m" };
242 PNAME(clk_ref_mipi1_p) = { "clk_ref_mipi1_src", "clk_ref_mipi1_frac", "xin24m" };
243 PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
244 PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
245 PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
246 PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
247 PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
248 PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
249 PNAME(clk_vicap_m0_p) = { "clk_vicap_m0_src", "clk_vicap_m0_frac", "xin24m" };
250 PNAME(clk_vicap_m1_p) = { "clk_vicap_m1_src", "clk_vicap_m1_frac", "xin24m" };
325 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
328 GATE(CLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
330 GATE(CLK_CORE_MCU_RTC, "clk_core_mcu_rtc", "xin24m", 0,
509 GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
581 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
616 GATE(CLK_CAPTURE_PWM0_PERI, "clk_capture_pwm0_peri", "xin24m", 0,
618 GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
634 GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
641 GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
651 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
693 GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
697 GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
701 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
705 GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
709 COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
721 GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL,
741 GATE(CLK_PMU_MCU_RTC, "clk_pmu_mcu_rtc", "xin24m", 0,
743 COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
748 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
792 GATE(CLK_UART_DETN_FLT, "clk_uart_detn_flt", "xin24m", 0,
806 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
833 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
849 GATE(CLK_SDMMC_DETN_FLT, "clk_sdmmc_detn_flt", "xin24m", 0,
882 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
892 GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
894 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
898 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
900 COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
905 GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", 0,
907 COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", 0,
928 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
931 COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,