1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/syscore_ops.h>
13 #include <dt-bindings/clock/rv1126-cru.h>
14 #include "clk.h"
15
16 #define RV1126_GMAC_CON 0x460
17 #define RV1126_GRF_IOFUNC_CON1 0x10264
18 #define RV1126_GRF_SOC_STATUS0 0x10
19 #define RV1126_PMUGRF_SOC_CON0 0x100
20
21 #define RV1126_FRAC_MAX_PRATE 1200000000
22 #define RV1126_CSIOUT_FRAC_MAX_PRATE 300000000
23
24 enum rv1126_pmu_plls {
25 gpll,
26 };
27
28 enum rv1126_plls {
29 apll, dpll, cpll, hpll,
30 };
31
32 static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
37 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
38 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
39 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
40 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
41 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
42 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
43 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
44 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
45 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
46 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
47 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
48 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
49 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
50 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
51 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
52 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
53 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
54 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
55 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
56 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
57 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
58 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
59 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
60 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
61 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
62 RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
63 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
64 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
65 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
66 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
67 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
68 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
69 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
70 RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
71 #ifdef CONFIG_ROCKCHIP_LOW_PERFORMANCE
72 RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
73 #else
74 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
75 #endif
76 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
77 RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
78 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
79 RK3036_PLL_RATE(496742400, 1, 124, 6, 1, 0, 3113851),
80 RK3036_PLL_RATE(491520000, 1, 40, 2, 1, 0, 16106127),
81 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
82 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
83 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
84 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
85 { /* sentinel */ },
86 };
87
88 #define RV1126_DIV_ACLK_CORE_MASK 0xf
89 #define RV1126_DIV_ACLK_CORE_SHIFT 4
90 #define RV1126_DIV_PCLK_DBG_MASK 0x7
91 #define RV1126_DIV_PCLK_DBG_SHIFT 0
92
93 #define RV1126_CLKSEL1(_aclk_core, _pclk_dbg) \
94 { \
95 .reg = RV1126_CLKSEL_CON(1), \
96 .val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK, \
97 RV1126_DIV_ACLK_CORE_SHIFT) | \
98 HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK, \
99 RV1126_DIV_PCLK_DBG_SHIFT), \
100 }
101
102 #define RV1126_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
103 { \
104 .prate = _prate, \
105 .divs = { \
106 RV1126_CLKSEL1(_aclk_core, _pclk_dbg), \
107 }, \
108 }
109
110 static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {
111 RV1126_CPUCLK_RATE(1608000000, 1, 7),
112 RV1126_CPUCLK_RATE(1584000000, 1, 7),
113 RV1126_CPUCLK_RATE(1560000000, 1, 7),
114 RV1126_CPUCLK_RATE(1536000000, 1, 7),
115 RV1126_CPUCLK_RATE(1512000000, 1, 7),
116 RV1126_CPUCLK_RATE(1488000000, 1, 5),
117 RV1126_CPUCLK_RATE(1464000000, 1, 5),
118 RV1126_CPUCLK_RATE(1440000000, 1, 5),
119 RV1126_CPUCLK_RATE(1416000000, 1, 5),
120 RV1126_CPUCLK_RATE(1392000000, 1, 5),
121 RV1126_CPUCLK_RATE(1368000000, 1, 5),
122 RV1126_CPUCLK_RATE(1344000000, 1, 5),
123 RV1126_CPUCLK_RATE(1320000000, 1, 5),
124 RV1126_CPUCLK_RATE(1296000000, 1, 5),
125 RV1126_CPUCLK_RATE(1272000000, 1, 5),
126 RV1126_CPUCLK_RATE(1248000000, 1, 5),
127 RV1126_CPUCLK_RATE(1224000000, 1, 5),
128 RV1126_CPUCLK_RATE(1200000000, 1, 5),
129 RV1126_CPUCLK_RATE(1104000000, 1, 5),
130 RV1126_CPUCLK_RATE(1008000000, 1, 5),
131 RV1126_CPUCLK_RATE(912000000, 1, 5),
132 RV1126_CPUCLK_RATE(816000000, 1, 3),
133 RV1126_CPUCLK_RATE(696000000, 1, 3),
134 RV1126_CPUCLK_RATE(600000000, 1, 3),
135 RV1126_CPUCLK_RATE(408000000, 1, 1),
136 RV1126_CPUCLK_RATE(312000000, 1, 1),
137 RV1126_CPUCLK_RATE(216000000, 1, 1),
138 RV1126_CPUCLK_RATE(96000000, 1, 1),
139 };
140
141 static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
142 .core_reg[0] = RV1126_CLKSEL_CON(0),
143 .div_core_shift[0] = 0,
144 .div_core_mask[0] = 0x1f,
145 .num_cores = 1,
146 .mux_core_alt = 0,
147 .mux_core_main = 2,
148 .mux_core_shift = 6,
149 .mux_core_mask = 0x3,
150 };
151
152 PNAME(mux_pll_p) = { "xin24m" };
153 PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
154 PNAME(mux_clk_32k_ioe_p) = { "xin32k", "clk_rtc32k" };
155 PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
156 PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
157 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
158 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
159 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
160 PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
161 PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
162 PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" };
163 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
164 PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
165 PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
166 PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
167 PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
168 PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
169 PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
170 PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
171 PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
172 PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" };
173 PNAME(mux_i2s0_rx_out2io_p) = { "mclk_i2s0_rx", "xin12m" };
174 PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
175 PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" };
176 PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
177 PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
178 PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
179 PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
180 PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
181 PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
182 PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
183 PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
184 PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
185 PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_np5" };
186 PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_np5" };
187 PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
188 PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
189 PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
190 PNAME(mux_clk_gmac_src_p) = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
191 PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
192 PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
193 PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" };
194 PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" };
195 PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
196 PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
197
198
199 #ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
200 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
201 PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
202 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
203 PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
204 PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
205 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
206 PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
207 PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
208 PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
209 PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
210 #else
211 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "dummy_cpll", "xin24m" };
212 PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "dummy_cpll", "dummy_dpll" };
213 PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
214 PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "dummy_cpll", "usb480m", "xin24m" };
215 PNAME(mux_cpll_gpll_p) = { "dummy_cpll", "gpll" };
216 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "dummy_cpll", "xin24m" };
217 PNAME(mux_cpll_hpll_gpll_p) = { "dummy_cpll", "dummy_hpll", "gpll" };
218 PNAME(mux_cpll_gpll_hpll_p) = { "dummy_cpll", "gpll", "dummy_hpll" };
219 PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "dummy_cpll", "dummy_hpll" };
220 PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "dummy_cpll", "dummy_apll", "dummy_hpll" };
221 #endif
222
223 static u32 rgmii_mux_idx[] = { 2, 3, 0, 1 };
224
225 static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = {
226 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
227 CLK_IS_CRITICAL, RV1126_PMU_PLL_CON(0),
228 RV1126_PMU_MODE, 0, 3, 0, rv1126_pll_rates),
229 };
230
231 static struct rockchip_pll_clock rv1126_pll_clks[] __initdata = {
232 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
233 CLK_IGNORE_UNUSED, RV1126_PLL_CON(0),
234 RV1126_MODE_CON, 0, 0, 0, rv1126_pll_rates),
235 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
236 CLK_IGNORE_UNUSED, RV1126_PLL_CON(8),
237 RV1126_MODE_CON, 2, 1, 0, NULL),
238 #ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
239 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
240 CLK_IS_CRITICAL, RV1126_PLL_CON(16),
241 RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
242 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
243 CLK_IS_CRITICAL, RV1126_PLL_CON(24),
244 RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
245 #else
246 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
247 0, RV1126_PLL_CON(16),
248 RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
249 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
250 0, RV1126_PLL_CON(24),
251 RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
252 #endif
253 };
254
255 #define MFLAGS CLK_MUX_HIWORD_MASK
256 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
257 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
258
259 static struct rockchip_clk_branch rv1126_rtc32k_fracmux __initdata =
260 MUX(CLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
261 RV1126_PMU_CLKSEL_CON(0), 7, 2, MFLAGS);
262
263 static struct rockchip_clk_branch rv1126_uart1_fracmux __initdata =
264 MUX(SCLK_UART1_MUX, "sclk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
265 RV1126_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
266
267 static struct rockchip_clk_branch rv1126_uart0_fracmux __initdata =
268 MUX(SCLK_UART0_MUX, "sclk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
269 RV1126_CLKSEL_CON(10), 10, 2, MFLAGS);
270
271 static struct rockchip_clk_branch rv1126_uart2_fracmux __initdata =
272 MUX(SCLK_UART2_MUX, "sclk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
273 RV1126_CLKSEL_CON(12), 10, 2, MFLAGS);
274
275 static struct rockchip_clk_branch rv1126_uart3_fracmux __initdata =
276 MUX(SCLK_UART3_MUX, "sclk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
277 RV1126_CLKSEL_CON(14), 10, 2, MFLAGS);
278
279 static struct rockchip_clk_branch rv1126_uart4_fracmux __initdata =
280 MUX(SCLK_UART4_MUX, "sclk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
281 RV1126_CLKSEL_CON(16), 10, 2, MFLAGS);
282
283 static struct rockchip_clk_branch rv1126_uart5_fracmux __initdata =
284 MUX(SCLK_UART5_MUX, "sclk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
285 RV1126_CLKSEL_CON(18), 10, 2, MFLAGS);
286
287 static struct rockchip_clk_branch rv1126_i2s0_tx_fracmux __initdata =
288 MUX(MCLK_I2S0_TX_MUX, "mclk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
289 RV1126_CLKSEL_CON(30), 0, 2, MFLAGS);
290
291 static struct rockchip_clk_branch rv1126_i2s0_rx_fracmux __initdata =
292 MUX(MCLK_I2S0_RX_MUX, "mclk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
293 RV1126_CLKSEL_CON(30), 2, 2, MFLAGS);
294
295 static struct rockchip_clk_branch rv1126_i2s1_fracmux __initdata =
296 MUX(MCLK_I2S1_MUX, "mclk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
297 RV1126_CLKSEL_CON(31), 8, 2, MFLAGS);
298
299 static struct rockchip_clk_branch rv1126_i2s2_fracmux __initdata =
300 MUX(MCLK_I2S2_MUX, "mclk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
301 RV1126_CLKSEL_CON(33), 8, 2, MFLAGS);
302
303 static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
304 MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
305 RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
306
307 static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata =
308 MUX(DCLK_VOP_MUX, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
309 RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
310
311 static struct rockchip_clk_branch rv1126_cif_out2io_fracmux __initdata =
312 MUX(CLK_CIF_OUT_MUX, "clk_cif_out2io_mux", mux_cif_out2io_p, CLK_SET_RATE_PARENT,
313 RV1126_CLKSEL_CON(50), 14, 2, MFLAGS);
314
315 static struct rockchip_clk_branch rv1126_mipicsi_out2io_fracmux __initdata =
316 MUX(CLK_MIPICSI_OUT_MUX, "clk_mipicsi_out2io_mux", mux_mipicsi_out2io_p, CLK_SET_RATE_PARENT,
317 RV1126_CLKSEL_CON(73), 10, 2, MFLAGS);
318
319 static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
320 /*
321 * Clock-Architecture Diagram 2
322 */
323 /* PD_PMU */
324 COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "gpll", CLK_IS_CRITICAL,
325 RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
326 RV1126_PMU_CLKGATE_CON(0), 0, GFLAGS),
327
328 COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
329 RV1126_PMU_CLKSEL_CON(13), 0,
330 RV1126_PMU_CLKGATE_CON(2), 9, GFLAGS,
331 &rv1126_rtc32k_fracmux),
332
333 MUXPMUGRF(CLK_32K_IOE, "clk_32k_ioe", mux_clk_32k_ioe_p, 0,
334 RV1126_PMUGRF_SOC_CON0, 0, 1, MFLAGS),
335
336 COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "gpll", 0,
337 RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
338 RV1126_PMU_CLKGATE_CON(2), 10, GFLAGS),
339 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
340 RV1126_PMU_CLKGATE_CON(2), 11, GFLAGS),
341 MUX(CLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
342 RV1126_PMU_CLKSEL_CON(12), 8, 1, MFLAGS),
343
344 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
345 RV1126_PMU_CLKGATE_CON(0), 1, GFLAGS),
346
347 GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
348 RV1126_PMU_CLKGATE_CON(0), 11, GFLAGS),
349 COMPOSITE(SCLK_UART1_DIV, "sclk_uart1_div", mux_gpll_usb480m_cpll_xin24m_p, 0,
350 RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
351 RV1126_PMU_CLKGATE_CON(0), 12, GFLAGS),
352 COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div", CLK_SET_RATE_PARENT,
353 RV1126_PMU_CLKSEL_CON(5), 0,
354 RV1126_PMU_CLKGATE_CON(0), 13, GFLAGS,
355 &rv1126_uart1_fracmux),
356 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
357 RV1126_PMU_CLKGATE_CON(0), 14, GFLAGS),
358
359 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
360 RV1126_PMU_CLKGATE_CON(0), 5, GFLAGS),
361 COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "gpll", 0,
362 RV1126_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
363 RV1126_PMU_CLKGATE_CON(0), 6, GFLAGS),
364 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
365 RV1126_PMU_CLKGATE_CON(0), 9, GFLAGS),
366 COMPOSITE_NOMUX(CLK_I2C2, "clk_i2c2", "gpll", 0,
367 RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
368 RV1126_PMU_CLKGATE_CON(0), 10, GFLAGS),
369
370 GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
371 RV1126_PMU_CLKGATE_CON(1), 2, GFLAGS),
372 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
373 RV1126_PMU_CLKGATE_CON(1), 0, GFLAGS),
374 COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,
375 RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
376 RV1126_PMU_CLKGATE_CON(1), 1, GFLAGS),
377 GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
378 RV1126_PMU_CLKGATE_CON(1), 5, GFLAGS),
379 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
380 RV1126_PMU_CLKGATE_CON(1), 3, GFLAGS),
381 COMPOSITE(CLK_PWM1, "clk_pwm1", mux_xin24m_gpll_p, 0,
382 RV1126_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 7, DFLAGS,
383 RV1126_PMU_CLKGATE_CON(1), 4, GFLAGS),
384
385 GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
386 RV1126_PMU_CLKGATE_CON(1), 11, GFLAGS),
387 COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
388 RV1126_PMU_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 7, DFLAGS,
389 RV1126_PMU_CLKGATE_CON(1), 12, GFLAGS),
390
391 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
392 RV1126_PMU_CLKGATE_CON(1), 9, GFLAGS),
393 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,
394 RV1126_PMU_CLKSEL_CON(8), 15, 1, MFLAGS,
395 RV1126_PMU_CLKGATE_CON(1), 10, GFLAGS),
396
397 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
398 RV1126_PMU_CLKGATE_CON(2), 6, GFLAGS),
399 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
400 RV1126_PMU_CLKGATE_CON(2), 5, GFLAGS),
401 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
402 RV1126_PMU_CLKGATE_CON(2), 7, GFLAGS),
403
404 COMPOSITE_NOMUX(CLK_REF12M, "clk_ref12m", "gpll", 0,
405 RV1126_PMU_CLKSEL_CON(7), 8, 7, DFLAGS,
406 RV1126_PMU_CLKGATE_CON(1), 15, GFLAGS),
407 GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
408 RV1126_PMU_CLKGATE_CON(1), 6, GFLAGS),
409 GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
410 RV1126_PMU_CLKGATE_CON(1), 7, GFLAGS),
411 FACTOR(0, "xin_osc0_div2_usbphyref_otg", "xin_osc0_usbphyref_otg", 0, 1, 2),
412 FACTOR(0, "xin_osc0_div2_usbphyref_host", "xin_osc0_usbphyref_host", 0, 1, 2),
413 MUX(CLK_USBPHY_OTG_REF, "clk_usbphy_otg_ref", mux_usbphy_otg_ref_p, CLK_SET_RATE_PARENT,
414 RV1126_PMU_CLKSEL_CON(7), 6, 1, MFLAGS),
415 MUX(CLK_USBPHY_HOST_REF, "clk_usbphy_host_ref", mux_usbphy_host_ref_p, CLK_SET_RATE_PARENT,
416 RV1126_PMU_CLKSEL_CON(7), 7, 1, MFLAGS),
417
418 COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "gpll", 0,
419 RV1126_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
420 RV1126_PMU_CLKGATE_CON(1), 14, GFLAGS),
421 GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
422 RV1126_PMU_CLKGATE_CON(1), 8, GFLAGS),
423 MUX(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
424 RV1126_PMU_CLKSEL_CON(7), 15, 1, MFLAGS),
425
426 #ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
427 GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
428 RV1126_PMU_CLKGATE_CON(0), 15, GFLAGS),
429
430 GATE(PCLK_PMUSGRF, "pclk_pmusgrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
431 RV1126_PMU_CLKGATE_CON(0), 4, GFLAGS),
432 GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
433 RV1126_PMU_CLKGATE_CON(1), 13, GFLAGS),
434 GATE(PCLK_PMUCRU, "pclk_pmucru", "pclk_pdpmu", CLK_IGNORE_UNUSED,
435 RV1126_PMU_CLKGATE_CON(2), 4, GFLAGS),
436 GATE(PCLK_CHIPVEROTP, "pclk_chipverotp", "pclk_pdpmu", CLK_IGNORE_UNUSED,
437 RV1126_PMU_CLKGATE_CON(2), 0, GFLAGS),
438 GATE(PCLK_PDPMU_NIU, "pclk_pdpmu_niu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
439 RV1126_PMU_CLKGATE_CON(0), 2, GFLAGS),
440
441 GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pdpmu", 0,
442 RV1126_PMU_CLKGATE_CON(0), 7, GFLAGS),
443 #endif
444 };
445
446 static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
447 /*
448 * Clock-Architecture Diagram 1
449 */
450 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
451 RV1126_MODE_CON, 10, 2, MFLAGS),
452 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
453
454 /*
455 * Clock-Architecture Diagram 3
456 */
457 /* PD_CORE */
458 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
459 RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
460 RV1126_CLKGATE_CON(0), 6, GFLAGS),
461 GATE(CLK_CORE_CPUPVTM, "clk_core_cpupvtm", "armclk", 0,
462 RV1126_CLKGATE_CON(0), 12, GFLAGS),
463 GATE(PCLK_CPUPVTM, "pclk_cpupvtm", "pclk_dbg", 0,
464 RV1126_CLKGATE_CON(0), 10, GFLAGS),
465 GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
466 RV1126_CLKGATE_CON(0), 11, GFLAGS),
467 COMPOSITE_NOMUX(HCLK_PDCORE_NIU, "hclk_pdcore_niu", "gpll", CLK_IGNORE_UNUSED,
468 RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
469 RV1126_CLKGATE_CON(0), 8, GFLAGS),
470
471 /*
472 * Clock-Architecture Diagram 4
473 */
474 /* PD_BUS */
475 COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IS_CRITICAL,
476 RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
477 RV1126_CLKGATE_CON(2), 0, GFLAGS),
478 GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IS_CRITICAL,
479 RV1126_CLKGATE_CON(2), 11, GFLAGS),
480 COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IS_CRITICAL,
481 RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
482 RV1126_CLKGATE_CON(2), 1, GFLAGS),
483 GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IS_CRITICAL,
484 RV1126_CLKGATE_CON(2), 12, GFLAGS),
485 COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IS_CRITICAL,
486 RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
487 RV1126_CLKGATE_CON(2), 2, GFLAGS),
488 GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IS_CRITICAL,
489 RV1126_CLKGATE_CON(2), 13, GFLAGS),
490 /* aclk_dmac is controlled by sgrf_clkgat_con. */
491 SGRF_GATE(ACLK_DMAC, "aclk_dmac", "hclk_pdbus"),
492 GATE(ACLK_DCF, "aclk_dcf", "hclk_pdbus", CLK_IGNORE_UNUSED,
493 RV1126_CLKGATE_CON(3), 6, GFLAGS),
494 GATE(PCLK_DCF, "pclk_dcf", "pclk_pdbus", CLK_IGNORE_UNUSED,
495 RV1126_CLKGATE_CON(3), 7, GFLAGS),
496 GATE(PCLK_WDT, "pclk_wdt", "pclk_pdbus", 0,
497 RV1126_CLKGATE_CON(6), 14, GFLAGS),
498 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_pdbus", 0,
499 RV1126_CLKGATE_CON(7), 10, GFLAGS),
500
501 COMPOSITE(CLK_SCR1, "clk_scr1", mux_gpll_cpll_p, 0,
502 RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
503 RV1126_CLKGATE_CON(4), 7, GFLAGS),
504 GATE(0, "clk_scr1_niu", "clk_scr1", CLK_IGNORE_UNUSED,
505 RV1126_CLKGATE_CON(2), 14, GFLAGS),
506 GATE(CLK_SCR1_CORE, "clk_scr1_core", "clk_scr1", 0,
507 RV1126_CLKGATE_CON(4), 8, GFLAGS),
508 GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
509 RV1126_CLKGATE_CON(4), 9, GFLAGS),
510 GATE(CLK_SCR1_JTAG, "clk_scr1_jtag", "clk_scr1_jtag_io", 0,
511 RV1126_CLKGATE_CON(4), 10, GFLAGS),
512
513 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdbus", 0,
514 RV1126_CLKGATE_CON(5), 0, GFLAGS),
515 COMPOSITE(SCLK_UART0_DIV, "sclk_uart0_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
516 RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
517 RV1126_CLKGATE_CON(5), 1, GFLAGS),
518 COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
519 RV1126_CLKSEL_CON(11), 0,
520 RV1126_CLKGATE_CON(5), 2, GFLAGS,
521 &rv1126_uart0_fracmux),
522 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
523 RV1126_CLKGATE_CON(5), 3, GFLAGS),
524 GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
525 RV1126_CLKGATE_CON(5), 4, GFLAGS),
526 COMPOSITE(SCLK_UART2_DIV, "sclk_uart2_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
527 RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
528 RV1126_CLKGATE_CON(5), 5, GFLAGS),
529 COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", CLK_SET_RATE_PARENT,
530 RV1126_CLKSEL_CON(13), 0,
531 RV1126_CLKGATE_CON(5), 6, GFLAGS,
532 &rv1126_uart2_fracmux),
533 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
534 RV1126_CLKGATE_CON(5), 7, GFLAGS),
535 GATE(PCLK_UART3, "pclk_uart3", "pclk_pdbus", 0,
536 RV1126_CLKGATE_CON(5), 8, GFLAGS),
537 COMPOSITE(SCLK_UART3_DIV, "sclk_uart3_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
538 RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
539 RV1126_CLKGATE_CON(5), 9, GFLAGS),
540 COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", CLK_SET_RATE_PARENT,
541 RV1126_CLKSEL_CON(15), 0,
542 RV1126_CLKGATE_CON(5), 10, GFLAGS,
543 &rv1126_uart3_fracmux),
544 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
545 RV1126_CLKGATE_CON(5), 11, GFLAGS),
546 GATE(PCLK_UART4, "pclk_uart4", "pclk_pdbus", 0,
547 RV1126_CLKGATE_CON(5), 12, GFLAGS),
548 COMPOSITE(SCLK_UART4_DIV, "sclk_uart4_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
549 RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
550 DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
551 COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", CLK_SET_RATE_PARENT,
552 RV1126_CLKSEL_CON(17), 0,
553 RV1126_CLKGATE_CON(5), 14, GFLAGS,
554 &rv1126_uart4_fracmux),
555 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
556 RV1126_CLKGATE_CON(5), 15, GFLAGS),
557 GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
558 RV1126_CLKGATE_CON(6), 0, GFLAGS),
559 COMPOSITE(SCLK_UART5_DIV, "sclk_uart5_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
560 RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
561 DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
562 COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", CLK_SET_RATE_PARENT,
563 RV1126_CLKSEL_CON(19), 0,
564 RV1126_CLKGATE_CON(6), 2, GFLAGS,
565 &rv1126_uart5_fracmux),
566 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
567 RV1126_CLKGATE_CON(6), 3, GFLAGS),
568
569 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pdbus", 0,
570 RV1126_CLKGATE_CON(3), 10, GFLAGS),
571 COMPOSITE_NOMUX(CLK_I2C1, "clk_i2c1", "gpll", 0,
572 RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
573 RV1126_CLKGATE_CON(3), 11, GFLAGS),
574 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_pdbus", 0,
575 RV1126_CLKGATE_CON(3), 12, GFLAGS),
576 COMPOSITE_NOMUX(CLK_I2C3, "clk_i2c3", "gpll", 0,
577 RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
578 RV1126_CLKGATE_CON(3), 13, GFLAGS),
579 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_pdbus", 0,
580 RV1126_CLKGATE_CON(3), 14, GFLAGS),
581 COMPOSITE_NOMUX(CLK_I2C4, "clk_i2c4", "gpll", 0,
582 RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
583 RV1126_CLKGATE_CON(3), 15, GFLAGS),
584 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_pdbus", 0,
585 RV1126_CLKGATE_CON(4), 0, GFLAGS),
586 COMPOSITE_NOMUX(CLK_I2C5, "clk_i2c5", "gpll", 0,
587 RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
588 RV1126_CLKGATE_CON(4), 1, GFLAGS),
589
590 GATE(PCLK_SPI1, "pclk_spi1", "pclk_pdbus", 0,
591 RV1126_CLKGATE_CON(4), 2, GFLAGS),
592 COMPOSITE(CLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
593 RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
594 RV1126_CLKGATE_CON(4), 3, GFLAGS),
595
596 GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
597 RV1126_CLKGATE_CON(4), 6, GFLAGS),
598 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_pdbus", 0,
599 RV1126_CLKGATE_CON(4), 4, GFLAGS),
600 COMPOSITE(CLK_PWM2, "clk_pwm2", mux_xin24m_gpll_p, 0,
601 RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
602 RV1126_CLKGATE_CON(4), 5, GFLAGS),
603
604 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pdbus", 0,
605 RV1126_CLKGATE_CON(7), 0, GFLAGS),
606 COMPOSITE_NODIV(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
607 RV1126_CLKSEL_CON(21), 15, 1, MFLAGS,
608 RV1126_CLKGATE_CON(7), 1, GFLAGS),
609 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pdbus", 0,
610 RV1126_CLKGATE_CON(7), 2, GFLAGS),
611 COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
612 RV1126_CLKSEL_CON(22), 15, 1, MFLAGS,
613 RV1126_CLKGATE_CON(7), 3, GFLAGS),
614 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pdbus", 0,
615 RV1126_CLKGATE_CON(7), 4, GFLAGS),
616 COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
617 RV1126_CLKSEL_CON(23), 15, 1, MFLAGS,
618 RV1126_CLKGATE_CON(7), 5, GFLAGS),
619 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pdbus", 0,
620 RV1126_CLKGATE_CON(7), 6, GFLAGS),
621 COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
622 RV1126_CLKSEL_CON(24), 15, 1, MFLAGS,
623 RV1126_CLKGATE_CON(7), 7, GFLAGS),
624
625 GATE(PCLK_SARADC, "pclk_saradc", "pclk_pdbus", 0,
626 RV1126_CLKGATE_CON(6), 4, GFLAGS),
627 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
628 RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
629 RV1126_CLKGATE_CON(6), 5, GFLAGS),
630
631 GATE(PCLK_TIMER, "pclk_timer", "pclk_pdbus", 0,
632 RV1126_CLKGATE_CON(6), 7, GFLAGS),
633 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
634 RV1126_CLKGATE_CON(6), 8, GFLAGS),
635 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
636 RV1126_CLKGATE_CON(6), 9, GFLAGS),
637 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
638 RV1126_CLKGATE_CON(6), 10, GFLAGS),
639 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
640 RV1126_CLKGATE_CON(6), 11, GFLAGS),
641 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
642 RV1126_CLKGATE_CON(6), 12, GFLAGS),
643 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
644 RV1126_CLKGATE_CON(6), 13, GFLAGS),
645
646 GATE(ACLK_SPINLOCK, "aclk_spinlock", "hclk_pdbus", 0,
647 RV1126_CLKGATE_CON(6), 6, GFLAGS),
648
649 GATE(ACLK_DECOM, "aclk_decom", "aclk_pdbus", 0,
650 RV1126_CLKGATE_CON(7), 11, GFLAGS),
651 GATE(PCLK_DECOM, "pclk_decom", "pclk_pdbus", 0,
652 RV1126_CLKGATE_CON(7), 12, GFLAGS),
653 COMPOSITE(DCLK_DECOM, "dclk_decom", mux_gpll_cpll_p, 0,
654 RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
655 RV1126_CLKGATE_CON(7), 13, GFLAGS),
656
657 GATE(PCLK_CAN, "pclk_can", "pclk_pdbus", 0,
658 RV1126_CLKGATE_CON(7), 8, GFLAGS),
659 COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
660 RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
661 RV1126_CLKGATE_CON(7), 9, GFLAGS),
662 /* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */
663 SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
664 SGRF_GATE(PCLK_OTP, "pclk_otp", "pclk_pdbus"),
665
666 GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
667 RV1126_CLKGATE_CON(24), 3, GFLAGS),
668 COMPOSITE_NOMUX(CLK_NPU_TSADC, "clk_npu_tsadc", "xin24m", 0,
669 RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
670 RV1126_CLKGATE_CON(24), 4, GFLAGS),
671 GATE(CLK_NPU_TSADCPHY, "clk_npu_tsadcphy", "clk_npu_tsadc", 0,
672 RV1126_CLKGATE_CON(24), 5, GFLAGS),
673 GATE(PCLK_CPU_TSADC, "pclk_cpu_tsadc", "pclk_pdbus", 0,
674 RV1126_CLKGATE_CON(24), 0, GFLAGS),
675 COMPOSITE_NOMUX(CLK_CPU_TSADC, "clk_cpu_tsadc", "xin24m", 0,
676 RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
677 RV1126_CLKGATE_CON(24), 1, GFLAGS),
678 GATE(CLK_CPU_TSADCPHY, "clk_cpu_tsadcphy", "clk_cpu_tsadc", 0,
679 RV1126_CLKGATE_CON(24), 2, GFLAGS),
680
681 /*
682 * Clock-Architecture Diagram 5
683 */
684 /* PD_CRYPTO */
685 COMPOSITE(ACLK_PDCRYPTO, "aclk_pdcrypto", mux_gpll_cpll_p, 0,
686 RV1126_CLKSEL_CON(4), 7, 1, MFLAGS, 0, 5, DFLAGS,
687 RV1126_CLKGATE_CON(4), 11, GFLAGS),
688 COMPOSITE_NOMUX(HCLK_PDCRYPTO, "hclk_pdcrypto", "aclk_pdcrypto", 0,
689 RV1126_CLKSEL_CON(4), 8, 5, DFLAGS,
690 RV1126_CLKGATE_CON(4), 12, GFLAGS),
691 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_pdcrypto", 0,
692 RV1126_CLKGATE_CON(3), 2, GFLAGS),
693 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_pdcrypto", 0,
694 RV1126_CLKGATE_CON(3), 3, GFLAGS),
695 COMPOSITE(CLK_CRYPTO_CORE, "aclk_crypto_core", mux_gpll_cpll_p, 0,
696 RV1126_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 5, DFLAGS,
697 RV1126_CLKGATE_CON(3), 4, GFLAGS),
698 COMPOSITE(CLK_CRYPTO_PKA, "aclk_crypto_pka", mux_gpll_cpll_p, 0,
699 RV1126_CLKSEL_CON(7), 15, 1, MFLAGS, 8, 5, DFLAGS,
700 RV1126_CLKGATE_CON(3), 5, GFLAGS),
701
702 /*
703 * Clock-Architecture Diagram 6
704 */
705 /* PD_AUDIO */
706 COMPOSITE_NOMUX(HCLK_PDAUDIO, "hclk_pdaudio", "gpll", 0,
707 RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
708 RV1126_CLKGATE_CON(9), 0, GFLAGS),
709
710 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_pdaudio", 0,
711 RV1126_CLKGATE_CON(9), 4, GFLAGS),
712 COMPOSITE(MCLK_I2S0_TX_DIV, "mclk_i2s0_tx_div", mux_cpll_gpll_p, 0,
713 RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
714 RV1126_CLKGATE_CON(9), 5, GFLAGS),
715 COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div", CLK_SET_RATE_PARENT,
716 RV1126_CLKSEL_CON(28), 0,
717 RV1126_CLKGATE_CON(9), 6, GFLAGS,
718 &rv1126_i2s0_tx_fracmux),
719 GATE(MCLK_I2S0_TX, "mclk_i2s0_tx", "mclk_i2s0_tx_mux", 0,
720 RV1126_CLKGATE_CON(9), 9, GFLAGS),
721 COMPOSITE(MCLK_I2S0_RX_DIV, "mclk_i2s0_rx_div", mux_cpll_gpll_p, 0,
722 RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
723 RV1126_CLKGATE_CON(9), 7, GFLAGS),
724 COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div", CLK_SET_RATE_PARENT,
725 RV1126_CLKSEL_CON(29), 0,
726 RV1126_CLKGATE_CON(9), 8, GFLAGS,
727 &rv1126_i2s0_rx_fracmux),
728 GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
729 RV1126_CLKGATE_CON(9), 10, GFLAGS),
730 COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, CLK_SET_RATE_PARENT,
731 RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
732 RV1126_CLKGATE_CON(9), 13, GFLAGS),
733 COMPOSITE_NODIV(MCLK_I2S0_RX_OUT2IO, "mclk_i2s0_rx_out2io", mux_i2s0_rx_out2io_p, CLK_SET_RATE_PARENT,
734 RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
735 RV1126_CLKGATE_CON(9), 14, GFLAGS),
736
737 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_pdaudio", 0,
738 RV1126_CLKGATE_CON(10), 0, GFLAGS),
739 COMPOSITE(MCLK_I2S1_DIV, "mclk_i2s1_div", mux_cpll_gpll_p, 0,
740 RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
741 RV1126_CLKGATE_CON(10), 1, GFLAGS),
742 COMPOSITE_FRACMUX(MCLK_I2S1_FRACDIV, "mclk_i2s1_fracdiv", "mclk_i2s1_div", CLK_SET_RATE_PARENT,
743 RV1126_CLKSEL_CON(32), 0,
744 RV1126_CLKGATE_CON(10), 2, GFLAGS,
745 &rv1126_i2s1_fracmux),
746 GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
747 RV1126_CLKGATE_CON(10), 3, GFLAGS),
748 COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, CLK_SET_RATE_PARENT,
749 RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
750 RV1126_CLKGATE_CON(10), 4, GFLAGS),
751 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_pdaudio", 0,
752 RV1126_CLKGATE_CON(10), 5, GFLAGS),
753 COMPOSITE(MCLK_I2S2_DIV, "mclk_i2s2_div", mux_cpll_gpll_p, 0,
754 RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
755 RV1126_CLKGATE_CON(10), 6, GFLAGS),
756 COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div", CLK_SET_RATE_PARENT,
757 RV1126_CLKSEL_CON(34), 0,
758 RV1126_CLKGATE_CON(10), 7, GFLAGS,
759 &rv1126_i2s2_fracmux),
760 GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
761 RV1126_CLKGATE_CON(10), 8, GFLAGS),
762 COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, CLK_SET_RATE_PARENT,
763 RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
764 RV1126_CLKGATE_CON(10), 9, GFLAGS),
765
766 GATE(HCLK_PDM, "hclk_pdm", "hclk_pdaudio", 0,
767 RV1126_CLKGATE_CON(10), 10, GFLAGS),
768 COMPOSITE(MCLK_PDM, "mclk_pdm", mux_gpll_cpll_xin24m_p, 0,
769 RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
770 RV1126_CLKGATE_CON(10), 11, GFLAGS),
771
772 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_pdaudio", 0,
773 RV1126_CLKGATE_CON(10), 12, GFLAGS),
774 COMPOSITE(SCLK_ADUPWM_DIV, "sclk_audpwm_div", mux_gpll_cpll_p, 0,
775 RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
776 RV1126_CLKGATE_CON(10), 13, GFLAGS),
777 COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div", CLK_SET_RATE_PARENT,
778 RV1126_CLKSEL_CON(37), 0,
779 RV1126_CLKGATE_CON(10), 14, GFLAGS,
780 &rv1126_audpwm_fracmux),
781 GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,
782 RV1126_CLKGATE_CON(10), 15, GFLAGS),
783
784 GATE(PCLK_ACDCDIG, "pclk_acdcdig", "hclk_pdaudio", 0,
785 RV1126_CLKGATE_CON(11), 0, GFLAGS),
786 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s0_rx", 0,
787 RV1126_CLKGATE_CON(11), 2, GFLAGS),
788 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s0_tx", 0,
789 RV1126_CLKGATE_CON(11), 3, GFLAGS),
790 COMPOSITE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", mux_gpll_xin24m_p, 0,
791 RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
792 RV1126_CLKGATE_CON(11), 1, GFLAGS),
793
794 /*
795 * Clock-Architecture Diagram 7
796 */
797 /* PD_VEPU */
798 COMPOSITE(ACLK_PDVEPU, "aclk_pdvepu", mux_cpll_hpll_gpll_p, 0,
799 RV1126_CLKSEL_CON(40), 6, 2, MFLAGS, 0, 5, DFLAGS,
800 RV1126_CLKGATE_CON(12), 0, GFLAGS),
801 COMPOSITE_NOMUX(HCLK_PDVEPU, "hclk_pdvepu", "aclk_pdvepu", 0,
802 RV1126_CLKSEL_CON(41), 0, 5, DFLAGS,
803 RV1126_CLKGATE_CON(12), 2, GFLAGS),
804 GATE(ACLK_VENC, "aclk_venc", "aclk_pdvepu", 0,
805 RV1126_CLKGATE_CON(12), 5, GFLAGS),
806 GATE(HCLK_VENC, "hclk_venc", "hclk_pdvepu", 0,
807 RV1126_CLKGATE_CON(12), 6, GFLAGS),
808 COMPOSITE(CLK_VENC_CORE, "clk_venc_core", mux_cpll_gpll_hpll_p, 0,
809 RV1126_CLKSEL_CON(40), 14, 2, MFLAGS, 8, 5, DFLAGS,
810 RV1126_CLKGATE_CON(12), 1, GFLAGS),
811
812 /*
813 * Clock-Architecture Diagram 8
814 */
815 /* PD_VDPU */
816 #if IS_ENABLED(CONFIG_ROCKCHIP_MPP_VDPU2) || IS_ENABLED(CONFIG_ROCKCHIP_MPP_RKVDEC)
817 COMPOSITE(ACLK_PDVDEC, "aclk_pdvdec", mux_cpll_hpll_gpll_p, CLK_IS_CRITICAL,
818 RV1126_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
819 RV1126_CLKGATE_CON(13), 0, GFLAGS),
820 COMPOSITE_NOMUX(HCLK_PDVDEC, "hclk_pdvdec", "aclk_pdvdec", CLK_IS_CRITICAL,
821 RV1126_CLKSEL_CON(41), 8, 5, DFLAGS,
822 RV1126_CLKGATE_CON(13), 4, GFLAGS),
823 GATE(0, "aclk_pdvdec_niu", "aclk_pdvdec", CLK_IS_CRITICAL,
824 RV1126_CLKGATE_CON(13), 5, GFLAGS),
825 GATE(0, "hclk_pdvdec_niu", "hclk_pdvdec", CLK_IS_CRITICAL,
826 RV1126_CLKGATE_CON(13), 6, GFLAGS),
827 COMPOSITE(ACLK_PDJPEG, "aclk_pdjpeg", mux_cpll_hpll_gpll_p, CLK_IS_CRITICAL,
828 RV1126_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
829 RV1126_CLKGATE_CON(13), 9, GFLAGS),
830 COMPOSITE_NOMUX(HCLK_PDJPEG, "hclk_pdjpeg", "aclk_pdjpeg", CLK_IS_CRITICAL,
831 RV1126_CLKSEL_CON(44), 8, 5, DFLAGS,
832 RV1126_CLKGATE_CON(13), 10, GFLAGS),
833 GATE(0, "aclk_pdjpeg_niu", "aclk_pdjpeg", CLK_IS_CRITICAL,
834 RV1126_CLKGATE_CON(13), 11, GFLAGS),
835 GATE(0, "hclk_pdjpeg_niu", "hclk_pdjpeg", CLK_IS_CRITICAL,
836 RV1126_CLKGATE_CON(13), 12, GFLAGS),
837 #else
838 COMPOSITE(ACLK_PDVDEC, "aclk_pdvdec", mux_cpll_hpll_gpll_p, 0,
839 RV1126_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
840 RV1126_CLKGATE_CON(13), 0, GFLAGS),
841 COMPOSITE_NOMUX(HCLK_PDVDEC, "hclk_pdvdec", "aclk_pdvdec", 0,
842 RV1126_CLKSEL_CON(41), 8, 5, DFLAGS,
843 RV1126_CLKGATE_CON(13), 4, GFLAGS),
844 GATE(0, "aclk_pdvdec_niu", "aclk_pdvdec", CLK_IGNORE_UNUSED,
845 RV1126_CLKGATE_CON(13), 5, GFLAGS),
846 GATE(0, "hclk_pdvdec_niu", "hclk_pdvdec", CLK_IGNORE_UNUSED,
847 RV1126_CLKGATE_CON(13), 6, GFLAGS),
848 COMPOSITE(ACLK_PDJPEG, "aclk_pdjpeg", mux_cpll_hpll_gpll_p, 0,
849 RV1126_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
850 RV1126_CLKGATE_CON(13), 9, GFLAGS),
851 COMPOSITE_NOMUX(HCLK_PDJPEG, "hclk_pdjpeg", "aclk_pdjpeg", 0,
852 RV1126_CLKSEL_CON(44), 8, 5, DFLAGS,
853 RV1126_CLKGATE_CON(13), 10, GFLAGS),
854 GATE(0, "aclk_pdjpeg_niu", "aclk_pdjpeg", CLK_IGNORE_UNUSED,
855 RV1126_CLKGATE_CON(13), 11, GFLAGS),
856 GATE(0, "hclk_pdjpeg_niu", "hclk_pdjpeg", CLK_IGNORE_UNUSED,
857 RV1126_CLKGATE_CON(13), 12, GFLAGS),
858 #endif
859 GATE(ACLK_VDEC, "aclk_vdec", "aclk_pdvdec", 0,
860 RV1126_CLKGATE_CON(13), 7, GFLAGS),
861 GATE(HCLK_VDEC, "hclk_vdec", "hclk_pdvdec", 0,
862 RV1126_CLKGATE_CON(13), 8, GFLAGS),
863 COMPOSITE(CLK_VDEC_CORE, "clk_vdec_core", mux_cpll_hpll_gpll_p, 0,
864 RV1126_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
865 RV1126_CLKGATE_CON(13), 1, GFLAGS),
866 COMPOSITE(CLK_VDEC_CA, "clk_vdec_ca", mux_cpll_hpll_gpll_p, 0,
867 RV1126_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
868 RV1126_CLKGATE_CON(13), 2, GFLAGS),
869 COMPOSITE(CLK_VDEC_HEVC_CA, "clk_vdec_hevc_ca", mux_cpll_hpll_gpll_p, 0,
870 RV1126_CLKSEL_CON(43), 14, 2, MFLAGS, 8, 5, DFLAGS,
871 RV1126_CLKGATE_CON(13), 3, GFLAGS),
872 GATE(ACLK_JPEG, "aclk_jpeg", "aclk_pdjpeg", 0,
873 RV1126_CLKGATE_CON(13), 13, GFLAGS),
874 GATE(HCLK_JPEG, "hclk_jpeg", "hclk_pdjpeg", 0,
875 RV1126_CLKGATE_CON(13), 14, GFLAGS),
876
877 /*
878 * Clock-Architecture Diagram 9
879 */
880 /* PD_VO */
881 COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0,
882 RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
883 RV1126_CLKGATE_CON(14), 0, GFLAGS),
884 COMPOSITE_NOMUX(HCLK_PDVO, "hclk_pdvo", "aclk_pdvo", 0,
885 RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
886 RV1126_CLKGATE_CON(14), 1, GFLAGS),
887 COMPOSITE_NOMUX(PCLK_PDVO, "pclk_pdvo", "aclk_pdvo", 0,
888 RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
889 RV1126_CLKGATE_CON(14), 2, GFLAGS),
890 GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
891 RV1126_CLKGATE_CON(14), 6, GFLAGS),
892 GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
893 RV1126_CLKGATE_CON(14), 7, GFLAGS),
894 COMPOSITE(CLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_p, 0,
895 RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
896 RV1126_CLKGATE_CON(14), 8, GFLAGS),
897 GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
898 RV1126_CLKGATE_CON(14), 9, GFLAGS),
899 GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
900 RV1126_CLKGATE_CON(14), 10, GFLAGS),
901 COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,
902 RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
903 RV1126_CLKGATE_CON(14), 11, GFLAGS),
904 COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div", CLK_SET_RATE_PARENT,
905 RV1126_CLKSEL_CON(48), 0,
906 RV1126_CLKGATE_CON(14), 12, GFLAGS,
907 &rv1126_dclk_vop_fracmux),
908 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
909 RV1126_CLKGATE_CON(14), 13, GFLAGS),
910 GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
911 RV1126_CLKGATE_CON(14), 14, GFLAGS),
912 GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
913 RV1126_CLKGATE_CON(12), 7, GFLAGS),
914 GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0,
915 RV1126_CLKGATE_CON(12), 8, GFLAGS),
916 COMPOSITE(CLK_IEP_CORE, "clk_iep_core", mux_gpll_cpll_p, 0,
917 RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
918 RV1126_CLKGATE_CON(12), 9, GFLAGS),
919
920 /*
921 * Clock-Architecture Diagram 10
922 */
923 /* PD_VI */
924 COMPOSITE(ACLK_PDVI_DIV, "aclk_pdvi_div", mux_cpll_gpll_hpll_p, 0,
925 RV1126_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
926 RV1126_CLKGATE_CON(15), 0, GFLAGS),
927 COMPOSITE_HALFDIV_OFFSET(ACLK_PDVI_NP5, "aclk_pdvi_np5", mux_cpll_gpll_hpll_p, 0,
928 RV1126_CLKSEL_CON(49), 6, 2, MFLAGS,
929 RV1126_CLKSEL_CON(76), 0, 5, DFLAGS,
930 RV1126_CLKGATE_CON(16), 13, GFLAGS),
931 MUX(ACLK_PDVI, "aclk_pdvi", mux_aclk_pdvi_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
932 RV1126_CLKSEL_CON(76), 5, 1, MFLAGS),
933 COMPOSITE_NOMUX(HCLK_PDVI, "hclk_pdvi", "aclk_pdvi", 0,
934 RV1126_CLKSEL_CON(49), 8, 5, DFLAGS,
935 RV1126_CLKGATE_CON(15), 1, GFLAGS),
936 COMPOSITE_NOMUX(PCLK_PDVI, "pclk_pdvi", "aclk_pdvi", 0,
937 RV1126_CLKSEL_CON(50), 8, 5, DFLAGS,
938 RV1126_CLKGATE_CON(15), 2, GFLAGS),
939 GATE(ACLK_ISP, "aclk_isp", "aclk_pdvi", 0,
940 RV1126_CLKGATE_CON(15), 6, GFLAGS),
941 GATE(HCLK_ISP, "hclk_isp", "hclk_pdvi", 0,
942 RV1126_CLKGATE_CON(15), 7, GFLAGS),
943 COMPOSITE(CLK_ISP_DIV, "clk_isp_div", mux_gpll_cpll_hpll_p, 0,
944 RV1126_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS,
945 RV1126_CLKGATE_CON(15), 8, GFLAGS),
946 COMPOSITE_HALFDIV_OFFSET(CLK_ISP_NP5, "clk_isp_np5", mux_gpll_cpll_hpll_p, 0,
947 RV1126_CLKSEL_CON(50), 6, 2, MFLAGS,
948 RV1126_CLKSEL_CON(76), 8, 5, DFLAGS,
949 RV1126_CLKGATE_CON(16), 14, GFLAGS),
950 MUX(CLK_ISP, "clk_isp", mux_clk_isp_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
951 RV1126_CLKSEL_CON(76), 13, 1, MFLAGS),
952 GATE(ACLK_CIF, "aclk_cif", "aclk_pdvi", 0,
953 RV1126_CLKGATE_CON(15), 9, GFLAGS),
954 GATE(HCLK_CIF, "hclk_cif", "hclk_pdvi", 0,
955 RV1126_CLKGATE_CON(15), 10, GFLAGS),
956 COMPOSITE(DCLK_CIF, "dclk_cif", mux_gpll_cpll_hpll_p, 0,
957 RV1126_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
958 RV1126_CLKGATE_CON(15), 11, GFLAGS),
959 COMPOSITE(CLK_CIF_OUT_DIV, "clk_cif_out2io_div", mux_gpll_usb480m_p, 0,
960 RV1126_CLKSEL_CON(51), 15, 1, MFLAGS, 8, 6, DFLAGS,
961 RV1126_CLKGATE_CON(15), 12, GFLAGS),
962 COMPOSITE_FRACMUX(CLK_CIF_OUT_FRACDIV, "clk_cif_out2io_fracdiv", "clk_cif_out2io_div", CLK_SET_RATE_PARENT,
963 RV1126_CLKSEL_CON(52), 0,
964 RV1126_CLKGATE_CON(15), 13, GFLAGS,
965 &rv1126_cif_out2io_fracmux),
966 GATE(CLK_CIF_OUT, "clk_cif_out2io", "clk_cif_out2io_mux", 0,
967 RV1126_CLKGATE_CON(15), 14, GFLAGS),
968 COMPOSITE(CLK_MIPICSI_OUT_DIV, "clk_mipicsi_out2io_div", mux_gpll_usb480m_p, 0,
969 RV1126_CLKSEL_CON(73), 8, 1, MFLAGS, 0, 5, DFLAGS,
970 RV1126_CLKGATE_CON(23), 5, GFLAGS),
971 COMPOSITE_FRACMUX(CLK_MIPICSI_OUT_FRACDIV, "clk_mipicsi_out2io_fracdiv", "clk_mipicsi_out2io_div", CLK_SET_RATE_PARENT,
972 RV1126_CLKSEL_CON(74), 0,
973 RV1126_CLKGATE_CON(23), 6, GFLAGS,
974 &rv1126_mipicsi_out2io_fracmux),
975 GATE(CLK_MIPICSI_OUT, "clk_mipicsi_out2io", "clk_mipicsi_out2io_mux", 0,
976 RV1126_CLKGATE_CON(23), 7, GFLAGS),
977 GATE(PCLK_CSIHOST, "pclk_csihost", "pclk_pdvi", 0,
978 RV1126_CLKGATE_CON(15), 15, GFLAGS),
979 GATE(ACLK_CIFLITE, "aclk_ciflite", "aclk_pdvi", 0,
980 RV1126_CLKGATE_CON(16), 10, GFLAGS),
981 GATE(HCLK_CIFLITE, "hclk_ciflite", "hclk_pdvi", 0,
982 RV1126_CLKGATE_CON(16), 11, GFLAGS),
983 COMPOSITE(DCLK_CIFLITE, "dclk_ciflite", mux_gpll_cpll_hpll_p, 0,
984 RV1126_CLKSEL_CON(54), 14, 2, MFLAGS, 8, 5, DFLAGS,
985 RV1126_CLKGATE_CON(16), 12, GFLAGS),
986
987 /*
988 * Clock-Architecture Diagram 11
989 */
990 /* PD_ISPP */
991 COMPOSITE(ACLK_PDISPP_DIV, "aclk_pdispp_div", mux_cpll_gpll_hpll_p, 0,
992 RV1126_CLKSEL_CON(68), 6, 2, MFLAGS, 0, 5, DFLAGS,
993 RV1126_CLKGATE_CON(16), 0, GFLAGS),
994 COMPOSITE_HALFDIV_OFFSET(ACLK_PDISPP_NP5, "aclk_pdispp_np5", mux_cpll_gpll_hpll_p, 0,
995 RV1126_CLKSEL_CON(68), 6, 2, MFLAGS,
996 RV1126_CLKSEL_CON(77), 0, 5, DFLAGS,
997 RV1126_CLKGATE_CON(16), 8, GFLAGS),
998 MUX(ACLK_PDISPP, "aclk_pdispp", mux_aclk_pdispp_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
999 RV1126_CLKSEL_CON(77), 5, 1, MFLAGS),
1000 COMPOSITE_NOMUX(HCLK_PDISPP, "hclk_pdispp", "aclk_pdispp", 0,
1001 RV1126_CLKSEL_CON(69), 8, 5, DFLAGS,
1002 RV1126_CLKGATE_CON(16), 1, GFLAGS),
1003 GATE(ACLK_ISPP, "aclk_ispp", "aclk_pdispp", 0,
1004 RV1126_CLKGATE_CON(16), 4, GFLAGS),
1005 GATE(HCLK_ISPP, "hclk_ispp", "hclk_pdispp", 0,
1006 RV1126_CLKGATE_CON(16), 5, GFLAGS),
1007 COMPOSITE(CLK_ISPP_DIV, "clk_ispp_div", mux_cpll_gpll_hpll_p, 0,
1008 RV1126_CLKSEL_CON(69), 6, 2, MFLAGS, 0, 5, DFLAGS,
1009 RV1126_CLKGATE_CON(16), 6, GFLAGS),
1010 COMPOSITE_HALFDIV_OFFSET(CLK_ISPP_NP5, "clk_ispp_np5", mux_cpll_gpll_hpll_p, 0,
1011 RV1126_CLKSEL_CON(69), 6, 2, MFLAGS,
1012 RV1126_CLKSEL_CON(77), 8, 5, DFLAGS,
1013 RV1126_CLKGATE_CON(16), 7, GFLAGS),
1014 MUX(CLK_ISPP, "clk_ispp", mux_clk_ispp_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1015 RV1126_CLKSEL_CON(77), 13, 1, MFLAGS),
1016
1017 /*
1018 * Clock-Architecture Diagram 12
1019 */
1020 /* PD_PHP */
1021 COMPOSITE(ACLK_PDPHP, "aclk_pdphp", mux_gpll_cpll_p, CLK_IS_CRITICAL,
1022 RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
1023 RV1126_CLKGATE_CON(17), 0, GFLAGS),
1024 COMPOSITE_NOMUX(HCLK_PDPHP, "hclk_pdphp", "gpll", CLK_IS_CRITICAL,
1025 RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
1026 RV1126_CLKGATE_CON(17), 1, GFLAGS),
1027 /* PD_SDCARD */
1028 GATE(HCLK_PDSDMMC, "hclk_pdsdmmc", "hclk_pdphp", 0,
1029 RV1126_CLKGATE_CON(17), 6, GFLAGS),
1030 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_pdsdmmc", 0,
1031 RV1126_CLKGATE_CON(18), 4, GFLAGS),
1032 COMPOSITE(CLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_xin24m_p, 0,
1033 RV1126_CLKSEL_CON(55), 14, 2, MFLAGS, 0, 8,
1034 DFLAGS, RV1126_CLKGATE_CON(18), 5, GFLAGS),
1035 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RV1126_SDMMC_CON0, 1),
1036 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RV1126_SDMMC_CON1, 1),
1037
1038 /* PD_SDIO */
1039 GATE(HCLK_PDSDIO, "hclk_pdsdio", "hclk_pdphp", 0,
1040 RV1126_CLKGATE_CON(17), 8, GFLAGS),
1041 GATE(HCLK_SDIO, "hclk_sdio", "hclk_pdsdio", 0,
1042 RV1126_CLKGATE_CON(18), 6, GFLAGS),
1043 COMPOSITE(CLK_SDIO, "clk_sdio", mux_gpll_cpll_xin24m_p, 0,
1044 RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
1045 RV1126_CLKGATE_CON(18), 7, GFLAGS),
1046 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RV1126_SDIO_CON0, 1),
1047 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RV1126_SDIO_CON1, 1),
1048
1049 /* PD_NVM */
1050 GATE(HCLK_PDNVM, "hclk_pdnvm", "hclk_pdphp", 0,
1051 RV1126_CLKGATE_CON(18), 1, GFLAGS),
1052 GATE(HCLK_EMMC, "hclk_emmc", "hclk_pdnvm", 0,
1053 RV1126_CLKGATE_CON(18), 8, GFLAGS),
1054 COMPOSITE(CLK_EMMC, "clk_emmc", mux_gpll_cpll_xin24m_p, 0,
1055 RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
1056 RV1126_CLKGATE_CON(18), 9, GFLAGS),
1057 GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
1058 RV1126_CLKGATE_CON(18), 13, GFLAGS),
1059 COMPOSITE(CLK_NANDC, "clk_nandc", mux_gpll_cpll_p, 0,
1060 RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
1061 RV1126_CLKGATE_CON(18), 14, GFLAGS),
1062 GATE(HCLK_SFC, "hclk_sfc", "hclk_pdnvm", 0,
1063 RV1126_CLKGATE_CON(18), 10, GFLAGS),
1064 GATE(HCLK_SFCXIP, "hclk_sfcxip", "hclk_pdnvm", 0,
1065 RV1126_CLKGATE_CON(18), 11, GFLAGS),
1066 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_cpll_gpll_p, 0,
1067 RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
1068 RV1126_CLKGATE_CON(18), 12, GFLAGS),
1069 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RV1126_EMMC_CON0, 1),
1070 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RV1126_EMMC_CON1, 1),
1071
1072 /* PD_USB */
1073 GATE(ACLK_PDUSB, "aclk_pdusb", "aclk_pdphp", 0,
1074 RV1126_CLKGATE_CON(19), 0, GFLAGS),
1075 GATE(HCLK_PDUSB, "hclk_pdusb", "hclk_pdphp", 0,
1076 RV1126_CLKGATE_CON(19), 1, GFLAGS),
1077 GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_pdusb", 0,
1078 RV1126_CLKGATE_CON(19), 4, GFLAGS),
1079 GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_pdusb", 0,
1080 RV1126_CLKGATE_CON(19), 5, GFLAGS),
1081 #if IS_ENABLED(CONFIG_USB_EHCI_HCD_PLATFORM) || IS_ENABLED(CONFIG_USB_OHCI_HCD_PLATFORM)
1082 COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, CLK_IS_CRITICAL,
1083 RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
1084 RV1126_CLKGATE_CON(19), 6, GFLAGS),
1085 #else
1086 COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, 0,
1087 RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
1088 RV1126_CLKGATE_CON(19), 6, GFLAGS),
1089 #endif
1090 GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_pdusb", 0,
1091 RV1126_CLKGATE_CON(19), 7, GFLAGS),
1092 GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
1093 RV1126_CLKGATE_CON(19), 8, GFLAGS),
1094 /* PD_GMAC */
1095 GATE(ACLK_PDGMAC, "aclk_pdgmac", "aclk_pdphp", 0,
1096 RV1126_CLKGATE_CON(20), 0, GFLAGS),
1097 COMPOSITE_NOMUX(PCLK_PDGMAC, "pclk_pdgmac", "aclk_pdgmac", 0,
1098 RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
1099 RV1126_CLKGATE_CON(20), 1, GFLAGS),
1100 GATE(ACLK_GMAC, "aclk_gmac", "aclk_pdgmac", 0,
1101 RV1126_CLKGATE_CON(20), 4, GFLAGS),
1102 GATE(PCLK_GMAC, "pclk_gmac", "pclk_pdgmac", 0,
1103 RV1126_CLKGATE_CON(20), 5, GFLAGS),
1104
1105 COMPOSITE(CLK_GMAC_DIV, "clk_gmac_div", mux_cpll_gpll_p, 0,
1106 RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
1107 RV1126_CLKGATE_CON(20), 6, GFLAGS),
1108 GATE(CLK_GMAC_RGMII_M0, "clk_gmac_rgmii_m0", "clk_gmac_rgmii_clkin_m0", 0,
1109 RV1126_CLKGATE_CON(20), 12, GFLAGS),
1110 MUX(CLK_GMAC_SRC_M0, "clk_gmac_src_m0", clk_gmac_src_m0_p, CLK_SET_RATE_PARENT,
1111 RV1126_GMAC_CON, 0, 1, MFLAGS),
1112 GATE(CLK_GMAC_RGMII_M1, "clk_gmac_rgmii_m1", "clk_gmac_rgmii_clkin_m1", 0,
1113 RV1126_CLKGATE_CON(20), 13, GFLAGS),
1114 MUX(CLK_GMAC_SRC_M1, "clk_gmac_src_m1", clk_gmac_src_m1_p, CLK_SET_RATE_PARENT,
1115 RV1126_GMAC_CON, 5, 1, MFLAGS),
1116 MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1117 RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),
1118
1119 GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
1120 RV1126_CLKGATE_CON(20), 7, GFLAGS),
1121
1122 GATE(CLK_GMAC_TX_SRC, "clk_gmac_tx_src", "clk_gmac_src", 0,
1123 RV1126_CLKGATE_CON(20), 9, GFLAGS),
1124 FACTOR(CLK_GMAC_TX_DIV5, "clk_gmac_tx_div5", "clk_gmac_tx_src", 0, 1, 5),
1125 FACTOR(CLK_GMAC_TX_DIV50, "clk_gmac_tx_div50", "clk_gmac_tx_src", 0, 1, 50),
1126 MUXTBL(RGMII_MODE_CLK, "rgmii_mode_clk", mux_rgmii_clk_p, CLK_SET_RATE_PARENT,
1127 RV1126_GMAC_CON, 2, 2, MFLAGS, rgmii_mux_idx),
1128 GATE(CLK_GMAC_RX_SRC, "clk_gmac_rx_src", "clk_gmac_src", 0,
1129 RV1126_CLKGATE_CON(20), 8, GFLAGS),
1130 FACTOR(CLK_GMAC_RX_DIV2, "clk_gmac_rx_div2", "clk_gmac_rx_src", 0, 1, 2),
1131 FACTOR(CLK_GMAC_RX_DIV20, "clk_gmac_rx_div20", "clk_gmac_rx_src", 0, 1, 20),
1132 MUX(RMII_MODE_CLK, "rmii_mode_clk", mux_rmii_clk_p, CLK_SET_RATE_PARENT,
1133 RV1126_GMAC_CON, 1, 1, MFLAGS),
1134 MUX(CLK_GMAC_TX_RX, "clk_gmac_tx_rx", mux_gmac_tx_rx_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1135 RV1126_GMAC_CON, 4, 1, MFLAGS),
1136
1137 GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
1138 RV1126_CLKGATE_CON(20), 10, GFLAGS),
1139 COMPOSITE(CLK_GMAC_ETHERNET_OUT, "clk_gmac_ethernet_out2io", mux_cpll_gpll_p, 0,
1140 RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
1141 RV1126_CLKGATE_CON(20), 11, GFLAGS),
1142
1143
1144 /*
1145 * Clock-Architecture Diagram 14
1146 */
1147 /* PD_NPU */
1148 COMPOSITE(ACLK_PDNPU_DIV, "aclk_pdnpu_div", mux_gpll_cpll_apll_hpll_p, 0,
1149 RV1126_CLKSEL_CON(65), 8, 2, MFLAGS, 0, 4, DFLAGS,
1150 RV1126_CLKGATE_CON(22), 0, GFLAGS),
1151 COMPOSITE_HALFDIV(ACLK_PDNPU_NP5, "aclk_pdnpu_np5", mux_gpll_cpll_apll_hpll_p, 0,
1152 RV1126_CLKSEL_CON(65), 8, 2, MFLAGS, 4, 4, DFLAGS,
1153 RV1126_CLKGATE_CON(22), 1, GFLAGS),
1154 MUX(ACLK_PDNPU, "aclk_pdnpu", mux_aclk_pdnpu_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1155 RV1126_CLKSEL_CON(65), 12, 1, MFLAGS),
1156 COMPOSITE_NOMUX(HCLK_PDNPU, "hclk_pdnpu", "gpll", 0,
1157 RV1126_CLKSEL_CON(66), 8, 4, DFLAGS,
1158 RV1126_CLKGATE_CON(22), 2, GFLAGS),
1159 COMPOSITE_NOMUX(PCLK_PDNPU, "pclk_pdnpu", "hclk_pdnpu", 0,
1160 RV1126_CLKSEL_CON(66), 0, 5, DFLAGS,
1161 RV1126_CLKGATE_CON(22), 3, GFLAGS),
1162 GATE(ACLK_NPU, "aclk_npu", "aclk_pdnpu", 0,
1163 RV1126_CLKGATE_CON(22), 7, GFLAGS),
1164 GATE(HCLK_NPU, "hclk_npu", "hclk_pdnpu", 0,
1165 RV1126_CLKGATE_CON(22), 8, GFLAGS),
1166 COMPOSITE(CLK_NPU_DIV, "clk_npu_div", mux_gpll_cpll_apll_hpll_p, 0,
1167 RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 0, 4, DFLAGS,
1168 RV1126_CLKGATE_CON(22), 9, GFLAGS),
1169 COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", mux_gpll_cpll_apll_hpll_p, 0,
1170 RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 4, 4, DFLAGS,
1171 RV1126_CLKGATE_CON(22), 10, GFLAGS),
1172 MUX(CLK_CORE_NPU, "clk_core_npu", mux_clk_npu_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1173 RV1126_CLKSEL_CON(67), 12, 1, MFLAGS),
1174 GATE(CLK_CORE_NPUPVTM, "clk_core_npupvtm", "clk_core_npu", CLK_IGNORE_UNUSED,
1175 RV1126_CLKGATE_CON(22), 14, GFLAGS),
1176 GATE(CLK_NPUPVTM, "clk_npupvtm", "xin24m", 0,
1177 RV1126_CLKGATE_CON(22), 13, GFLAGS),
1178 GATE(PCLK_NPUPVTM, "pclk_npupvtm", "pclk_pdnpu", CLK_IGNORE_UNUSED,
1179 RV1126_CLKGATE_CON(22), 12, GFLAGS),
1180
1181 /*
1182 * Clock-Architecture Diagram 15
1183 */
1184 GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IS_CRITICAL,
1185 RV1126_CLKGATE_CON(23), 8, GFLAGS),
1186 GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_pdtop", 0,
1187 RV1126_CLKGATE_CON(23), 4, GFLAGS),
1188 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_pdtop", 0,
1189 RV1126_CLKGATE_CON(23), 2, GFLAGS),
1190 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_pdtop", 0,
1191 RV1126_CLKGATE_CON(23), 3, GFLAGS),
1192 GATE(PCLK_USBPHY_HOST, "pclk_usbphy_host", "pclk_pdtop", 0,
1193 RV1126_CLKGATE_CON(19), 13, GFLAGS),
1194 GATE(PCLK_USBPHY_OTG, "pclk_usbphy_otg", "pclk_pdtop", 0,
1195 RV1126_CLKGATE_CON(19), 12, GFLAGS),
1196
1197 #ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
1198 /*
1199 * Clock-Architecture Diagram 3
1200 */
1201 /* PD_CORE */
1202 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IS_CRITICAL,
1203 RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
1204 RV1126_CLKGATE_CON(0), 2, GFLAGS),
1205 GATE(0, "pclk_dbg_daplite", "pclk_dbg", CLK_IGNORE_UNUSED,
1206 RV1126_CLKGATE_CON(0), 5, GFLAGS),
1207 GATE(0, "clk_a7_jtag", "clk_jtag_ori", CLK_IGNORE_UNUSED,
1208 RV1126_CLKGATE_CON(0), 9, GFLAGS),
1209 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
1210 RV1126_CLKGATE_CON(0), 3, GFLAGS),
1211 GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
1212 RV1126_CLKGATE_CON(0), 4, GFLAGS),
1213 /*
1214 * Clock-Architecture Diagram 4
1215 */
1216 /* PD_BUS */
1217 GATE(0, "aclk_pdbus_hold_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
1218 RV1126_CLKGATE_CON(2), 10, GFLAGS),
1219 GATE(0, "aclk_pdbus_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
1220 RV1126_CLKGATE_CON(2), 3, GFLAGS),
1221 GATE(0, "hclk_pdbus_niu1", "hclk_pdbus", CLK_IGNORE_UNUSED,
1222 RV1126_CLKGATE_CON(2), 4, GFLAGS),
1223 GATE(0, "pclk_pdbus_niu1", "pclk_pdbus", CLK_IGNORE_UNUSED,
1224 RV1126_CLKGATE_CON(2), 5, GFLAGS),
1225 GATE(0, "aclk_pdbus_niu2", "aclk_pdbus", CLK_IGNORE_UNUSED,
1226 RV1126_CLKGATE_CON(2), 6, GFLAGS),
1227 GATE(0, "hclk_pdbus_niu2", "hclk_pdbus", CLK_IGNORE_UNUSED,
1228 RV1126_CLKGATE_CON(2), 7, GFLAGS),
1229 GATE(0, "aclk_pdbus_niu3", "aclk_pdbus", CLK_IGNORE_UNUSED,
1230 RV1126_CLKGATE_CON(2), 8, GFLAGS),
1231 GATE(0, "hclk_pdbus_niu3", "hclk_pdbus", CLK_IGNORE_UNUSED,
1232 RV1126_CLKGATE_CON(2), 9, GFLAGS),
1233 GATE(0, "pclk_grf", "pclk_pdbus", CLK_IGNORE_UNUSED,
1234 RV1126_CLKGATE_CON(6), 15, GFLAGS),
1235 GATE(0, "pclk_sgrf", "pclk_pdbus", CLK_IGNORE_UNUSED,
1236 RV1126_CLKGATE_CON(8), 4, GFLAGS),
1237 GATE(0, "aclk_sysram", "hclk_pdbus", CLK_IGNORE_UNUSED,
1238 RV1126_CLKGATE_CON(3), 9, GFLAGS),
1239 GATE(0, "pclk_intmux", "pclk_pdbus", CLK_IGNORE_UNUSED,
1240 RV1126_CLKGATE_CON(7), 14, GFLAGS),
1241
1242 /*
1243 * Clock-Architecture Diagram 5
1244 */
1245 /* PD_CRYPTO */
1246 GATE(0, "aclk_pdcrypto_niu", "aclk_pdcrypto", CLK_IGNORE_UNUSED,
1247 RV1126_CLKGATE_CON(4), 13, GFLAGS),
1248 GATE(0, "hclk_pdcrypto_niu", "hclk_pdcrypto", CLK_IGNORE_UNUSED,
1249 RV1126_CLKGATE_CON(4), 14, GFLAGS),
1250
1251 /*
1252 * Clock-Architecture Diagram 6
1253 */
1254 /* PD_AUDIO */
1255 GATE(0, "hclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
1256 RV1126_CLKGATE_CON(9), 2, GFLAGS),
1257 GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
1258 RV1126_CLKGATE_CON(9), 3, GFLAGS),
1259
1260 /*
1261 * Clock-Architecture Diagram 7
1262 */
1263 /* PD_VEPU */
1264 GATE(0, "aclk_pdvepu_niu", "aclk_pdvepu", CLK_IGNORE_UNUSED,
1265 RV1126_CLKGATE_CON(12), 3, GFLAGS),
1266 GATE(0, "hclk_pdvepu_niu", "hclk_pdvepu", CLK_IGNORE_UNUSED,
1267 RV1126_CLKGATE_CON(12), 4, GFLAGS),
1268
1269 /*
1270 * Clock-Architecture Diagram 9
1271 */
1272 /* PD_VO */
1273 GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
1274 RV1126_CLKGATE_CON(14), 3, GFLAGS),
1275 GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
1276 RV1126_CLKGATE_CON(14), 4, GFLAGS),
1277 GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
1278 RV1126_CLKGATE_CON(14), 5, GFLAGS),
1279
1280 /*
1281 * Clock-Architecture Diagram 10
1282 */
1283 /* PD_VI */
1284 GATE(0, "aclk_pdvi_niu", "aclk_pdvi", CLK_IGNORE_UNUSED,
1285 RV1126_CLKGATE_CON(15), 3, GFLAGS),
1286 GATE(0, "hclk_pdvi_niu", "hclk_pdvi", CLK_IGNORE_UNUSED,
1287 RV1126_CLKGATE_CON(15), 4, GFLAGS),
1288 GATE(0, "pclk_pdvi_niu", "pclk_pdvi", CLK_IGNORE_UNUSED,
1289 RV1126_CLKGATE_CON(15), 5, GFLAGS),
1290 /*
1291 * Clock-Architecture Diagram 11
1292 */
1293 /* PD_ISPP */
1294 GATE(0, "aclk_pdispp_niu", "aclk_pdispp", CLK_IGNORE_UNUSED,
1295 RV1126_CLKGATE_CON(16), 2, GFLAGS),
1296 GATE(0, "hclk_pdispp_niu", "hclk_pdispp", CLK_IGNORE_UNUSED,
1297 RV1126_CLKGATE_CON(16), 3, GFLAGS),
1298
1299 /*
1300 * Clock-Architecture Diagram 12
1301 */
1302 /* PD_PHP */
1303 GATE(0, "aclk_pdphpmid", "aclk_pdphp", CLK_IGNORE_UNUSED,
1304 RV1126_CLKGATE_CON(17), 2, GFLAGS),
1305 GATE(0, "hclk_pdphpmid", "hclk_pdphp", CLK_IGNORE_UNUSED,
1306 RV1126_CLKGATE_CON(17), 3, GFLAGS),
1307 GATE(0, "aclk_pdphpmid_niu", "aclk_pdphpmid", CLK_IGNORE_UNUSED,
1308 RV1126_CLKGATE_CON(17), 4, GFLAGS),
1309 GATE(0, "hclk_pdphpmid_niu", "hclk_pdphpmid", CLK_IGNORE_UNUSED,
1310 RV1126_CLKGATE_CON(17), 5, GFLAGS),
1311
1312 /* PD_SDCARD */
1313 GATE(0, "hclk_pdsdmmc_niu", "hclk_pdsdmmc", CLK_IGNORE_UNUSED,
1314 RV1126_CLKGATE_CON(17), 7, GFLAGS),
1315
1316 /* PD_SDIO */
1317 GATE(0, "hclk_pdsdio_niu", "hclk_pdsdio", CLK_IGNORE_UNUSED,
1318 RV1126_CLKGATE_CON(17), 9, GFLAGS),
1319
1320 /* PD_NVM */
1321 GATE(0, "hclk_pdnvm_niu", "hclk_pdnvm", CLK_IGNORE_UNUSED,
1322 RV1126_CLKGATE_CON(18), 3, GFLAGS),
1323
1324 /* PD_USB */
1325 GATE(0, "aclk_pdusb_niu", "aclk_pdusb", CLK_IGNORE_UNUSED,
1326 RV1126_CLKGATE_CON(19), 2, GFLAGS),
1327 GATE(0, "hclk_pdusb_niu", "hclk_pdusb", CLK_IGNORE_UNUSED,
1328 RV1126_CLKGATE_CON(19), 3, GFLAGS),
1329
1330 /* PD_GMAC */
1331 GATE(0, "aclk_pdgmac_niu", "aclk_pdgmac", CLK_IGNORE_UNUSED,
1332 RV1126_CLKGATE_CON(20), 2, GFLAGS),
1333 GATE(0, "pclk_pdgmac_niu", "pclk_pdgmac", CLK_IGNORE_UNUSED,
1334 RV1126_CLKGATE_CON(20), 3, GFLAGS),
1335
1336 /*
1337 * Clock-Architecture Diagram 13
1338 */
1339 /* PD_DDR */
1340 COMPOSITE_NOMUX(0, "pclk_pdddr_pre", "gpll", CLK_IS_CRITICAL,
1341 RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
1342 RV1126_CLKGATE_CON(21), 0, GFLAGS),
1343 GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IS_CRITICAL,
1344 RV1126_CLKGATE_CON(21), 15, GFLAGS),
1345 GATE(0, "pclk_ddr_msch", "pclk_pdddr", CLK_IGNORE_UNUSED,
1346 RV1126_CLKGATE_CON(21), 6, GFLAGS),
1347 COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_gpll_p, CLK_IS_CRITICAL,
1348 RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS),
1349 COMPOSITE(CLK_DDRPHY, "clk_ddrphy", mux_dpll_gpll_p, CLK_IS_CRITICAL,
1350 RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
1351 RV1126_CLKGATE_CON(21), 8, GFLAGS),
1352 GATE(0, "clk1x_phy", "clk_ddrphy", CLK_IGNORE_UNUSED,
1353 RV1126_CLKGATE_CON(23), 1, GFLAGS),
1354 GATE(0, "clk_ddr_msch", "clk_ddrphy", CLK_IGNORE_UNUSED,
1355 RV1126_CLKGATE_CON(21), 10, GFLAGS),
1356 GATE(0, "pclk_ddr_dfictl", "pclk_pdddr", CLK_IGNORE_UNUSED,
1357 RV1126_CLKGATE_CON(21), 2, GFLAGS),
1358 GATE(0, "clk_ddr_dfictl", "clk_ddrphy", CLK_IGNORE_UNUSED,
1359 RV1126_CLKGATE_CON(21), 13, GFLAGS),
1360 GATE(0, "pclk_ddr_standby", "pclk_pdddr", CLK_IGNORE_UNUSED,
1361 RV1126_CLKGATE_CON(21), 4, GFLAGS),
1362 GATE(0, "clk_ddr_standby", "clk_ddrphy", CLK_IGNORE_UNUSED,
1363 RV1126_CLKGATE_CON(21), 14, GFLAGS),
1364 GATE(0, "aclk_ddr_split", "clk_ddrphy", CLK_IGNORE_UNUSED,
1365 RV1126_CLKGATE_CON(21), 9, GFLAGS),
1366 GATE(0, "pclk_ddr_grf", "pclk_pdddr", CLK_IGNORE_UNUSED,
1367 RV1126_CLKGATE_CON(21), 5, GFLAGS),
1368 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_pdddr", CLK_IGNORE_UNUSED,
1369 RV1126_CLKGATE_CON(21), 3, GFLAGS),
1370 GATE(CLK_DDR_MON, "clk_ddr_mon", "clk_ddrphy", CLK_IGNORE_UNUSED,
1371 RV1126_CLKGATE_CON(20), 15, GFLAGS),
1372 GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
1373 RV1126_CLKGATE_CON(21), 7, GFLAGS),
1374
1375 /*
1376 * Clock-Architecture Diagram 14
1377 */
1378 /* PD_NPU */
1379 GATE(0, "aclk_pdnpu_niu", "aclk_pdnpu", CLK_IGNORE_UNUSED,
1380 RV1126_CLKGATE_CON(22), 4, GFLAGS),
1381 GATE(0, "hclk_pdnpu_niu", "hclk_pdnpu", CLK_IGNORE_UNUSED,
1382 RV1126_CLKGATE_CON(22), 5, GFLAGS),
1383 GATE(0, "pclk_pdnpu_niu", "pclk_pdnpu", CLK_IGNORE_UNUSED,
1384 RV1126_CLKGATE_CON(22), 6, GFLAGS),
1385
1386 /*
1387 * Clock-Architecture Diagram 15
1388 */
1389 GATE(0, "pclk_topniu", "pclk_pdtop", CLK_IGNORE_UNUSED,
1390 RV1126_CLKGATE_CON(23), 9, GFLAGS),
1391 GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_pdtop", CLK_IGNORE_UNUSED,
1392 RV1126_CLKGATE_CON(23), 10, GFLAGS),
1393 GATE(PCLK_TOPGRF, "pclk_topgrf", "pclk_pdtop", CLK_IGNORE_UNUSED,
1394 RV1126_CLKGATE_CON(23), 11, GFLAGS),
1395 GATE(PCLK_CPUEMADET, "pclk_cpuemadet", "pclk_pdtop", CLK_IGNORE_UNUSED,
1396 RV1126_CLKGATE_CON(23), 12, GFLAGS),
1397 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_pdtop", CLK_IGNORE_UNUSED,
1398 RV1126_CLKGATE_CON(23), 0, GFLAGS),
1399 #endif
1400 };
1401
1402 static void __iomem *rv1126_cru_base;
1403 static void __iomem *rv1126_pmucru_base;
1404
rv1126_dump_cru(void)1405 void rv1126_dump_cru(void)
1406 {
1407 if (rv1126_pmucru_base) {
1408 pr_warn("PMU CRU:\n");
1409 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1410 32, 4, rv1126_pmucru_base,
1411 0x248, false);
1412 }
1413 if (rv1126_cru_base) {
1414 pr_warn("CRU:\n");
1415 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1416 32, 4, rv1126_cru_base,
1417 0x588, false);
1418 }
1419 }
1420 EXPORT_SYMBOL_GPL(rv1126_dump_cru);
1421
rv1126_clk_panic(struct notifier_block * this,unsigned long ev,void * ptr)1422 static int rv1126_clk_panic(struct notifier_block *this,
1423 unsigned long ev, void *ptr)
1424 {
1425 rv1126_dump_cru();
1426 return NOTIFY_DONE;
1427 }
1428
1429 static struct notifier_block rv1126_clk_panic_block = {
1430 .notifier_call = rv1126_clk_panic,
1431 };
1432
1433 static struct rockchip_clk_provider *pmucru_ctx;
rv1126_pmu_clk_init(struct device_node * np)1434 static void __init rv1126_pmu_clk_init(struct device_node *np)
1435 {
1436 struct rockchip_clk_provider *ctx;
1437 void __iomem *reg_base;
1438
1439 reg_base = of_iomap(np, 0);
1440 if (!reg_base) {
1441 pr_err("%s: could not map cru pmu region\n", __func__);
1442 return;
1443 }
1444
1445 rv1126_pmucru_base = reg_base;
1446
1447 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1448 if (IS_ERR(ctx)) {
1449 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1450 return;
1451 }
1452
1453 rockchip_clk_register_plls(ctx, rv1126_pmu_pll_clks,
1454 ARRAY_SIZE(rv1126_pmu_pll_clks),
1455 RV1126_GRF_SOC_STATUS0);
1456
1457 rockchip_clk_register_branches(ctx, rv1126_clk_pmu_branches,
1458 ARRAY_SIZE(rv1126_clk_pmu_branches));
1459
1460 rockchip_register_softrst(np, 2, reg_base + RV1126_PMU_SOFTRST_CON(0),
1461 ROCKCHIP_SOFTRST_HIWORD_MASK);
1462
1463 rockchip_clk_of_add_provider(np, ctx);
1464
1465 pmucru_ctx = ctx;
1466 }
1467
1468 CLK_OF_DECLARE(rv1126_cru_pmu, "rockchip,rv1126-pmucru", rv1126_pmu_clk_init);
1469
rv1126_clk_init(struct device_node * np)1470 static void __init rv1126_clk_init(struct device_node *np)
1471 {
1472 struct rockchip_clk_provider *ctx;
1473 void __iomem *reg_base;
1474 struct clk **cru_clks, **pmucru_clks;
1475
1476 reg_base = of_iomap(np, 0);
1477 if (!reg_base) {
1478 pr_err("%s: could not map cru region\n", __func__);
1479 return;
1480 }
1481
1482 rv1126_cru_base = reg_base;
1483
1484 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1485 if (IS_ERR(ctx)) {
1486 pr_err("%s: rockchip clk init failed\n", __func__);
1487 iounmap(reg_base);
1488 return;
1489 }
1490 cru_clks = ctx->clk_data.clks;
1491 pmucru_clks = pmucru_ctx->clk_data.clks;
1492
1493 rockchip_clk_register_plls(ctx, rv1126_pll_clks,
1494 ARRAY_SIZE(rv1126_pll_clks),
1495 RV1126_GRF_SOC_STATUS0);
1496
1497 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1498 3, cru_clks[PLL_APLL], pmucru_clks[PLL_GPLL],
1499 &rv1126_cpuclk_data, rv1126_cpuclk_rates,
1500 ARRAY_SIZE(rv1126_cpuclk_rates));
1501
1502 rockchip_clk_register_branches(ctx, rv1126_clk_branches,
1503 ARRAY_SIZE(rv1126_clk_branches));
1504
1505 rockchip_register_softrst(np, 15, reg_base + RV1126_SOFTRST_CON(0),
1506 ROCKCHIP_SOFTRST_HIWORD_MASK);
1507
1508 rockchip_register_restart_notifier(ctx, RV1126_GLB_SRST_FST, NULL);
1509
1510 rockchip_clk_of_add_provider(np, ctx);
1511
1512 atomic_notifier_chain_register(&panic_notifier_list,
1513 &rv1126_clk_panic_block);
1514 }
1515
1516 CLK_OF_DECLARE(rv1126_cru, "rockchip,rv1126-cru", rv1126_clk_init);
1517
1518 struct clk_rv1126_inits {
1519 void (*inits)(struct device_node *np);
1520 };
1521
1522 static const struct clk_rv1126_inits clk_rv1126_pmu_init = {
1523 .inits = rv1126_pmu_clk_init,
1524 };
1525
1526 static const struct clk_rv1126_inits clk_rv1126_init = {
1527 .inits = rv1126_clk_init,
1528 };
1529
1530 static const struct of_device_id clk_rv1126_match_table[] = {
1531 {
1532 .compatible = "rockchip,rv1126-cru",
1533 .data = &clk_rv1126_init,
1534 }, {
1535 .compatible = "rockchip,rv1126-pmucru",
1536 .data = &clk_rv1126_pmu_init,
1537 },
1538 { }
1539 };
1540 MODULE_DEVICE_TABLE(of, clk_rv1126_match_table);
1541
clk_rv1126_probe(struct platform_device * pdev)1542 static int __init clk_rv1126_probe(struct platform_device *pdev)
1543 {
1544 struct device_node *np = pdev->dev.of_node;
1545 const struct of_device_id *match;
1546 const struct clk_rv1126_inits *init_data;
1547
1548 match = of_match_device(clk_rv1126_match_table, &pdev->dev);
1549 if (!match || !match->data)
1550 return -EINVAL;
1551
1552 init_data = match->data;
1553 if (init_data->inits)
1554 init_data->inits(np);
1555
1556 return 0;
1557 }
1558
1559 static struct platform_driver clk_rv1126_driver = {
1560 .driver = {
1561 .name = "clk-rv1126",
1562 .of_match_table = clk_rv1126_match_table,
1563 },
1564 };
1565 builtin_platform_driver_probe(clk_rv1126_driver, clk_rv1126_probe);
1566
1567 MODULE_DESCRIPTION("Rockchip RV1126 Clock Driver");
1568 MODULE_LICENSE("GPL");
1569