Lines Matching full:xin24m
137 PNAME(mux_pll_p) = { "xin24m" };
138 PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
140 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
141 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
142 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" };
143 PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src", "xin24m" };
144 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m"…
145 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m…
146 PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", "clk_100m_src", "xin24m…
147 PNAME(mux_500m_200m_100m_24m_p) = { "clk_500m_src", "clk_200m_src", "clk_100m_src", "xin24m…
148 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m…
149 PNAME(mux_600m_300m_200m_24m_p) = { "clk_600m_src", "clk_300m_src", "clk_200m_src", "xin24m…
152 PNAME(clk_i2c2_p) = { "clk_200m_src", "clk_100m_src", "xin24m", "clk_32k" };
153 PNAME(clk_ref_pcie_inner_phy_p) = { "clk_ppll_100m_src", "xin24m" };
162 PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
163 PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
164 PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
165 PNAME(sclk_uart3_src_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
166 PNAME(sclk_uart4_src_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
167 PNAME(sclk_uart5_src_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
168 PNAME(sclk_uart6_src_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
169 PNAME(sclk_uart7_src_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
257 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
295 COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0,
478 GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
480 GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
482 GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0,
484 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
487 GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
542 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
544 COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
548 COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0,
556 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
591 GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
709 GATE(CLK_UART_JTAG, "clk_uart_jtag", "xin24m", 0,
718 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
826 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
829 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
831 GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
833 GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
835 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
871 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
873 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
875 GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0,
877 GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0,
879 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
881 GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0,
1007 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
1010 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
1013 COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,