1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/rv1108-cru.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/media/rockchip_mipi_dsi.h> 13#include <linux/media-bus-format.h> 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1108"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 i2c0 = &i2c0; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 spi0 = &sfc; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@f00 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a7"; 37 reg = <0xf00>; 38 }; 39 }; 40 41 arm-pmu { 42 compatible = "arm,cortex-a7-pmu"; 43 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 44 }; 45 46 display_subsystem: display-subsystem { 47 compatible = "rockchip,display-subsystem"; 48 ports = <&vop_out>; 49 status = "disabled"; 50 51 route { 52 route_dsi: route-dsi { 53 status = "okay"; 54 logo,uboot = "logo.bmp"; 55 logo,kernel = "logo_kernel.bmp"; 56 logo,mode = "center"; 57 charge_logo,mode = "center"; 58 connect = <&vop_out_mipi>; 59 }; 60 }; 61 }; 62 63 mipi_dphy: mipi-dphy@0x20228000 { 64 compatible = "rockchip,rv1108-mipi-dphy"; 65 reg = <0x20228000 0x8000>; 66 clock-output-names = "mipi_dphy_pll"; 67 #clock-cells = <0>; 68 resets = <&cru PRST_MIPI_DSI_PHY>; 69 reset-names = "apb"; 70 #phy-cells = <0>; 71 status = "disabled"; 72 }; 73 74 dsi: dsi@300e0000 { 75 compatible = "rockchip,rv1108-mipi-dsi"; 76 reg = <0x300e0000 0x10000>; 77 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&cru PCLK_MIPI_DSI>, <&mipi_dphy>; 79 clock-names = "pclk", "hs_clk"; 80 resets = <&cru 127>; 81 reset-names = "apb"; 82 phys = <&mipi_dphy>; 83 phy-names = "mipi_dphy"; 84 rockchip,grf = <&grf>; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&lcdc_mipi_data>; 89 status = "disabled"; 90 91 ports { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 95 port@0 { 96 reg = <0>; 97 98 #address-cells = <1>; 99 #size-cells = <0>; 100 101 mipi_in_vop: endpoint@0 { 102 reg = <0>; 103 remote-endpoint = <&vop_out_mipi>; 104 }; 105 }; 106 107 }; 108 }; 109 110 timer { 111 compatible = "arm,armv7-timer"; 112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, 113 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 114 clock-frequency = <24000000>; 115 }; 116 117 xin24m: oscillator { 118 compatible = "fixed-clock"; 119 clock-frequency = <24000000>; 120 clock-output-names = "xin24m"; 121 #clock-cells = <0>; 122 }; 123 124 amba { 125 compatible = "simple-bus"; 126 #address-cells = <1>; 127 #size-cells = <1>; 128 ranges; 129 130 pdma: pdma@102a0000 { 131 compatible = "arm,pl330", "arm,primecell"; 132 reg = <0x102a0000 0x4000>; 133 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 134 #dma-cells = <1>; 135 arm,pl330-broken-no-flushp; 136 clocks = <&cru ACLK_DMAC>; 137 clock-names = "apb_pclk"; 138 }; 139 }; 140 141 bus_intmem@10080000 { 142 compatible = "mmio-sram"; 143 reg = <0x10080000 0x2000>; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0 0x10080000 0x2000>; 147 }; 148 149 uart2: serial@10210000 { 150 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 151 reg = <0x10210000 0x100>; 152 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 153 reg-shift = <2>; 154 reg-io-width = <4>; 155 clock-frequency = <24000000>; 156 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 157 clock-names = "baudclk", "apb_pclk"; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&uart2m0_xfer>; 160 status = "disabled"; 161 }; 162 163 uart1: serial@10220000 { 164 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 165 reg = <0x10220000 0x100>; 166 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 167 reg-shift = <2>; 168 reg-io-width = <4>; 169 clock-frequency = <24000000>; 170 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 171 clock-names = "baudclk", "apb_pclk"; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&uart1_xfer>; 174 status = "disabled"; 175 }; 176 177 uart0: serial@10230000 { 178 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 179 reg = <0x10230000 0x100>; 180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 181 reg-shift = <2>; 182 reg-io-width = <4>; 183 clock-frequency = <24000000>; 184 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 185 clock-names = "baudclk", "apb_pclk"; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 188 status = "disabled"; 189 }; 190 191 grf: syscon@10300000 { 192 compatible = "rockchip,rv1108-grf", "syscon"; 193 reg = <0x10300000 0x1000>; 194 }; 195 196 u2phy: usb2-phy@10300100 { 197 compatible = "rockchip,rv1108-usb2phy"; 198 reg = <0x100 0x0c>; 199 rockchip,grf = <&grf>; 200 #phy-cells = <1>; 201 status = "disabled"; 202 203 u2phy_otg: otg-port { 204 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 205 interrupt-names = "otg-mux"; 206 #phy-cells = <0>; 207 status = "disabled"; 208 }; 209 210 u2phy_host: host-port { 211 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "linestate"; 213 #phy-cells = <0>; 214 status = "disabled"; 215 }; 216 }; 217 218 saradc: saradc@1038c000 { 219 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; 220 reg = <0x1038c000 0x100>; 221 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 222 #io-channel-cells = <1>; 223 clock-frequency = <1000000>; 224 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 225 clock-names = "saradc", "apb_pclk"; 226 status = "disabled"; 227 }; 228 229 pwm0: pwm@20040000 { 230 compatible = "rockchip,rk1108-pwm", "rockchip,rk3328-pwm"; 231 reg = <0x20040000 0x10>; 232 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 233 #pwm-cells = <3>; 234 pinctrl-names = "active"; 235 pinctrl-0 = <&pwm0_pin>; 236 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 237 clock-names = "pwm", "pclk"; 238 status = "disabled"; 239 }; 240 241 pmugrf: syscon@20060000 { 242 compatible = "rockchip,rv1108-pmugrf", "syscon"; 243 reg = <0x20060000 0x1000>; 244 }; 245 246 cru: clock-controller@20200000 { 247 compatible = "rockchip,rv1108-cru"; 248 reg = <0x20200000 0x1000>; 249 rockchip,grf = <&grf>; 250 #clock-cells = <1>; 251 #reset-cells = <1>; 252 }; 253 i2c0: i2c@20000000 { 254 compatible = "rockchip,rv1108-i2c"; 255 reg = <0x20000000 0x1000>; 256 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 257 rockchip,grf = <&grf>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; 261 clock-names = "i2c", "pclk"; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&i2c0_xfer>; 264 status = "disabled"; 265 }; 266 usbgrf: syscon@202a0000 { 267 compatible = "rockchip,rv1108-usbgrf", "syscon"; 268 reg = <0x202a0000 0x1000>; 269 }; 270 271 nandc: nandc@30100000 { 272 compatible = "rockchip,rk-nandc"; 273 reg = <0x30100000 0x1000>; 274 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 275 nandc_id = <0>; 276 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 277 clock-names = "clk_nandc", "hclk_nandc"; 278 status = "disabled"; 279 }; 280 281 emmc: dwmmc@30110000 { 282 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 283 clock-freq-min-max = <400000 150000000>; 284 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 285 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 286 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 287 fifo-depth = <0x100>; 288 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 289 reg = <0x30110000 0x4000>; 290 status = "disabled"; 291 }; 292 293 sdio: dwmmc@30120000 { 294 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 295 clock-freq-min-max = <400000 150000000>; 296 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 297 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 298 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 299 fifo-depth = <0x100>; 300 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 301 reg = <0x30120000 0x4000>; 302 status = "disabled"; 303 }; 304 305 sdmmc: dwmmc@30130000 { 306 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 307 clock-freq-min-max = <400000 100000000>; 308 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 309 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 310 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 311 cd-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; 312 fifo-depth = <0x100>; 313 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 314 reg = <0x30130000 0x4000>; 315 status = "disabled"; 316 }; 317 318 usb_host_ehci: usb@30140000 { 319 compatible = "generic-ehci"; 320 reg = <0x30140000 0x20000>; 321 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 322 phys = <&u2phy_host>; 323 phy-names = "usb"; 324 status = "disabled"; 325 }; 326 327 usb_host_ohci: usb@30160000 { 328 compatible = "generic-ohci"; 329 reg = <0x30160000 0x20000>; 330 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 331 phys = <&u2phy_host>; 332 phy-names = "usb"; 333 status = "disabled"; 334 }; 335 336 usb20_otg: usb@30180000 { 337 compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb", 338 "snps,dwc2"; 339 reg = <0x30180000 0x40000>; 340 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 341 hnp-srp-disable; 342 dr_mode = "otg"; 343 phys = <&u2phy_otg>; 344 phy-names = "usb"; 345 status = "disabled"; 346 }; 347 348 sfc: sfc@301c0000 { 349 compatible = "rockchip,sfc"; 350 reg = <0x301c0000 0x200>; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 355 clock-names = "clk_sfc", "hclk_sfc"; 356 pinctrl-0 = <&sfc_pins>; 357 pinctrl-names = "default"; 358 status = "disabled"; 359 }; 360 361 gmac: ethernet@30200000 { 362 compatible = "rockchip,rv1108-gmac"; 363 reg = <0x30200000 0x10000>; 364 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 365 interrupt-names = "macirq"; 366 rockchip,grf = <&grf>; 367 clocks = <&cru SCLK_MAC>, 368 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 369 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 370 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 371 clock-names = "stmmaceth", 372 "mac_clk_rx", "mac_clk_tx", 373 "clk_mac_ref", "clk_mac_refout", 374 "aclk_mac", "pclk_mac"; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&rmii_pins>; 377 phy-mode = "rmii"; 378 max-speed = <100>; 379 status = "disabled"; 380 }; 381 382 gic: interrupt-controller@32010000 { 383 compatible = "arm,gic-400"; 384 interrupt-controller; 385 #interrupt-cells = <3>; 386 #address-cells = <0>; 387 388 reg = <0x32011000 0x1000>, 389 <0x32012000 0x1000>, 390 <0x32014000 0x2000>, 391 <0x32016000 0x2000>; 392 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 393 }; 394 395 pinctrl: pinctrl { 396 compatible = "rockchip,rv1108-pinctrl"; 397 rockchip,grf = <&grf>; 398 rockchip,pmu = <&pmugrf>; 399 #address-cells = <1>; 400 #size-cells = <1>; 401 ranges; 402 403 gpio0: gpio0@20030000 { 404 compatible = "rockchip,gpio-bank"; 405 reg = <0x20030000 0x100>; 406 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&xin24m>; 408 409 gpio-controller; 410 #gpio-cells = <2>; 411 412 interrupt-controller; 413 #interrupt-cells = <2>; 414 }; 415 416 gpio1: gpio1@10310000 { 417 compatible = "rockchip,gpio-bank"; 418 reg = <0x10310000 0x100>; 419 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&xin24m>; 421 422 gpio-controller; 423 #gpio-cells = <2>; 424 425 interrupt-controller; 426 #interrupt-cells = <2>; 427 }; 428 429 gpio2: gpio2@10320000 { 430 compatible = "rockchip,gpio-bank"; 431 reg = <0x10320000 0x100>; 432 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&xin24m>; 434 435 gpio-controller; 436 #gpio-cells = <2>; 437 438 interrupt-controller; 439 #interrupt-cells = <2>; 440 }; 441 442 gpio3: gpio3@10330000 { 443 compatible = "rockchip,gpio-bank"; 444 reg = <0x10330000 0x100>; 445 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&xin24m>; 447 448 gpio-controller; 449 #gpio-cells = <2>; 450 451 interrupt-controller; 452 #interrupt-cells = <2>; 453 }; 454 455 pcfg_pull_up: pcfg-pull-up { 456 bias-pull-up; 457 }; 458 459 pcfg_pull_down: pcfg-pull-down { 460 bias-pull-down; 461 }; 462 463 pcfg_pull_none: pcfg-pull-none { 464 bias-disable; 465 }; 466 467 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 468 drive-strength = <8>; 469 }; 470 471 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 472 drive-strength = <12>; 473 }; 474 475 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 476 bias-pull-up; 477 drive-strength = <8>; 478 }; 479 480 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { 481 drive-strength = <4>; 482 }; 483 484 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { 485 bias-pull-up; 486 drive-strength = <4>; 487 }; 488 489 pcfg_pull_none_smt: pcfg-pull-none-smt { 490 bias-disable; 491 input-schmitt-enable; 492 }; 493 494 pcfg_output_high: pcfg-output-high { 495 output-high; 496 }; 497 498 pcfg_output_low: pcfg-output-low { 499 output-low; 500 }; 501 502 pcfg_input_high: pcfg-input-high { 503 bias-pull-up; 504 input-enable; 505 }; 506 507 pwm0 { 508 pwm0_pin: pwm0-pin { 509 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 510 }; 511 }; 512 513 gmac { 514 rmii_pins: rmii-pins { 515 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 516 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, 517 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 518 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 519 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 520 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, 521 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, 522 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, 523 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, 524 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 525 }; 526 }; 527 528 gpio1_lcdc { 529 lcdc_mipi_data: lcdc-mipi_data { 530 rockchip,pins = <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, /* DSI_CLKP */ 531 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, /* DSI_CLKN */ 532 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, /* D0P */ 533 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, /* D0N */ 534 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* D1P */ 535 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* D1N */ 536 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* D2P */ 537 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* D2N */ 538 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* D3P */ 539 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* D3N */ 540 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* D10 */ 541 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* D11 */ 542 }; 543 }; 544 545 i2c0 { 546 i2c0_xfer: i2c0-xfer { 547 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>, 548 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>; 549 }; 550 }; 551 552 i2c1 { 553 i2c1_xfer: i2c1-xfer { 554 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, 555 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 556 }; 557 }; 558 559 i2c2m1 { 560 i2c2m1_xfer: i2c2m1-xfer { 561 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, 562 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; 563 }; 564 565 i2c2m1_gpio: i2c2m1-gpio { 566 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, 567 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 568 }; 569 }; 570 571 i2c2m05v { 572 i2c2m05v_xfer: i2c2m05v-xfer { 573 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 574 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; 575 }; 576 577 i2c2m05v_gpio: i2c2m05v-gpio { 578 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, 579 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 580 }; 581 }; 582 583 i2c3 { 584 i2c3_xfer: i2c3-xfer { 585 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 586 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 587 }; 588 }; 589 590 sfc { 591 sfc_pins: sfc-pins { 592 rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, 593 <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, 594 <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, 595 <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, 596 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 597 <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; 598 }; 599 }; 600 601 sdmmc { 602 sdmmc_clk: sdmmc-clk { 603 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 604 }; 605 606 sdmmc_cmd: sdmmc-cmd { 607 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; 608 }; 609 610 sdmmc_cd: sdmmc-cd { 611 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; 612 }; 613 614 sdmmc_bus1: sdmmc-bus1 { 615 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; 616 }; 617 618 sdmmc_bus4: sdmmc-bus4 { 619 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, 620 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, 621 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, 622 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; 623 }; 624 }; 625 626 uart0 { 627 uart0_xfer: uart0-xfer { 628 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, 629 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 630 }; 631 632 uart0_cts: uart0-cts { 633 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; 634 }; 635 636 uart0_rts: uart0-rts { 637 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 638 }; 639 640 uart0_rts_gpio: uart0-rts-gpio { 641 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 642 }; 643 }; 644 645 uart1 { 646 uart1_xfer: uart1-xfer { 647 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, 648 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; 649 }; 650 651 uart1_cts: uart1-cts { 652 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 653 }; 654 655 uart01rts: uart1-rts { 656 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 657 }; 658 }; 659 660 uart2m0 { 661 uart2m0_xfer: uart2m0-xfer { 662 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, 663 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 664 }; 665 }; 666 667 uart2m1 { 668 uart2m1_xfer: uart2m1-xfer { 669 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, 670 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 671 }; 672 }; 673 674 uart2_5v { 675 uart2_5v_cts: uart2_5v-cts { 676 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; 677 }; 678 679 uart2_5v_rts: uart2_5v-rts { 680 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 681 }; 682 }; 683 }; 684 685 dmc: dmc@202b0000 { 686 compatible = "rockchip,rv1108-dmc"; 687 reg = <0x202b0000 0x400 688 0x20210000 0x400 689 0x31070000 0x40 690 0x10300000 0xf94 691 0x20060000 0x38c 692 0x20200000 0x1f0 693 0x20010000 0x78>; 694 }; 695 696 vop: vop@30040000 { 697 compatible = "rockchip,rv1108-vop"; 698 reg = <0x30040000 0xe00>; 699 reg-names = "regs"; 700 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 702 <&cru HCLK_VOP>; 703 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 704 status = "disabled"; 705 706 vop_out: port { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 710 vop_out_mipi: endpoint@0 { 711 reg = <0>; 712 remote-endpoint = <&mipi_in_vop>; 713 }; 714 }; 715 }; 716}; 717
