1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang<zhangqing@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/io.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/rockchip/cpu.h>
14 #include <linux/syscore_ops.h>
15 #include <dt-bindings/clock/px30-cru.h>
16 #include "clk.h"
17
18 #define PX30_GRF_SOC_STATUS0 0x480
19
20 enum px30_plls {
21 apll, dpll, cpll, npll, apll_b_h, apll_b_l,
22 };
23
24 enum px30_pmu_plls {
25 gpll,
26 };
27
28 static struct rockchip_pll_rate_table px30_pll_rates[] = {
29 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
30 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
31 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
32 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
51 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
52 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
53 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
54 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
55 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
56 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
57 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
58 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
59 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
60 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
61 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
62 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
63 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
64 RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
65 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
66 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
67 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
68 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
69 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
70 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
71 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
72 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
73 { /* sentinel */ },
74 };
75
76 #define PX30_DIV_ACLKM_MASK 0x7
77 #define PX30_DIV_ACLKM_SHIFT 12
78 #define PX30_DIV_PCLK_DBG_MASK 0xf
79 #define PX30_DIV_PCLK_DBG_SHIFT 8
80
81 #define PX30_CLKSEL0(_aclk_core, _pclk_dbg) \
82 { \
83 .reg = PX30_CLKSEL_CON(0), \
84 .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \
85 PX30_DIV_ACLKM_SHIFT) | \
86 HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \
87 PX30_DIV_PCLK_DBG_SHIFT), \
88 }
89
90 #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
91 { \
92 .prate = _prate, \
93 .divs = { \
94 PX30_CLKSEL0(_aclk_core, _pclk_dbg), \
95 }, \
96 }
97
98 static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {
99 PX30_CPUCLK_RATE(1608000000, 1, 7),
100 PX30_CPUCLK_RATE(1584000000, 1, 7),
101 PX30_CPUCLK_RATE(1560000000, 1, 7),
102 PX30_CPUCLK_RATE(1536000000, 1, 7),
103 PX30_CPUCLK_RATE(1512000000, 1, 7),
104 PX30_CPUCLK_RATE(1488000000, 1, 5),
105 PX30_CPUCLK_RATE(1464000000, 1, 5),
106 PX30_CPUCLK_RATE(1440000000, 1, 5),
107 PX30_CPUCLK_RATE(1416000000, 1, 5),
108 PX30_CPUCLK_RATE(1392000000, 1, 5),
109 PX30_CPUCLK_RATE(1368000000, 1, 5),
110 PX30_CPUCLK_RATE(1344000000, 1, 5),
111 PX30_CPUCLK_RATE(1320000000, 1, 5),
112 PX30_CPUCLK_RATE(1296000000, 1, 5),
113 PX30_CPUCLK_RATE(1272000000, 1, 5),
114 PX30_CPUCLK_RATE(1248000000, 1, 5),
115 PX30_CPUCLK_RATE(1224000000, 1, 5),
116 PX30_CPUCLK_RATE(1200000000, 1, 5),
117 PX30_CPUCLK_RATE(1104000000, 1, 5),
118 PX30_CPUCLK_RATE(1008000000, 1, 5),
119 PX30_CPUCLK_RATE(912000000, 1, 5),
120 PX30_CPUCLK_RATE(816000000, 1, 3),
121 PX30_CPUCLK_RATE(696000000, 1, 3),
122 PX30_CPUCLK_RATE(600000000, 1, 3),
123 PX30_CPUCLK_RATE(408000000, 1, 1),
124 PX30_CPUCLK_RATE(312000000, 1, 1),
125 PX30_CPUCLK_RATE(216000000, 1, 1),
126 PX30_CPUCLK_RATE(96000000, 1, 1),
127 };
128
129 static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
130 .core_reg[0] = PX30_CLKSEL_CON(0),
131 .div_core_shift[0] = 0,
132 .div_core_mask[0] = 0xf,
133 .num_cores = 1,
134 .mux_core_alt = 1,
135 .mux_core_main = 0,
136 .mux_core_shift = 7,
137 .mux_core_mask = 0x1,
138 .pll_name = "pll_apll",
139 };
140
141 PNAME(mux_pll_p) = { "xin24m"};
142 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
143 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
144 PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" };
145 PNAME(mux_gpll_dmycpll_usb480m_npll_p) = { "gpll", "dummy_cpll", "usb480m", "npll" };
146 PNAME(mux_gpll_dmycpll_usb480m_dmynpll_p) = { "gpll", "dummy_cpll", "usb480m", "dummy_npll" };
147 PNAME(mux_cpll_npll_p) = { "cpll", "npll" };
148 PNAME(mux_npll_cpll_p) = { "npll", "cpll" };
149 PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
150 PNAME(mux_gpll_npll_p) = { "gpll", "dummy_npll" };
151 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
152 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll"};
153 PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "dummy_npll" };
154 PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "dummy_npll", "xin24m" };
155 PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "dummy_npll"};
156 PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
157 PNAME(mux_i2s0_tx_p) = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"};
158 PNAME(mux_i2s0_rx_p) = { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"};
159 PNAME(mux_i2s1_p) = { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"};
160 PNAME(mux_i2s2_p) = { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"};
161 PNAME(mux_i2s0_tx_out_p) = { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"};
162 PNAME(mux_i2s0_rx_out_p) = { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"};
163 PNAME(mux_i2s1_out_p) = { "clk_i2s1", "xin12m"};
164 PNAME(mux_i2s2_out_p) = { "clk_i2s2", "xin12m"};
165 PNAME(mux_i2s0_tx_rx_p) = { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"};
166 PNAME(mux_i2s0_rx_tx_p) = { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"};
167 PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "dummy_npll" };
168 PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" };
169 PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" };
170 PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" };
171 PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" };
172 PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" };
173 PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "dummy_npll", "usb480m" };
174 PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
175 PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
176 PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
177 PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
178 PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
179 PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
180 PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" };
181 PNAME(mux_gmac_rmii_sel_p) = { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" };
182 PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", };
183 PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" };
184 PNAME(mux_uart0_pmu_p) = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" };
185 PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
186 PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
187 PNAME(mux_gpu_p) = { "clk_gpu_div", "clk_gpu_np5" };
188
189 static struct rockchip_pll_clock px30_pll_clks[] __initdata = {
190 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
191 0, PX30_PLL_CON(0),
192 PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
193 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
194 0, PX30_PLL_CON(8),
195 PX30_MODE_CON, 4, 1, 0, NULL),
196 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
197 0, PX30_PLL_CON(16),
198 PX30_MODE_CON, 2, 2, 0, px30_pll_rates),
199 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
200 CLK_IS_CRITICAL, PX30_PLL_CON(24),
201 PX30_MODE_CON, 6, 4, 0, px30_pll_rates),
202 };
203
204 static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = {
205 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0),
206 PX30_PMU_MODE, 0, 3, 0, px30_pll_rates),
207 };
208
209 #define MFLAGS CLK_MUX_HIWORD_MASK
210 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
211 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
212
213 static struct rockchip_clk_branch px30_pdm_fracmux __initdata =
214 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
215 PX30_CLKSEL_CON(26), 15, 1, MFLAGS);
216
217 static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata =
218 MUX(SCLK_I2S0_TX_MUX, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
219 PX30_CLKSEL_CON(28), 10, 2, MFLAGS);
220
221 static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata =
222 MUX(SCLK_I2S0_RX_MUX, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
223 PX30_CLKSEL_CON(58), 10, 2, MFLAGS);
224
225 static struct rockchip_clk_branch px30_i2s1_fracmux __initdata =
226 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
227 PX30_CLKSEL_CON(30), 10, 2, MFLAGS);
228
229 static struct rockchip_clk_branch px30_i2s2_fracmux __initdata =
230 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
231 PX30_CLKSEL_CON(32), 10, 2, MFLAGS);
232
233 static struct rockchip_clk_branch px30_uart1_fracmux __initdata =
234 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
235 PX30_CLKSEL_CON(35), 14, 2, MFLAGS);
236
237 static struct rockchip_clk_branch px30_uart2_fracmux __initdata =
238 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
239 PX30_CLKSEL_CON(38), 14, 2, MFLAGS);
240
241 static struct rockchip_clk_branch px30_uart3_fracmux __initdata =
242 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
243 PX30_CLKSEL_CON(41), 14, 2, MFLAGS);
244
245 static struct rockchip_clk_branch px30_uart4_fracmux __initdata =
246 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
247 PX30_CLKSEL_CON(44), 14, 2, MFLAGS);
248
249 static struct rockchip_clk_branch px30_uart5_fracmux __initdata =
250 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
251 PX30_CLKSEL_CON(47), 14, 2, MFLAGS);
252
253 static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata =
254 MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT,
255 PX30_CLKSEL_CON(5), 14, 2, MFLAGS);
256
257 static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata =
258 MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT,
259 PX30_CLKSEL_CON(8), 14, 2, MFLAGS);
260
261 static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata =
262 MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
263 PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
264
265 static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata =
266 MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT,
267 PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
268
269 static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
270 /*
271 * Clock-Architecture Diagram 1
272 */
273
274 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
275 PX30_MODE_CON, 8, 2, MFLAGS),
276 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
277
278 /*
279 * Clock-Architecture Diagram 3
280 */
281
282 /* PD_CORE */
283 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
284 PX30_CLKGATE_CON(0), 0, GFLAGS),
285 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
286 PX30_CLKGATE_CON(0), 0, GFLAGS),
287 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
288 PX30_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
289 PX30_CLKGATE_CON(0), 2, GFLAGS),
290 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
291 PX30_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
292 PX30_CLKGATE_CON(0), 1, GFLAGS),
293 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
294 PX30_CLKGATE_CON(0), 4, GFLAGS),
295 GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED,
296 PX30_CLKGATE_CON(17), 5, GFLAGS),
297 GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
298 PX30_CLKGATE_CON(0), 5, GFLAGS),
299 GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED,
300 PX30_CLKGATE_CON(0), 6, GFLAGS),
301 GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED,
302 PX30_CLKGATE_CON(17), 6, GFLAGS),
303
304 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
305 PX30_CLKGATE_CON(0), 3, GFLAGS),
306 GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
307 PX30_CLKGATE_CON(17), 4, GFLAGS),
308
309 /* PD_GPU */
310 GATE(SCLK_GPU, "clk_gpu", "clk_gpu_src", 0,
311 PX30_CLKGATE_CON(0), 10, GFLAGS),
312 COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED,
313 PX30_CLKSEL_CON(1), 13, 2, DFLAGS,
314 PX30_CLKGATE_CON(17), 10, GFLAGS),
315 GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IS_CRITICAL,
316 PX30_CLKGATE_CON(0), 11, GFLAGS),
317 GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED,
318 PX30_CLKGATE_CON(17), 8, GFLAGS),
319 GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED,
320 PX30_CLKGATE_CON(17), 9, GFLAGS),
321
322 /*
323 * Clock-Architecture Diagram 4
324 */
325
326 /* PD_DDR */
327 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
328 PX30_CLKGATE_CON(0), 7, GFLAGS),
329 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
330 PX30_CLKGATE_CON(0), 13, GFLAGS),
331 COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p,
332 CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 7, 1, 0, 3,
333 ROCKCHIP_DDRCLK_SIP_V2),
334 COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
335 PX30_CLKSEL_CON(2), 4, 1, MFLAGS,
336 PX30_CLKGATE_CON(1), 13, GFLAGS),
337 GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
338 PX30_CLKGATE_CON(1), 15, GFLAGS),
339 GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
340 PX30_CLKGATE_CON(1), 8, GFLAGS),
341 GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
342 PX30_CLKGATE_CON(1), 5, GFLAGS),
343 GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
344 PX30_CLKGATE_CON(1), 6, GFLAGS),
345 GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
346 PX30_CLKGATE_CON(1), 6, GFLAGS),
347 GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
348 PX30_CLKGATE_CON(1), 11, GFLAGS),
349
350 GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED,
351 PX30_CLKGATE_CON(0), 15, GFLAGS),
352
353 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED,
354 PX30_CLKSEL_CON(2), 8, 5, DFLAGS,
355 PX30_CLKGATE_CON(1), 1, GFLAGS),
356 GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
357 PX30_CLKGATE_CON(1), 10, GFLAGS),
358 GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED,
359 PX30_CLKGATE_CON(1), 7, GFLAGS),
360 GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
361 PX30_CLKGATE_CON(1), 9, GFLAGS),
362 GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
363 PX30_CLKGATE_CON(1), 12, GFLAGS),
364 GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
365 PX30_CLKGATE_CON(1), 14, GFLAGS),
366 GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED,
367 PX30_CLKGATE_CON(1), 3, GFLAGS),
368
369 /*
370 * Clock-Architecture Diagram 5
371 */
372
373 /* PD_VI */
374 COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0,
375 PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
376 PX30_CLKGATE_CON(4), 8, GFLAGS),
377 COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0,
378 PX30_CLKSEL_CON(11), 8, 4, DFLAGS,
379 PX30_CLKGATE_CON(4), 12, GFLAGS),
380 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
381 PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
382 PX30_CLKGATE_CON(4), 9, GFLAGS),
383 COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0,
384 PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS,
385 PX30_CLKGATE_CON(4), 11, GFLAGS),
386 GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0,
387 PX30_CLKGATE_CON(4), 13, GFLAGS),
388 GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0,
389 PX30_CLKGATE_CON(4), 14, GFLAGS),
390
391 /*
392 * Clock-Architecture Diagram 6
393 */
394
395 /* PD_VO */
396 COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0,
397 PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS,
398 PX30_CLKGATE_CON(2), 0, GFLAGS),
399 COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0,
400 PX30_CLKSEL_CON(3), 8, 4, DFLAGS,
401 PX30_CLKGATE_CON(2), 12, GFLAGS),
402 COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0,
403 PX30_CLKSEL_CON(3), 12, 4, DFLAGS,
404 PX30_CLKGATE_CON(2), 13, GFLAGS),
405 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0,
406 PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
407 PX30_CLKGATE_CON(2), 1, GFLAGS),
408
409 COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0,
410 PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS,
411 PX30_CLKGATE_CON(2), 5, GFLAGS),
412 COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
413 PX30_CLKSEL_CON(5), 11, 1, MFLAGS, 0, 8, DFLAGS,
414 PX30_CLKGATE_CON(2), 2, GFLAGS),
415 COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT,
416 PX30_CLKSEL_CON(6), 0,
417 PX30_CLKGATE_CON(2), 3, GFLAGS,
418 &px30_dclk_vopb_fracmux),
419 GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
420 PX30_CLKGATE_CON(2), 4, GFLAGS),
421 COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
422 PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS,
423 PX30_CLKGATE_CON(2), 6, GFLAGS),
424 COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,
425 PX30_CLKSEL_CON(9), 0,
426 PX30_CLKGATE_CON(2), 7, GFLAGS,
427 &px30_dclk_vopl_fracmux),
428 GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
429 PX30_CLKGATE_CON(2), 8, GFLAGS),
430
431 /* PD_VPU */
432 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0,
433 PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
434 PX30_CLKGATE_CON(4), 0, GFLAGS),
435 COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0,
436 PX30_CLKSEL_CON(10), 8, 4, DFLAGS,
437 PX30_CLKGATE_CON(4), 2, GFLAGS),
438 COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0,
439 PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS,
440 PX30_CLKGATE_CON(4), 1, GFLAGS),
441
442 /*
443 * Clock-Architecture Diagram 7
444 */
445
446 COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
447 PX30_CLKSEL_CON(14), 15, 1, MFLAGS,
448 PX30_CLKGATE_CON(5), 7, GFLAGS),
449 COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IS_CRITICAL,
450 PX30_CLKSEL_CON(14), 0, 5, DFLAGS,
451 PX30_CLKGATE_CON(5), 8, GFLAGS),
452 DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IS_CRITICAL,
453 PX30_CLKSEL_CON(14), 8, 5, DFLAGS),
454
455 /* PD_MMC_NAND */
456 GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0,
457 PX30_CLKGATE_CON(6), 0, GFLAGS),
458 COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_gpll_cpll_npll_p, 0,
459 PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
460 PX30_CLKGATE_CON(5), 11, GFLAGS),
461 COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0,
462 PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 8, 5, DFLAGS,
463 PX30_CLKGATE_CON(5), 12, GFLAGS),
464 COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p,
465 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
466 PX30_CLKSEL_CON(15), 15, 1, MFLAGS,
467 PX30_CLKGATE_CON(5), 13, GFLAGS),
468
469 COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_xin24m_p, 0,
470 PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS,
471 PX30_CLKGATE_CON(6), 1, GFLAGS),
472 COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
473 mux_gpll_cpll_npll_xin24m_p, 0,
474 PX30_CLKSEL_CON(18), 14, 2, MFLAGS,
475 PX30_CLKSEL_CON(19), 0, 8, DFLAGS,
476 PX30_CLKGATE_CON(6), 2, GFLAGS),
477 COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p,
478 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
479 PX30_CLKSEL_CON(19), 15, 1, MFLAGS,
480 PX30_CLKGATE_CON(6), 3, GFLAGS),
481
482 COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
483 PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
484 PX30_CLKGATE_CON(6), 4, GFLAGS),
485 COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
486 PX30_CLKSEL_CON(20), 14, 2, MFLAGS,
487 PX30_CLKSEL_CON(21), 0, 8, DFLAGS,
488 PX30_CLKGATE_CON(6), 5, GFLAGS),
489 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p,
490 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
491 PX30_CLKSEL_CON(21), 15, 1, MFLAGS,
492 PX30_CLKGATE_CON(6), 6, GFLAGS),
493
494 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
495 PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS,
496 PX30_CLKGATE_CON(6), 7, GFLAGS),
497
498 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
499 PX30_SDMMC_CON0, 1),
500 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
501 PX30_SDMMC_CON1, 1),
502
503 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
504 PX30_SDIO_CON0, 1),
505 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
506 PX30_SDIO_CON1, 1),
507
508 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
509 PX30_EMMC_CON0, 1),
510 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
511 PX30_EMMC_CON1, 1),
512
513 /* PD_SDCARD */
514 GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0,
515 PX30_CLKGATE_CON(6), 12, GFLAGS),
516 COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
517 PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS,
518 PX30_CLKGATE_CON(6), 13, GFLAGS),
519 COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
520 PX30_CLKSEL_CON(16), 14, 2, MFLAGS,
521 PX30_CLKSEL_CON(17), 0, 8, DFLAGS,
522 PX30_CLKGATE_CON(6), 14, GFLAGS),
523 COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p,
524 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
525 PX30_CLKSEL_CON(17), 15, 1, MFLAGS,
526 PX30_CLKGATE_CON(6), 15, GFLAGS),
527
528 /* PD_USB */
529 GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", CLK_IS_CRITICAL,
530 PX30_CLKGATE_CON(7), 2, GFLAGS),
531 GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0,
532 PX30_CLKGATE_CON(7), 3, GFLAGS),
533
534 /* PD_GMAC */
535 COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0,
536 PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS,
537 PX30_CLKGATE_CON(7), 11, GFLAGS),
538 MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT,
539 PX30_CLKSEL_CON(23), 6, 1, MFLAGS),
540 GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0,
541 PX30_CLKGATE_CON(7), 15, GFLAGS),
542 GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0,
543 PX30_CLKGATE_CON(7), 13, GFLAGS),
544 FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2),
545 FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20),
546 MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT,
547 PX30_CLKSEL_CON(23), 7, 1, MFLAGS),
548
549 GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0,
550 PX30_CLKGATE_CON(7), 10, GFLAGS),
551 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
552 PX30_CLKSEL_CON(23), 0, 4, DFLAGS,
553 PX30_CLKGATE_CON(7), 12, GFLAGS),
554
555 COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0,
556 PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
557 PX30_CLKGATE_CON(8), 5, GFLAGS),
558
559 /*
560 * Clock-Architecture Diagram 8
561 */
562
563 /* PD_BUS */
564 COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
565 PX30_CLKSEL_CON(23), 15, 1, MFLAGS,
566 PX30_CLKGATE_CON(8), 6, GFLAGS),
567 COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IS_CRITICAL,
568 PX30_CLKSEL_CON(24), 0, 5, DFLAGS,
569 PX30_CLKGATE_CON(8), 8, GFLAGS),
570 COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IS_CRITICAL,
571 PX30_CLKSEL_CON(23), 8, 5, DFLAGS,
572 PX30_CLKGATE_CON(8), 7, GFLAGS),
573 COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
574 PX30_CLKSEL_CON(24), 8, 2, DFLAGS,
575 PX30_CLKGATE_CON(8), 9, GFLAGS),
576 GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IS_CRITICAL,
577 PX30_CLKGATE_CON(8), 10, GFLAGS),
578
579 COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0,
580 PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS,
581 PX30_CLKGATE_CON(9), 9, GFLAGS),
582 COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
583 PX30_CLKSEL_CON(27), 0,
584 PX30_CLKGATE_CON(9), 10, GFLAGS,
585 &px30_pdm_fracmux),
586 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
587 PX30_CLKGATE_CON(9), 11, GFLAGS),
588
589 COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0,
590 PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS,
591 PX30_CLKGATE_CON(9), 12, GFLAGS),
592 COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT,
593 PX30_CLKSEL_CON(29), 0,
594 PX30_CLKGATE_CON(9), 13, GFLAGS,
595 &px30_i2s0_tx_fracmux),
596 COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
597 PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
598 PX30_CLKGATE_CON(9), 14, GFLAGS),
599 COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, CLK_SET_RATE_PARENT,
600 PX30_CLKSEL_CON(28), 14, 2, MFLAGS,
601 PX30_CLKGATE_CON(9), 15, GFLAGS),
602 GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT,
603 PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK),
604
605 COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0,
606 PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS,
607 PX30_CLKGATE_CON(17), 0, GFLAGS),
608 COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT,
609 PX30_CLKSEL_CON(59), 0,
610 PX30_CLKGATE_CON(17), 1, GFLAGS,
611 &px30_i2s0_rx_fracmux),
612 COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT,
613 PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
614 PX30_CLKGATE_CON(17), 2, GFLAGS),
615 COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0,
616 PX30_CLKSEL_CON(58), 14, 2, MFLAGS,
617 PX30_CLKGATE_CON(17), 3, GFLAGS),
618 GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT,
619 PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK),
620
621 COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0,
622 PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS,
623 PX30_CLKGATE_CON(10), 0, GFLAGS),
624 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT,
625 PX30_CLKSEL_CON(31), 0,
626 PX30_CLKGATE_CON(10), 1, GFLAGS,
627 &px30_i2s1_fracmux),
628 GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
629 PX30_CLKGATE_CON(10), 2, GFLAGS),
630 COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, CLK_SET_RATE_PARENT,
631 PX30_CLKSEL_CON(30), 15, 1, MFLAGS,
632 PX30_CLKGATE_CON(10), 3, GFLAGS),
633 GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT,
634 PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK),
635
636 COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0,
637 PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS,
638 PX30_CLKGATE_CON(10), 4, GFLAGS),
639 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT,
640 PX30_CLKSEL_CON(33), 0,
641 PX30_CLKGATE_CON(10), 5, GFLAGS,
642 &px30_i2s2_fracmux),
643 GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
644 PX30_CLKGATE_CON(10), 6, GFLAGS),
645 COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0,
646 PX30_CLKSEL_CON(32), 15, 1, MFLAGS,
647 PX30_CLKGATE_CON(10), 7, GFLAGS),
648 GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT,
649 PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK),
650
651 COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT,
652 PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS,
653 PX30_CLKGATE_CON(10), 12, GFLAGS),
654 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0,
655 PX30_CLKSEL_CON(35), 0, 5, DFLAGS,
656 PX30_CLKGATE_CON(10), 13, GFLAGS),
657 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
658 PX30_CLKSEL_CON(36), 0,
659 PX30_CLKGATE_CON(10), 14, GFLAGS,
660 &px30_uart1_fracmux),
661 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
662 PX30_CLKGATE_CON(10), 15, GFLAGS),
663
664 COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0,
665 PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS,
666 PX30_CLKGATE_CON(11), 0, GFLAGS),
667 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0,
668 PX30_CLKSEL_CON(38), 0, 5, DFLAGS,
669 PX30_CLKGATE_CON(11), 1, GFLAGS),
670 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
671 PX30_CLKSEL_CON(39), 0,
672 PX30_CLKGATE_CON(11), 2, GFLAGS,
673 &px30_uart2_fracmux),
674 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
675 PX30_CLKGATE_CON(11), 3, GFLAGS),
676
677 COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0,
678 PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS,
679 PX30_CLKGATE_CON(11), 4, GFLAGS),
680 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0,
681 PX30_CLKSEL_CON(41), 0, 5, DFLAGS,
682 PX30_CLKGATE_CON(11), 5, GFLAGS),
683 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
684 PX30_CLKSEL_CON(42), 0,
685 PX30_CLKGATE_CON(11), 6, GFLAGS,
686 &px30_uart3_fracmux),
687 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
688 PX30_CLKGATE_CON(11), 7, GFLAGS),
689
690 COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0,
691 PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS,
692 PX30_CLKGATE_CON(11), 8, GFLAGS),
693 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0,
694 PX30_CLKSEL_CON(44), 0, 5, DFLAGS,
695 PX30_CLKGATE_CON(11), 9, GFLAGS),
696 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
697 PX30_CLKSEL_CON(45), 0,
698 PX30_CLKGATE_CON(11), 10, GFLAGS,
699 &px30_uart4_fracmux),
700 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
701 PX30_CLKGATE_CON(11), 11, GFLAGS),
702
703 COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0,
704 PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS,
705 PX30_CLKGATE_CON(11), 12, GFLAGS),
706 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0,
707 PX30_CLKSEL_CON(47), 0, 5, DFLAGS,
708 PX30_CLKGATE_CON(11), 13, GFLAGS),
709 COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
710 PX30_CLKSEL_CON(48), 0,
711 PX30_CLKGATE_CON(11), 14, GFLAGS,
712 &px30_uart5_fracmux),
713 GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
714 PX30_CLKGATE_CON(11), 15, GFLAGS),
715
716 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0,
717 PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS,
718 PX30_CLKGATE_CON(12), 0, GFLAGS),
719 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
720 PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS,
721 PX30_CLKGATE_CON(12), 1, GFLAGS),
722 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
723 PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS,
724 PX30_CLKGATE_CON(12), 2, GFLAGS),
725 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
726 PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS,
727 PX30_CLKGATE_CON(12), 3, GFLAGS),
728 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
729 PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS,
730 PX30_CLKGATE_CON(12), 5, GFLAGS),
731 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
732 PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS,
733 PX30_CLKGATE_CON(12), 6, GFLAGS),
734 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
735 PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS,
736 PX30_CLKGATE_CON(12), 7, GFLAGS),
737 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
738 PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS,
739 PX30_CLKGATE_CON(12), 8, GFLAGS),
740
741 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
742 PX30_CLKGATE_CON(13), 0, GFLAGS),
743 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
744 PX30_CLKGATE_CON(13), 1, GFLAGS),
745 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
746 PX30_CLKGATE_CON(13), 2, GFLAGS),
747 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
748 PX30_CLKGATE_CON(13), 3, GFLAGS),
749 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
750 PX30_CLKGATE_CON(13), 4, GFLAGS),
751 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
752 PX30_CLKGATE_CON(13), 5, GFLAGS),
753
754 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
755 PX30_CLKSEL_CON(54), 0, 11, DFLAGS,
756 PX30_CLKGATE_CON(12), 9, GFLAGS),
757 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
758 PX30_CLKSEL_CON(55), 0, 11, DFLAGS,
759 PX30_CLKGATE_CON(12), 10, GFLAGS),
760
761 GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
762 PX30_CLKGATE_CON(12), 12, GFLAGS),
763
764 /* PD_CRYPTO */
765 GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0,
766 PX30_CLKGATE_CON(8), 12, GFLAGS),
767 GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0,
768 PX30_CLKGATE_CON(8), 13, GFLAGS),
769 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0,
770 PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
771 PX30_CLKGATE_CON(8), 14, GFLAGS),
772 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0,
773 PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5, DFLAGS,
774 PX30_CLKGATE_CON(8), 15, GFLAGS),
775
776 /*
777 * Clock-Architecture Diagram 9
778 */
779
780 /* PD_BUS_TOP */
781 GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS),
782 GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS),
783 GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS),
784 GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS),
785 GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS),
786 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS),
787 GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(16), 6, GFLAGS),
788 GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS),
789
790 /* PD_VI */
791 GATE(0, "aclk_vi_niu", "aclk_vi_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(4), 15, GFLAGS),
792 GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS),
793 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS),
794 GATE(0, "hclk_vi_niu", "hclk_vi_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(5), 0, GFLAGS),
795 GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS),
796 GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS),
797
798 /* PD_VO */
799 GATE(0, "aclk_vo_niu", "aclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 0, GFLAGS),
800 GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS),
801 GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS),
802 GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS),
803
804 GATE(0, "hclk_vo_niu", "hclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 1, GFLAGS),
805 GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS),
806 GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
807 GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS),
808
809 GATE(0, "pclk_vo_niu", "pclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 2, GFLAGS),
810 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS),
811
812 /* PD_BUS */
813 GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS),
814 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS),
815 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),
816 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),
817
818 /* aclk_dmac is controlled by sgrf_soc_con1[11]. */
819 SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),
820
821 GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),
822 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),
823 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),
824 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS),
825 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS),
826 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS),
827
828 GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS),
829 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS),
830 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS),
831 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(14), 6, GFLAGS),
832 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS),
833 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS),
834 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS),
835 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS),
836 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS),
837 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS),
838 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS),
839 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS),
840 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS),
841 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS),
842 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS),
843 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS),
844 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS),
845 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS),
846 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS),
847 GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS),
848 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS),
849 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS),
850 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS),
851 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS),
852 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS),
853 GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS),
854
855 /* PD_VPU */
856 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS),
857 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS),
858 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS),
859 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS),
860
861 /* PD_CRYPTO */
862 GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS),
863 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS),
864 GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS),
865 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS),
866
867 /* PD_SDCARD */
868 GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS),
869 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS),
870
871 /* PD_PERI */
872 GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(5), 9, GFLAGS),
873
874 /* PD_MMC_NAND */
875 GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS),
876 GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS),
877 GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS),
878 GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS),
879 GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS),
880
881 /* PD_USB */
882 GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IS_CRITICAL, PX30_CLKGATE_CON(7), 4, GFLAGS),
883 GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS),
884 GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS),
885 GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS),
886
887 /* PD_GMAC */
888 GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
889 PX30_CLKGATE_CON(8), 0, GFLAGS),
890 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
891 PX30_CLKGATE_CON(8), 2, GFLAGS),
892 GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
893 PX30_CLKGATE_CON(8), 1, GFLAGS),
894 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
895 PX30_CLKGATE_CON(8), 3, GFLAGS),
896 };
897
898 static struct rockchip_clk_branch px30_gpu_src_clk[] __initdata = {
899 COMPOSITE(0, "clk_gpu_src", mux_gpll_dmycpll_usb480m_dmynpll_p, 0,
900 PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 4, DFLAGS,
901 PX30_CLKGATE_CON(0), 8, GFLAGS),
902 };
903
904 static struct rockchip_clk_branch rk3326_gpu_src_clk[] __initdata = {
905 COMPOSITE(0, "clk_gpu_src", mux_gpll_dmycpll_usb480m_npll_p, 0,
906 PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 4, DFLAGS,
907 PX30_CLKGATE_CON(0), 8, GFLAGS),
908 };
909
910 static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
911 /*
912 * Clock-Architecture Diagram 2
913 */
914
915 COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
916 PX30_PMU_CLKSEL_CON(1), 0,
917 PX30_PMU_CLKGATE_CON(0), 13, GFLAGS,
918 &px30_rtc32k_pmu_fracmux),
919
920 COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
921 PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
922 PX30_PMU_CLKGATE_CON(0), 12, GFLAGS),
923
924 COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0,
925 PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS,
926 PX30_PMU_CLKGATE_CON(0), 14, GFLAGS),
927 COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
928 PX30_PMU_CLKSEL_CON(2), 15, 1, MFLAGS,
929 PX30_PMU_CLKGATE_CON(0), 15, GFLAGS),
930
931 COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0,
932 PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS,
933 PX30_PMU_CLKGATE_CON(1), 0, GFLAGS),
934 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0,
935 PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS,
936 PX30_PMU_CLKGATE_CON(1), 1, GFLAGS),
937 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
938 PX30_PMU_CLKSEL_CON(5), 0,
939 PX30_PMU_CLKGATE_CON(1), 2, GFLAGS,
940 &px30_uart0_pmu_fracmux),
941 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
942 PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),
943
944 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
945 PX30_PMU_CLKGATE_CON(1), 4, GFLAGS),
946
947 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", CLK_IS_CRITICAL,
948 PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
949 PX30_PMU_CLKGATE_CON(0), 0, GFLAGS),
950
951 COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0,
952 PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS,
953 PX30_PMU_CLKGATE_CON(1), 8, GFLAGS),
954 COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
955 PX30_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
956 PX30_PMU_CLKGATE_CON(1), 9, GFLAGS),
957 COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
958 PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS,
959 PX30_PMU_CLKGATE_CON(1), 10, GFLAGS),
960
961 /*
962 * Clock-Architecture Diagram 9
963 */
964
965 /* PD_PMU */
966 GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS),
967 GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS),
968 GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS),
969 GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS),
970 GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS),
971 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS),
972 GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS),
973 GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
974 };
975
976 static struct rockchip_clk_branch px30_clk_ddrphy_otp[] __initdata = {
977 COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
978 PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
979 FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
980 PX30_CLKGATE_CON(0), 14, GFLAGS),
981 FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x",
982 CLK_IGNORE_UNUSED, 1, 4,
983 PX30_CLKGATE_CON(1), 0, GFLAGS),
984
985 COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
986 PX30_CLKSEL_CON(56), 0, 3, DFLAGS,
987 PX30_CLKGATE_CON(12), 11, GFLAGS),
988 COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
989 PX30_CLKSEL_CON(56), 4, 2, DFLAGS,
990 PX30_CLKGATE_CON(13), 6, GFLAGS),
991 };
992
993 static struct rockchip_clk_branch px30s_clk_ddrphy_otp[] __initdata = {
994 COMPOSITE(0, "clk_ddrphy1x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
995 PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS,
996 PX30_CLKGATE_CON(0), 14, GFLAGS),
997 FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy1x",
998 CLK_IGNORE_UNUSED, 1, 4,
999 PX30_CLKGATE_CON(1), 0, GFLAGS),
1000
1001 COMPOSITE(SCLK_OTP_USR, "clk_otp_usr", mux_xin24m_gpll_p, 0,
1002 PX30_CLKSEL_CON(56), 8, 1, MFLAGS, 0, 8, DFLAGS,
1003 PX30_CLKGATE_CON(12), 11, GFLAGS),
1004 };
1005
1006 static __initdata struct rockchip_clk_provider *cru_ctx, *pmucru_ctx;
px30_register_armclk(void)1007 static void __init px30_register_armclk(void)
1008 {
1009 rockchip_clk_register_armclk(cru_ctx, ARMCLK, "armclk", 2,
1010 cru_ctx->clk_data.clks[PLL_APLL],
1011 pmucru_ctx->clk_data.clks[PLL_GPLL],
1012 &px30_cpuclk_data,
1013 px30_cpuclk_rates,
1014 ARRAY_SIZE(px30_cpuclk_rates));
1015 }
1016
px30_clk_init(struct device_node * np)1017 static void __init px30_clk_init(struct device_node *np)
1018 {
1019 struct rockchip_clk_provider *ctx;
1020 void __iomem *reg_base;
1021
1022 reg_base = of_iomap(np, 0);
1023 if (!reg_base) {
1024 pr_err("%s: could not map cru region\n", __func__);
1025 return;
1026 }
1027
1028 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1029 if (IS_ERR(ctx)) {
1030 pr_err("%s: rockchip clk init failed\n", __func__);
1031 iounmap(reg_base);
1032 return;
1033 }
1034 cru_ctx = ctx;
1035
1036 rockchip_clk_register_plls(ctx, px30_pll_clks,
1037 ARRAY_SIZE(px30_pll_clks),
1038 PX30_GRF_SOC_STATUS0);
1039
1040 if (pmucru_ctx)
1041 px30_register_armclk();
1042
1043 rockchip_clk_register_branches(ctx, px30_clk_branches,
1044 ARRAY_SIZE(px30_clk_branches));
1045 if (of_machine_is_compatible("rockchip,px30"))
1046 rockchip_clk_register_branches(ctx, px30_gpu_src_clk,
1047 ARRAY_SIZE(px30_gpu_src_clk));
1048 else
1049 rockchip_clk_register_branches(ctx, rk3326_gpu_src_clk,
1050 ARRAY_SIZE(rk3326_gpu_src_clk));
1051
1052 rockchip_soc_id_init();
1053 if (soc_is_px30s())
1054 rockchip_clk_register_branches(ctx, px30s_clk_ddrphy_otp,
1055 ARRAY_SIZE(px30s_clk_ddrphy_otp));
1056 else
1057 rockchip_clk_register_branches(ctx, px30_clk_ddrphy_otp,
1058 ARRAY_SIZE(px30_clk_ddrphy_otp));
1059
1060 rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0),
1061 ROCKCHIP_SOFTRST_HIWORD_MASK);
1062
1063 rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL);
1064
1065 rockchip_clk_of_add_provider(np, ctx);
1066 }
1067 CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init);
1068
px30_pmu_clk_init(struct device_node * np)1069 static void __init px30_pmu_clk_init(struct device_node *np)
1070 {
1071 struct rockchip_clk_provider *ctx;
1072 void __iomem *reg_base;
1073
1074 reg_base = of_iomap(np, 0);
1075 if (!reg_base) {
1076 pr_err("%s: could not map cru pmu region\n", __func__);
1077 return;
1078 }
1079
1080 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1081 if (IS_ERR(ctx)) {
1082 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1083 return;
1084 }
1085 pmucru_ctx = ctx;
1086
1087 rockchip_clk_register_plls(ctx, px30_pmu_pll_clks,
1088 ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0);
1089
1090 if (cru_ctx)
1091 px30_register_armclk();
1092
1093 rockchip_clk_register_branches(ctx, px30_clk_pmu_branches,
1094 ARRAY_SIZE(px30_clk_pmu_branches));
1095
1096 rockchip_clk_of_add_provider(np, ctx);
1097 }
1098 CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init);
1099
1100 #ifdef MODULE
1101 struct clk_px30_inits {
1102 void (*inits)(struct device_node *np);
1103 };
1104
1105 static const struct clk_px30_inits clk_px30_init = {
1106 .inits = px30_clk_init,
1107 };
1108
1109 static const struct clk_px30_inits clk_px30_pmu_init = {
1110 .inits = px30_pmu_clk_init,
1111 };
1112
1113 static const struct of_device_id clk_px30_match_table[] = {
1114 {
1115 .compatible = "rockchip,px30-cru",
1116 .data = &clk_px30_init,
1117 }, {
1118 .compatible = "rockchip,px30-pmucru",
1119 .data = &clk_px30_pmu_init,
1120 },
1121 { }
1122 };
1123 MODULE_DEVICE_TABLE(of, clk_px30_match_table);
1124
clk_px30_probe(struct platform_device * pdev)1125 static int clk_px30_probe(struct platform_device *pdev)
1126 {
1127 struct device_node *np = pdev->dev.of_node;
1128 const struct of_device_id *match;
1129 const struct clk_px30_inits *init_data;
1130
1131 match = of_match_device(clk_px30_match_table, &pdev->dev);
1132 if (!match || !match->data)
1133 return -EINVAL;
1134
1135 init_data = match->data;
1136 if (init_data->inits)
1137 init_data->inits(np);
1138
1139 return 0;
1140 }
1141
1142 static struct platform_driver clk_px30_driver = {
1143 .probe = clk_px30_probe,
1144 .driver = {
1145 .name = "clk-px30",
1146 .of_match_table = clk_px30_match_table,
1147 },
1148 };
1149 module_platform_driver(clk_px30_driver);
1150
1151 MODULE_DESCRIPTION("Rockchip PX30 Clock Driver");
1152 MODULE_LICENSE("GPL");
1153 #endif /* MODULE */
1154