1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/dts-v1/; 5*4882a593Smuzhiyun#include "rk1808.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun model = "Rockchip rk1808 fpga board"; 9*4882a593Smuzhiyun compatible = "rockchip,fpga", "rockchip,rk1808"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun chosen { 12*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 root=/dev/mmcblk1p8 rootfstype=ext4 rootwait clk_ignore_unused"; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun memory@200000 { 16*4882a593Smuzhiyun device_type = "memory"; 17*4882a593Smuzhiyun reg = <0x0 0x00200000 0x0 0x0FE00000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun fiq_debugger: fiq-debugger { 21*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 22*4882a593Smuzhiyun rockchip,serial-id = <2>; 23*4882a593Smuzhiyun rockchip,wake-irq = <0>; 24*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 25*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 26*4882a593Smuzhiyun interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 27*4882a593Smuzhiyun status = "okay"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun&emmc { 32*4882a593Smuzhiyun max-frequency = <400000>; 33*4882a593Smuzhiyun clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>; 34*4882a593Smuzhiyun clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 35*4882a593Smuzhiyun mmc-hs200-1_8v; 36*4882a593Smuzhiyun no-sdio; 37*4882a593Smuzhiyun no-sd; 38*4882a593Smuzhiyun num-slots = <1>; 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&npu { 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&sdmmc { 47*4882a593Smuzhiyun max-frequency = <400000>; 48*4882a593Smuzhiyun clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>; 49*4882a593Smuzhiyun clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 50*4882a593Smuzhiyun no-sdio; 51*4882a593Smuzhiyun no-mmc; 52*4882a593Smuzhiyun status = "okay"; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun/* If fiq_debugger set okay, need to define uart2 and to be disabled */ 56*4882a593Smuzhiyun&uart2 { 57*4882a593Smuzhiyun status = "disabled"; 58*4882a593Smuzhiyun}; 59