clk/rockchip/clk-px30.c

141 PNAME(mux_pll_p)		= { "xin24m"};
142 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
151 PNAME(mux_gpll_xin24m_p)		= { "gpll", "xin24m"};
152 PNAME(mux_xin24m_gpll_p)		= { "xin24m", "gpll"};
154 PNAME(mux_gpll_cpll_npll_xin24m_p)	= { "gpll", "dummy_cpll", "dummy_npll", "xin24m" };
155 PNAME(mux_gpll_xin24m_npll_p)		= { "gpll", "xin24m", "dummy_npll"};
167 PNAME(mux_uart_src_p)		= { "gpll", "xin24m", "usb480m", "dummy_npll" };
173 PNAME(mux_cif_out_p)		= { "xin24m", "dummy_cpll", "dummy_npll", "usb480m" };
174 PNAME(mux_dclk_vopb_p)		= { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
175 PNAME(mux_dclk_vopl_p)		= { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
183 PNAME(mux_wifi_pmu_p)		= { "xin24m", "clk_wifi_pmu_src" };
185 PNAME(mux_usbphy_ref_p)		= { "xin24m", "clk_ref24m_pmu" };
186 PNAME(mux_mipidsiphy_ref_p)	= { "xin24m", "clk_ref24m_pmu" };
276 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
306 	GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
350 	GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED,
741 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
743 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
745 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
747 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
749 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
751 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
754 	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
757 	COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
761 	GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
915 	COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
920 	COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
944 	GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
985 	COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,