1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
4 * Author: Elaine <zhangqing@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/io.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/rockchip/cpu.h>
14 #include <linux/syscore_ops.h>
15 #include <dt-bindings/clock/rk3128-cru.h>
16 #include "clk.h"
17
18 #define RK3128_GRF_SOC_STATUS0 0x14c
19
20 enum rk3128_plls {
21 apll, dpll, cpll, gpll,
22 };
23
24 static struct rockchip_pll_rate_table rk3128_pll_rates[] = {
25 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
26 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
27 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
28 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
29 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
30 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
31 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
32 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
47 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
48 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
49 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
50 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
51 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
52 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
53 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
54 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
55 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
56 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
57 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
58 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
59 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
60 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
61 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
62 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
63 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
64 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
65 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
66 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
67 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
68 { /* sentinel */ },
69 };
70
71 #define RK3128_DIV_CPU_MASK 0x1f
72 #define RK3128_DIV_CPU_SHIFT 8
73
74 #define RK3128_DIV_PERI_MASK 0xf
75 #define RK3128_DIV_PERI_SHIFT 0
76 #define RK3128_DIV_ACLK_MASK 0x7
77 #define RK3128_DIV_ACLK_SHIFT 4
78 #define RK3128_DIV_HCLK_MASK 0x3
79 #define RK3128_DIV_HCLK_SHIFT 8
80 #define RK3128_DIV_PCLK_MASK 0x7
81 #define RK3128_DIV_PCLK_SHIFT 12
82
83 #define RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div) \
84 { \
85 .reg = RK2928_CLKSEL_CON(1), \
86 .val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \
87 RK3128_DIV_PERI_SHIFT) | \
88 HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, \
89 RK3128_DIV_ACLK_SHIFT), \
90 }
91
92 #define RK3128_CPUCLK_RATE(_prate, _core_aclk_div, _pclk_dbg_div) \
93 { \
94 .prate = _prate, \
95 .divs = { \
96 RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div), \
97 }, \
98 }
99
100 static struct rockchip_cpuclk_rate_table rk3128_cpuclk_rates[] __initdata = {
101 RK3128_CPUCLK_RATE(1800000000, 1, 7),
102 RK3128_CPUCLK_RATE(1704000000, 1, 7),
103 RK3128_CPUCLK_RATE(1608000000, 1, 7),
104 RK3128_CPUCLK_RATE(1512000000, 1, 7),
105 RK3128_CPUCLK_RATE(1488000000, 1, 5),
106 RK3128_CPUCLK_RATE(1416000000, 1, 5),
107 RK3128_CPUCLK_RATE(1392000000, 1, 5),
108 RK3128_CPUCLK_RATE(1296000000, 1, 5),
109 RK3128_CPUCLK_RATE(1200000000, 1, 5),
110 RK3128_CPUCLK_RATE(1104000000, 1, 5),
111 RK3128_CPUCLK_RATE(1008000000, 1, 5),
112 RK3128_CPUCLK_RATE(912000000, 1, 5),
113 RK3128_CPUCLK_RATE(816000000, 1, 3),
114 RK3128_CPUCLK_RATE(696000000, 1, 3),
115 RK3128_CPUCLK_RATE(600000000, 1, 3),
116 RK3128_CPUCLK_RATE(408000000, 1, 1),
117 RK3128_CPUCLK_RATE(312000000, 1, 1),
118 RK3128_CPUCLK_RATE(216000000, 1, 1),
119 RK3128_CPUCLK_RATE(96000000, 1, 1),
120 };
121
122 static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = {
123 .core_reg[0] = RK2928_CLKSEL_CON(0),
124 .div_core_shift[0] = 0,
125 .div_core_mask[0] = 0x1f,
126 .num_cores = 1,
127 .mux_core_alt = 1,
128 .mux_core_main = 0,
129 .mux_core_shift = 7,
130 .mux_core_mask = 0x1,
131 };
132
133 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
134
135 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_div2_ddr" };
136 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
137 PNAME(mux_aclk_cpu_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
138
139 PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" };
140 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" };
141 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" };
142
143 PNAME(mux_aclk_peri_src_p) = { "gpll", "cpll", "gpll_div2", "gpll_div3" };
144 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
145 PNAME(mux_clk_cif_out_src_p) = { "sclk_cif_src", "xin24m" };
146 PNAME(mux_sclk_vop_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
147
148 PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
149 PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
150 PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" };
151 PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" };
152
153 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
154 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
155 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
156
157 PNAME(mux_sclk_gmac_p) = { "sclk_gmac_src", "gmac_clkin" };
158 PNAME(mux_sclk_sfc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
159
160 static struct rockchip_pll_clock rk3128_pll_clks[] __initdata = {
161 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
162 RK2928_MODE_CON, 0, 1, 0, rk3128_pll_rates),
163 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
164 RK2928_MODE_CON, 4, 0, 0, NULL),
165 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
166 RK2928_MODE_CON, 8, 2, 0, rk3128_pll_rates),
167 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
168 RK2928_MODE_CON, 12, 3, ROCKCHIP_PLL_SYNC_RATE, rk3128_pll_rates),
169 };
170
171 #define MFLAGS CLK_MUX_HIWORD_MASK
172 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
173 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
174
175 static struct rockchip_clk_branch rk3128_i2s0_fracmux __initdata =
176 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
177 RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
178
179 static struct rockchip_clk_branch rk3128_i2s1_fracmux __initdata =
180 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
181 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
182
183 static struct rockchip_clk_branch rk3128_spdif_fracmux __initdata =
184 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
185 RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
186
187 static struct rockchip_clk_branch rk3128_uart0_fracmux __initdata =
188 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
189 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
190
191 static struct rockchip_clk_branch rk3128_uart1_fracmux __initdata =
192 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
193 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
194
195 static struct rockchip_clk_branch rk3128_uart2_fracmux __initdata =
196 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
197 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
198
199 static struct rockchip_clk_branch common_clk_branches[] __initdata = {
200 /*
201 * Clock-Architecture Diagram 1
202 */
203
204 FACTOR(PLL_GPLL_DIV2, "gpll_div2", "gpll", 0, 1, 2),
205 FACTOR(PLL_GPLL_DIV3, "gpll_div3", "gpll", 0, 1, 3),
206
207 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
208 RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
209
210 /* PD_DDR */
211 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
212 RK2928_CLKGATE_CON(0), 2, GFLAGS),
213 GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED,
214 RK2928_CLKGATE_CON(0), 2, GFLAGS),
215 COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrphy_p, 0,
216 RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
217 ROCKCHIP_DDRCLK_SIP_V2),
218 FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2),
219
220 /* PD_CORE */
221 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
222 RK2928_CLKGATE_CON(0), 6, GFLAGS),
223 GATE(0, "gpll_div2_core", "gpll_div2", CLK_IGNORE_UNUSED,
224 RK2928_CLKGATE_CON(0), 6, GFLAGS),
225 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
226 RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
227 RK2928_CLKGATE_CON(0), 0, GFLAGS),
228 COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
229 RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
230 RK2928_CLKGATE_CON(0), 7, GFLAGS),
231
232 /* PD_MISC */
233 MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
234 RK2928_MISC_CON, 15, 1, MFLAGS),
235
236 /* PD_CPU */
237 COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IS_CRITICAL,
238 RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
239 RK2928_CLKGATE_CON(0), 1, GFLAGS),
240 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
241 RK2928_CLKGATE_CON(0), 3, GFLAGS),
242 COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
243 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
244 RK2928_CLKGATE_CON(0), 4, GFLAGS),
245 COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
246 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS,
247 RK2928_CLKGATE_CON(0), 5, GFLAGS),
248 COMPOSITE_NOMUX(SCLK_CRYPTO, "clk_crypto", "aclk_cpu_src", 0,
249 RK2928_CLKSEL_CON(24), 0, 2, DFLAGS,
250 RK2928_CLKGATE_CON(0), 12, GFLAGS),
251
252 /* PD_VIDEO */
253 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_5plls_p, 0,
254 RK2928_CLKSEL_CON(32), 5, 3, MFLAGS, 0, 5, DFLAGS,
255 RK2928_CLKGATE_CON(3), 9, GFLAGS),
256 FACTOR(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0, 1, 4),
257
258 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_5plls_p, 0,
259 RK2928_CLKSEL_CON(32), 13, 3, MFLAGS, 8, 5, DFLAGS,
260 RK2928_CLKGATE_CON(3), 11, GFLAGS),
261 FACTOR_GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0, 1, 4,
262 RK2928_CLKGATE_CON(3), 12, GFLAGS),
263
264 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_5plls_p, 0,
265 RK2928_CLKSEL_CON(34), 13, 3, MFLAGS, 8, 5, DFLAGS,
266 RK2928_CLKGATE_CON(3), 10, GFLAGS),
267
268 /* PD_VIO */
269 COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_5plls_p, CLK_IS_CRITICAL,
270 RK2928_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS,
271 RK2928_CLKGATE_CON(3), 0, GFLAGS),
272 COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0,
273 RK2928_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS,
274 RK2928_CLKGATE_CON(1), 4, GFLAGS),
275 FACTOR_GATE(HCLK_VIO, "hclk_vio", "aclk_vio0", CLK_IS_CRITICAL, 1, 4,
276 RK2928_CLKGATE_CON(0), 11, GFLAGS),
277
278 /* PD_PERI */
279 COMPOSITE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
280 RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
281 RK2928_CLKGATE_CON(2), 0, GFLAGS),
282
283 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
284 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
285 RK2928_CLKGATE_CON(2), 3, GFLAGS),
286 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
287 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
288 RK2928_CLKGATE_CON(2), 2, GFLAGS),
289 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
290 RK2928_CLKGATE_CON(2), 1, GFLAGS),
291
292 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
293 RK2928_CLKGATE_CON(10), 3, GFLAGS),
294 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
295 RK2928_CLKGATE_CON(10), 4, GFLAGS),
296 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
297 RK2928_CLKGATE_CON(10), 5, GFLAGS),
298 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
299 RK2928_CLKGATE_CON(10), 6, GFLAGS),
300 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
301 RK2928_CLKGATE_CON(10), 7, GFLAGS),
302 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", CLK_IS_CRITICAL,
303 RK2928_CLKGATE_CON(10), 8, GFLAGS),
304
305 GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
306 RK2928_CLKGATE_CON(10), 0, GFLAGS),
307 GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0,
308 RK2928_CLKGATE_CON(10), 1, GFLAGS),
309 GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,
310 RK2928_CLKGATE_CON(10), 2, GFLAGS),
311 GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", 0,
312 RK2928_CLKGATE_CON(2), 15, GFLAGS),
313
314 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
315 RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
316 RK2928_CLKGATE_CON(2), 11, GFLAGS),
317
318 COMPOSITE(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
319 RK2928_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
320 RK2928_CLKGATE_CON(2), 13, GFLAGS),
321
322 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
323 RK2928_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
324 RK2928_CLKGATE_CON(2), 14, GFLAGS),
325
326 DIV(SCLK_PVTM, "clk_pvtm", "clk_pvtm_func", 0,
327 RK2928_CLKSEL_CON(2), 0, 7, DFLAGS),
328
329 /*
330 * Clock-Architecture Diagram 2
331 */
332 COMPOSITE(DCLK_VOP, "dclk_vop", mux_sclk_vop_src_p, 0,
333 RK2928_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
334 RK2928_CLKGATE_CON(3), 1, GFLAGS),
335 COMPOSITE(SCLK_VOP, "sclk_vop", mux_sclk_vop_src_p, 0,
336 RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
337 RK2928_CLKGATE_CON(3), 2, GFLAGS),
338 COMPOSITE(DCLK_EBC, "dclk_ebc", mux_pll_src_3plls_p, 0,
339 RK2928_CLKSEL_CON(23), 0, 2, MFLAGS, 8, 8, DFLAGS,
340 RK2928_CLKGATE_CON(3), 4, GFLAGS),
341
342 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
343
344 COMPOSITE_NODIV(SCLK_CIF_SRC, "sclk_cif_src", mux_pll_src_4plls_p, 0,
345 RK2928_CLKSEL_CON(29), 0, 2, MFLAGS,
346 RK2928_CLKGATE_CON(3), 7, GFLAGS),
347 MUX(SCLK_CIF_OUT_SRC, "sclk_cif_out_src", mux_clk_cif_out_src_p, 0,
348 RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
349 DIV(SCLK_CIF_OUT, "sclk_cif_out", "sclk_cif_out_src", 0,
350 RK2928_CLKSEL_CON(29), 2, 5, DFLAGS),
351
352 COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0,
353 RK2928_CLKSEL_CON(9), 14, 2, MFLAGS, 0, 7, DFLAGS,
354 RK2928_CLKGATE_CON(4), 4, GFLAGS),
355 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
356 RK2928_CLKSEL_CON(8), 0,
357 RK2928_CLKGATE_CON(4), 5, GFLAGS,
358 &rk3128_i2s0_fracmux),
359 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
360 RK2928_CLKGATE_CON(4), 6, GFLAGS),
361
362 COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0,
363 RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
364 RK2928_CLKGATE_CON(0), 9, GFLAGS),
365 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
366 RK2928_CLKSEL_CON(7), 0,
367 RK2928_CLKGATE_CON(0), 10, GFLAGS,
368 &rk3128_i2s1_fracmux),
369 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
370 RK2928_CLKGATE_CON(0), 14, GFLAGS),
371 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
372 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
373 RK2928_CLKGATE_CON(0), 13, GFLAGS),
374
375 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0,
376 RK2928_CLKSEL_CON(6), 14, 2, MFLAGS, 0, 7, DFLAGS,
377 RK2928_CLKGATE_CON(2), 10, GFLAGS),
378 COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
379 RK2928_CLKSEL_CON(20), 0,
380 RK2928_CLKGATE_CON(2), 12, GFLAGS,
381 &rk3128_spdif_fracmux),
382
383 GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
384 RK2928_CLKGATE_CON(1), 3, GFLAGS),
385
386 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", 0,
387 RK2928_CLKGATE_CON(1), 5, GFLAGS),
388 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin12m", 0,
389 RK2928_CLKGATE_CON(1), 6, GFLAGS),
390
391 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
392 RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
393 RK2928_CLKGATE_CON(2), 8, GFLAGS),
394
395 COMPOSITE(ACLK_GPU, "aclk_gpu", mux_pll_src_5plls_p, 0,
396 RK2928_CLKSEL_CON(34), 5, 3, MFLAGS, 0, 5, DFLAGS,
397 RK2928_CLKGATE_CON(3), 13, GFLAGS),
398
399 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
400 RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
401 RK2928_CLKGATE_CON(2), 9, GFLAGS),
402
403 /* PD_UART */
404 COMPOSITE(0, "uart0_src", mux_pll_src_4plls_p, 0,
405 RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
406 RK2928_CLKGATE_CON(1), 8, GFLAGS),
407 MUX(0, "uart12_src", mux_pll_src_4plls_p, 0,
408 RK2928_CLKSEL_CON(13), 14, 2, MFLAGS),
409 COMPOSITE_NOMUX(0, "uart1_src", "uart12_src", 0,
410 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
411 RK2928_CLKGATE_CON(1), 10, GFLAGS),
412 COMPOSITE_NOMUX(0, "uart2_src", "uart12_src", 0,
413 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
414 RK2928_CLKGATE_CON(1), 13, GFLAGS),
415 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
416 RK2928_CLKSEL_CON(17), 0,
417 RK2928_CLKGATE_CON(1), 9, GFLAGS,
418 &rk3128_uart0_fracmux),
419 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
420 RK2928_CLKSEL_CON(18), 0,
421 RK2928_CLKGATE_CON(1), 11, GFLAGS,
422 &rk3128_uart1_fracmux),
423 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
424 RK2928_CLKSEL_CON(19), 0,
425 RK2928_CLKGATE_CON(1), 13, GFLAGS,
426 &rk3128_uart2_fracmux),
427
428 COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
429 RK2928_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
430 RK2928_CLKGATE_CON(1), 7, GFLAGS),
431 MUX(SCLK_MAC, "sclk_gmac", mux_sclk_gmac_p, 0,
432 RK2928_CLKSEL_CON(5), 15, 1, MFLAGS),
433 GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac", 0,
434 RK2928_CLKGATE_CON(2), 5, GFLAGS),
435 GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac", 0,
436 RK2928_CLKGATE_CON(2), 4, GFLAGS),
437 GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac", 0,
438 RK2928_CLKGATE_CON(2), 6, GFLAGS),
439 GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac", 0,
440 RK2928_CLKGATE_CON(2), 7, GFLAGS),
441
442 COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_3plls_p, 0,
443 RK2928_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
444 RK2928_CLKGATE_CON(1), 14, GFLAGS),
445 GATE(SCLK_HSADC_TSP, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
446 RK2928_CLKGATE_CON(10), 13, GFLAGS),
447
448 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
449 RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS,
450 RK2928_CLKGATE_CON(10), 15, GFLAGS),
451
452 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", CLK_IS_CRITICAL,
453 RK2928_CLKSEL_CON(29), 8, 6, DFLAGS,
454 RK2928_CLKGATE_CON(1), 0, GFLAGS),
455
456 /*
457 * Clock-Architecture Diagram 3
458 */
459
460 /* PD_VOP */
461 GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
462 GATE(ACLK_CIF, "aclk_cif", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
463 GATE(ACLK_RGA, "aclk_rga", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
464 GATE(0, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
465
466 GATE(ACLK_IEP, "aclk_iep", "aclk_vio1", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
467 GATE(0, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 10, GFLAGS),
468
469 GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(9), 5, GFLAGS),
470 GATE(PCLK_MIPI, "pclk_mipi", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
471 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
472 GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
473 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
474 GATE(0, "hclk_vio_niu", "hclk_vio", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(6), 12, GFLAGS),
475 GATE(HCLK_CIF, "hclk_cif", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
476 GATE(HCLK_EBC, "hclk_ebc", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
477
478 /* PD_PERI */
479 GATE(0, "aclk_peri_axi", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
480 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(10), 10, GFLAGS),
481 GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
482 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
483 GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
484
485 GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
486 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
487 GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
488 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
489 GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
490 GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),
491 GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
492 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
493 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS),
494 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
495 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
496 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
497 GATE(0, "hclk_emmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 6, GFLAGS),
498 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
499 GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 14, GFLAGS),
500 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
501
502 GATE(PCLK_SIM_CARD, "pclk_sim_card", "pclk_peri", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
503 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
504 GATE(0, "pclk_peri_axi", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
505 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
506 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
507 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
508 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
509 GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
510 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
511 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
512 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
513 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
514 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
515 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
516 GATE(PCLK_EFUSE, "pclk_efuse", "pclk_peri", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
517 GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 7, GFLAGS),
518 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
519 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
520 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
521 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
522
523 /* PD_BUS */
524 GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
525 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
526
527 GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
528 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
529
530 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
531 GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS),
532 GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
533 GATE(PCLK_MIPIPHY, "pclk_mipiphy", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
534
535 GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(9), 2, GFLAGS),
536 GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(9), 3, GFLAGS),
537
538 /* PD_MMC */
539 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
540 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
541
542 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
543 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0),
544
545 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
546 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
547 };
548
549 static struct rockchip_clk_branch rk3126_clk_branches[] __initdata = {
550 GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
551 GATE(0, "pclk_s_efuse", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
552 GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 8, GFLAGS),
553 };
554
555 static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
556 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
557 RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
558 RK2928_CLKGATE_CON(3), 15, GFLAGS),
559
560 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
561 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
562 };
563
564 static void __iomem *rk312x_reg_base;
565
rkclk_cpuclk_div_setting(int div)566 void rkclk_cpuclk_div_setting(int div)
567 {
568 if (cpu_is_rk312x())
569 writel_relaxed((0x001f0000 | (div - 1)),
570 rk312x_reg_base + RK2928_CLKSEL_CON(0));
571 }
572
rk3128_dump_cru(void)573 static void rk3128_dump_cru(void)
574 {
575 if (rk312x_reg_base) {
576 pr_warn("CRU:\n");
577 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
578 32, 4, rk312x_reg_base,
579 0x1f8, false);
580 }
581 }
582
rk3128_common_clk_init(struct device_node * np)583 static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
584 {
585 struct rockchip_clk_provider *ctx;
586 void __iomem *reg_base;
587 struct clk **clks;
588
589 reg_base = of_iomap(np, 0);
590 if (!reg_base) {
591 pr_err("%s: could not map cru region\n", __func__);
592 return ERR_PTR(-ENOMEM);
593 }
594
595 rk312x_reg_base = reg_base;
596 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
597 if (IS_ERR(ctx)) {
598 pr_err("%s: rockchip clk init failed\n", __func__);
599 iounmap(reg_base);
600 return ERR_PTR(-ENOMEM);
601 }
602 clks = ctx->clk_data.clks;
603
604 rockchip_clk_register_plls(ctx, rk3128_pll_clks,
605 ARRAY_SIZE(rk3128_pll_clks),
606 RK3128_GRF_SOC_STATUS0);
607 rockchip_clk_register_branches(ctx, common_clk_branches,
608 ARRAY_SIZE(common_clk_branches));
609
610 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
611 2, clks[PLL_APLL], clks[PLL_GPLL_DIV2],
612 &rk3128_cpuclk_data, rk3128_cpuclk_rates,
613 ARRAY_SIZE(rk3128_cpuclk_rates));
614
615 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
616 ROCKCHIP_SOFTRST_HIWORD_MASK);
617
618 rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
619
620 if (!rk_dump_cru)
621 rk_dump_cru = rk3128_dump_cru;
622
623 return ctx;
624 }
625
rk3126_clk_init(struct device_node * np)626 static void __init rk3126_clk_init(struct device_node *np)
627 {
628 struct rockchip_clk_provider *ctx;
629
630 ctx = rk3128_common_clk_init(np);
631 if (IS_ERR(ctx))
632 return;
633
634 rockchip_clk_register_branches(ctx, rk3126_clk_branches,
635 ARRAY_SIZE(rk3126_clk_branches));
636
637 rockchip_clk_of_add_provider(np, ctx);
638 }
639
640 CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
641
rk3128_clk_init(struct device_node * np)642 static void __init rk3128_clk_init(struct device_node *np)
643 {
644 struct rockchip_clk_provider *ctx;
645
646 ctx = rk3128_common_clk_init(np);
647 if (IS_ERR(ctx))
648 return;
649
650 rockchip_clk_register_branches(ctx, rk3128_clk_branches,
651 ARRAY_SIZE(rk3128_clk_branches));
652
653 rockchip_clk_of_add_provider(np, ctx);
654 }
655
656 CLK_OF_DECLARE(rk3128_cru, "rockchip,rk3128-cru", rk3128_clk_init);
657
658 struct clk_rk3128_inits {
659 void (*inits)(struct device_node *np);
660 };
661
662 static const struct clk_rk3128_inits clk_rk3126_init = {
663 .inits = rk3126_clk_init,
664 };
665
666 static const struct clk_rk3128_inits clk_rk3128_init = {
667 .inits = rk3128_clk_init,
668 };
669
670 static const struct of_device_id clk_rk3128_match_table[] = {
671 {
672 .compatible = "rockchip,rk3126-cru",
673 .data = &clk_rk3126_init,
674 }, {
675 .compatible = "rockchip,rk3128-cru",
676 .data = &clk_rk3128_init,
677 },
678 { }
679 };
680 MODULE_DEVICE_TABLE(of, clk_rk3128_match_table);
681
clk_rk3128_probe(struct platform_device * pdev)682 static int __init clk_rk3128_probe(struct platform_device *pdev)
683 {
684 struct device_node *np = pdev->dev.of_node;
685 const struct of_device_id *match;
686 const struct clk_rk3128_inits *init_data;
687
688 match = of_match_device(clk_rk3128_match_table, &pdev->dev);
689 if (!match || !match->data)
690 return -EINVAL;
691
692 init_data = match->data;
693 if (init_data->inits)
694 init_data->inits(np);
695
696 return 0;
697 }
698
699 static struct platform_driver clk_rk3128_driver = {
700 .driver = {
701 .name = "clk-rk3128",
702 .of_match_table = clk_rk3128_match_table,
703 },
704 };
705 builtin_platform_driver_probe(clk_rk3128_driver, clk_rk3128_probe);
706
707 MODULE_DESCRIPTION("Rockchip RK3128 Clock Driver");
708 MODULE_LICENSE("GPL");
709