1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
4 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/io.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <dt-bindings/clock/rk3399-cru.h>
16 #include "clk.h"
17
18 enum rk3399_plls {
19 lpll, bpll, dpll, cpll, gpll, npll, vpll,
20 };
21
22 enum rk3399_pmu_plls {
23 ppll,
24 };
25
26 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
27 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
28 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
29 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
30 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
31 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
32 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
33 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
34 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
35 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
36 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
64 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
65 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
66 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
67 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
70 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
71 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
72 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
73 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
74 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
75 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
76 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
77 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
78 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
79 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
80 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
81 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
82 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
83 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
84 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
85 RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0),
86 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
87 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
88 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
89 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
90 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
91 RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
92 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
93 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
94 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
95 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
96 RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
97 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
98 RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
99 RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
100 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
101 RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
102 RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
103 RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
104 RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
105 { /* sentinel */ },
106 };
107
108 static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
109 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
110 RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912), /* vco = 2970000000 */
111 RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804), /* vco = 2967032965 */
112 RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912), /* vco = 2970000000 */
113 RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807), /* vco = 2967032970 */
114 RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640), /* vco = 3118500000 */
115 RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco = 2967032960 */
116 RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0, 4194304), /* vco = 2982000000 */
117 RK3036_PLL_RATE( 74250000, 1, 129, 7, 6, 0, 15728640), /* vco = 3118500000 */
118 RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco = 3115384608 */
119 RK3036_PLL_RATE( 65000000, 1, 113, 7, 6, 0, 12582912), /* vco = 2730000000 */
120 RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco = 2907692291 */
121 RK3036_PLL_RATE( 54000000, 1, 110, 7, 7, 0, 4194304), /* vco = 2646000000 */
122 RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 */
123 RK3036_PLL_RATE( 26973027, 1, 55, 7, 7, 0, 1173232), /* vco = 1321678323 */
124 { /* sentinel */ },
125 };
126
127 /* CRU parents */
128 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
129
130 PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
131 "clk_ddrc_bpll_src",
132 "clk_ddrc_dpll_src",
133 "clk_ddrc_gpll_src" };
134
135 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
136 PNAME(mux_pll_src_dmyvpll_cpll_gpll_p) = { "dummy_vpll", "cpll", "gpll" };
137
138 #ifdef RK3399_TWO_PLL_FOR_VOP
139 PNAME(mux_aclk_cci_p) = { "dummy_cpll",
140 "gpll_aclk_cci_src",
141 "npll_aclk_cci_src",
142 "dummy_vpll" };
143 PNAME(mux_cci_trace_p) = { "dummy_cpll",
144 "gpll_cci_trace" };
145 PNAME(mux_cs_p) = { "dummy_cpll", "gpll_cs",
146 "npll_cs"};
147 PNAME(mux_aclk_perihp_p) = { "dummy_cpll",
148 "gpll_aclk_perihp_src" };
149
150 PNAME(mux_pll_src_cpll_gpll_p) = { "dummy_cpll", "gpll" };
151 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "dummy_cpll", "gpll", "npll" };
152 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "dummy_cpll", "gpll", "ppll" };
153 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "dummy_cpll", "gpll", "upll" };
154 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "dummy_cpll", "gpll" };
155 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "dummy_cpll", "gpll", "npll",
156 "ppll" };
157 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "dummy_cpll", "gpll", "npll",
158 "xin24m" };
159 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "dummy_cpll", "gpll", "npll",
160 "clk_usbphy_480m" };
161 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "dummy_cpll", "gpll",
162 "npll", "upll" };
163 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "dummy_cpll", "gpll", "npll",
164 "upll", "xin24m" };
165 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "dummy_cpll", "gpll", "npll",
166 "ppll", "upll", "xin24m" };
167 /*
168 * We hope to be able to HDMI/DP can obtain better signal quality,
169 * therefore, we move VOP pwm and aclk clocks to other PLLs, let
170 * HDMI/DP phyclock can monopolize VPLL.
171 */
172 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "dummy_cpll", "gpll",
173 "npll" };
174 PNAME(mux_pll_src_dmyvpll_cpll_gpll_gpll_p) = { "dummy_vpll", "dummy_cpll", "gpll",
175 "gpll" };
176 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
177 "dummy_cpll", "gpll" };
178
179 PNAME(mux_aclk_emmc_p) = { "dummy_cpll",
180 "gpll_aclk_emmc_src" };
181
182 PNAME(mux_aclk_perilp0_p) = { "dummy_cpll",
183 "gpll_aclk_perilp0_src" };
184
185 PNAME(mux_fclk_cm0s_p) = { "dummy_cpll",
186 "gpll_fclk_cm0s_src" };
187
188 PNAME(mux_hclk_perilp1_p) = { "dummy_cpll",
189 "gpll_hclk_perilp1_src" };
190 PNAME(mux_aclk_gmac_p) = { "dummy_cpll",
191 "gpll_aclk_gmac_src" };
192 #else
193 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
194 "gpll_aclk_cci_src",
195 "npll_aclk_cci_src",
196 "dummy_vpll" };
197 PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
198 "gpll_cci_trace" };
199 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
200 "npll_cs"};
201 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
202 "gpll_aclk_perihp_src" };
203
204 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
205 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
206 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
207 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
208 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
209 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
210 "ppll" };
211 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
212 "xin24m" };
213 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
214 "clk_usbphy_480m" };
215 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
216 "npll", "upll" };
217 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
218 "upll", "xin24m" };
219 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
220 "ppll", "upll", "xin24m" };
221 /*
222 * We hope to be able to HDMI/DP can obtain better signal quality,
223 * therefore, we move VOP pwm and aclk clocks to other PLLs, let
224 * HDMI/DP phyclock can monopolize VPLL.
225 */
226 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "cpll", "gpll",
227 "npll" };
228 PNAME(mux_pll_src_dmyvpll_cpll_gpll_gpll_p) = { "dummy_vpll", "cpll", "gpll",
229 "gpll" };
230 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
231 "cpll", "gpll" };
232
233 PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
234 "gpll_aclk_emmc_src" };
235
236 PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
237 "gpll_aclk_perilp0_src" };
238
239 PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
240 "gpll_fclk_cm0s_src" };
241
242 PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
243 "gpll_hclk_perilp1_src" };
244 PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
245 "gpll_aclk_gmac_src" };
246 #endif
247
248 PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
249 "dummy_dclk_vop0_frac" };
250 PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
251 "dummy_dclk_vop1_frac" };
252
253 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
254
255 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
256 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
257 PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
258 "clk_pcie_core_phy" };
259 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
260 PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
261
262 PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
263 "clk_usbphy1_480m_src" };
264 PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
265 PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
266 "clkin_i2s", "xin12m" };
267 PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
268 "clkin_i2s", "xin12m" };
269 PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
270 "clkin_i2s", "xin12m" };
271 PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
272 "clkin_i2s", "xin12m" };
273 PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1",
274 "clk_i2s2" };
275 PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
276
277 PNAME(mux_uart0_p) = { "xin24m", "clk_uart0_div", "clk_uart0_frac" };
278 PNAME(mux_uart1_p) = { "xin24m", "clk_uart1_div", "clk_uart1_frac" };
279 PNAME(mux_uart2_p) = { "xin24m", "clk_uart2_div", "clk_uart2_frac" };
280 PNAME(mux_uart3_p) = { "xin24m", "clk_uart3_div", "clk_uart3_frac" };
281
282 /* PMU CRU parents */
283 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
284 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
285 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
286 PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
287 PNAME(mux_uart4_pmu_p) = { "xin24m", "clk_uart4_div",
288 "clk_uart4_frac" };
289 PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
290
291 static u32 uart_mux_idx[] = { 2, 0, 1 };
292
293 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
294 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
295 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
296 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
297 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
298 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
299 RK3399_PLL_CON(19), 8, 31, 0, NULL),
300 #ifdef RK3399_TWO_PLL_FOR_VOP
301 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
302 RK3399_PLL_CON(27), 8, 31, 0, rk3399_pll_rates),
303 #else
304 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
305 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
306 #endif
307 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
308 RK3399_PLL_CON(35), 8, 31, 0, rk3399_pll_rates),
309 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
310 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
311 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
312 RK3399_PLL_CON(51), 8, 31, 0, rk3399_vpll_rates),
313 };
314
315 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
316 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, CLK_IS_CRITICAL, RK3399_PMU_PLL_CON(0),
317 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
318 };
319
320 #define MFLAGS CLK_MUX_HIWORD_MASK
321 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
322 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
323 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
324
325 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
326 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
327 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
328
329 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
330 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
331 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
332
333 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
334 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
335 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
336
337 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
338 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
339 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
340
341 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
342 MUXTBL(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
343 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS, uart_mux_idx);
344
345 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
346 MUXTBL(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
347 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS, uart_mux_idx);
348
349 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
350 MUXTBL(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
351 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS, uart_mux_idx);
352
353 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
354 MUXTBL(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
355 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS, uart_mux_idx);
356
357 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
358 MUXTBL(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
359 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS, uart_mux_idx);
360
361 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
362 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
363 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
364
365 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
366 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
367 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
368
369 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
370 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
371 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
372
373 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
374 .core_reg[0] = RK3399_CLKSEL_CON(0),
375 .div_core_shift[0] = 0,
376 .div_core_mask[0] = 0x1f,
377 .num_cores = 1,
378 .mux_core_alt = 3,
379 .mux_core_main = 0,
380 .mux_core_shift = 6,
381 .mux_core_mask = 0x3,
382 };
383
384 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
385 .core_reg[0] = RK3399_CLKSEL_CON(2),
386 .div_core_shift[0] = 0,
387 .div_core_mask[0] = 0x1f,
388 .num_cores = 1,
389 .mux_core_alt = 3,
390 .mux_core_main = 1,
391 .mux_core_shift = 6,
392 .mux_core_mask = 0x3,
393 };
394
395 #define RK3399_DIV_ACLKM_MASK 0x1f
396 #define RK3399_DIV_ACLKM_SHIFT 8
397 #define RK3399_DIV_ATCLK_MASK 0x1f
398 #define RK3399_DIV_ATCLK_SHIFT 0
399 #define RK3399_DIV_PCLK_DBG_MASK 0x1f
400 #define RK3399_DIV_PCLK_DBG_SHIFT 8
401
402 #define RK3399_CLKSEL0(_offs, _aclkm) \
403 { \
404 .reg = RK3399_CLKSEL_CON(0 + _offs), \
405 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
406 RK3399_DIV_ACLKM_SHIFT), \
407 }
408 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
409 { \
410 .reg = RK3399_CLKSEL_CON(1 + _offs), \
411 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
412 RK3399_DIV_ATCLK_SHIFT) | \
413 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
414 RK3399_DIV_PCLK_DBG_SHIFT), \
415 }
416
417 /* cluster_l: aclkm in clksel0, rest in clksel1 */
418 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
419 { \
420 .prate = _prate##U, \
421 .divs = { \
422 RK3399_CLKSEL0(0, _aclkm), \
423 RK3399_CLKSEL1(0, _atclk, _pdbg), \
424 }, \
425 }
426
427 /* cluster_b: aclkm in clksel2, rest in clksel3 */
428 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
429 { \
430 .prate = _prate##U, \
431 .divs = { \
432 RK3399_CLKSEL0(2, _aclkm), \
433 RK3399_CLKSEL1(2, _atclk, _pdbg), \
434 }, \
435 }
436
437 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
438 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
439 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
440 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
441 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
442 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
443 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
444 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
445 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
446 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
447 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
448 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
449 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
450 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
451 RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
452 RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1),
453 };
454
455 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
456 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
457 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
458 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
459 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
460 RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9),
461 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
462 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
463 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
464 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
465 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
466 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
467 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
468 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
469 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
470 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
471 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
472 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
473 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
474 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
475 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
476 RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
477 RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1),
478 };
479
480 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
481 /*
482 * CRU Clock-Architecture
483 */
484
485 /* usbphy */
486 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
487 RK3399_CLKGATE_CON(6), 5, GFLAGS),
488 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
489 RK3399_CLKGATE_CON(6), 6, GFLAGS),
490
491 GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
492 RK3399_CLKGATE_CON(13), 12, GFLAGS),
493 GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
494 RK3399_CLKGATE_CON(13), 12, GFLAGS),
495 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
496 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
497
498 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
499 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
500
501 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
502 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
503 RK3399_CLKGATE_CON(6), 4, GFLAGS),
504
505 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
506 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
507 RK3399_CLKGATE_CON(12), 0, GFLAGS),
508 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IS_CRITICAL,
509 RK3399_CLKGATE_CON(30), 0, GFLAGS),
510 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
511 RK3399_CLKGATE_CON(30), 1, GFLAGS),
512 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
513 RK3399_CLKGATE_CON(30), 2, GFLAGS),
514 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
515 RK3399_CLKGATE_CON(30), 3, GFLAGS),
516 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
517 RK3399_CLKGATE_CON(30), 4, GFLAGS),
518
519 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
520 RK3399_CLKGATE_CON(12), 1, GFLAGS),
521 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
522 RK3399_CLKGATE_CON(12), 2, GFLAGS),
523
524 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
525 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
526 RK3399_CLKGATE_CON(12), 3, GFLAGS),
527
528 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
529 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
530 RK3399_CLKGATE_CON(12), 4, GFLAGS),
531
532 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
533 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
534 RK3399_CLKGATE_CON(13), 4, GFLAGS),
535
536 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
537 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
538 RK3399_CLKGATE_CON(13), 5, GFLAGS),
539
540 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
541 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
542 RK3399_CLKGATE_CON(13), 6, GFLAGS),
543
544 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
545 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
546 RK3399_CLKGATE_CON(13), 7, GFLAGS),
547
548 /* little core */
549 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
550 RK3399_CLKGATE_CON(0), 0, GFLAGS),
551 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
552 RK3399_CLKGATE_CON(0), 1, GFLAGS),
553 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
554 RK3399_CLKGATE_CON(0), 2, GFLAGS),
555 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
556 RK3399_CLKGATE_CON(0), 3, GFLAGS),
557
558 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
559 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
560 RK3399_CLKGATE_CON(0), 4, GFLAGS),
561 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
562 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
563 RK3399_CLKGATE_CON(0), 5, GFLAGS),
564 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
565 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
566 RK3399_CLKGATE_CON(0), 6, GFLAGS),
567
568 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
569 RK3399_CLKGATE_CON(14), 12, GFLAGS),
570 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
571 RK3399_CLKGATE_CON(14), 13, GFLAGS),
572
573 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
574 RK3399_CLKGATE_CON(14), 9, GFLAGS),
575 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
576 RK3399_CLKGATE_CON(14), 10, GFLAGS),
577 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
578 RK3399_CLKGATE_CON(14), 11, GFLAGS),
579 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0,
580 RK3399_CLKGATE_CON(0), 7, GFLAGS),
581
582 /* big core */
583 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
584 RK3399_CLKGATE_CON(1), 0, GFLAGS),
585 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
586 RK3399_CLKGATE_CON(1), 1, GFLAGS),
587 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
588 RK3399_CLKGATE_CON(1), 2, GFLAGS),
589 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
590 RK3399_CLKGATE_CON(1), 3, GFLAGS),
591
592 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
593 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
594 RK3399_CLKGATE_CON(1), 4, GFLAGS),
595 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
596 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
597 RK3399_CLKGATE_CON(1), 5, GFLAGS),
598 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
599 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
600 RK3399_CLKGATE_CON(1), 6, GFLAGS),
601
602 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
603 RK3399_CLKGATE_CON(14), 5, GFLAGS),
604 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
605 RK3399_CLKGATE_CON(14), 6, GFLAGS),
606
607 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
608 RK3399_CLKGATE_CON(14), 1, GFLAGS),
609 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
610 RK3399_CLKGATE_CON(14), 3, GFLAGS),
611 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
612 RK3399_CLKGATE_CON(14), 4, GFLAGS),
613
614 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
615 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
616
617 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
618 RK3399_CLKGATE_CON(14), 2, GFLAGS),
619
620 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0,
621 RK3399_CLKGATE_CON(1), 7, GFLAGS),
622
623 /* gmac */
624 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
625 RK3399_CLKGATE_CON(6), 9, GFLAGS),
626 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
627 RK3399_CLKGATE_CON(6), 8, GFLAGS),
628 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
629 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
630 RK3399_CLKGATE_CON(6), 10, GFLAGS),
631
632 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
633 RK3399_CLKGATE_CON(32), 0, GFLAGS),
634 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IS_CRITICAL,
635 RK3399_CLKGATE_CON(32), 1, GFLAGS),
636 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
637 RK3399_CLKGATE_CON(32), 4, GFLAGS),
638
639 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
640 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
641 RK3399_CLKGATE_CON(6), 11, GFLAGS),
642 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
643 RK3399_CLKGATE_CON(32), 2, GFLAGS),
644 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IS_CRITICAL,
645 RK3399_CLKGATE_CON(32), 3, GFLAGS),
646
647 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
648 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
649 RK3399_CLKGATE_CON(5), 5, GFLAGS),
650
651 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
652 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
653 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
654 RK3399_CLKGATE_CON(5), 7, GFLAGS),
655 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
656 RK3399_CLKGATE_CON(5), 6, GFLAGS),
657 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
658 RK3399_CLKGATE_CON(5), 8, GFLAGS),
659 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
660 RK3399_CLKGATE_CON(5), 9, GFLAGS),
661
662 /* spdif */
663 COMPOSITE(SCLK_SPDIF_DIV, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
664 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
665 RK3399_CLKGATE_CON(8), 13, GFLAGS),
666 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
667 RK3399_CLKSEL_CON(99), 0,
668 RK3399_CLKGATE_CON(8), 14, GFLAGS,
669 &rk3399_spdif_fracmux),
670 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
671 RK3399_CLKGATE_CON(8), 15, GFLAGS),
672
673 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
674 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
675 RK3399_CLKGATE_CON(10), 6, GFLAGS),
676 /* i2s */
677 COMPOSITE(SCLK_I2S0_DIV, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
678 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
679 RK3399_CLKGATE_CON(8), 3, GFLAGS),
680 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
681 RK3399_CLKSEL_CON(96), 0,
682 RK3399_CLKGATE_CON(8), 4, GFLAGS,
683 &rk3399_i2s0_fracmux),
684 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
685 RK3399_CLKGATE_CON(8), 5, GFLAGS),
686
687 COMPOSITE(SCLK_I2S1_DIV, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
688 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
689 RK3399_CLKGATE_CON(8), 6, GFLAGS),
690 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
691 RK3399_CLKSEL_CON(97), 0,
692 RK3399_CLKGATE_CON(8), 7, GFLAGS,
693 &rk3399_i2s1_fracmux),
694 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
695 RK3399_CLKGATE_CON(8), 8, GFLAGS),
696
697 COMPOSITE(SCLK_I2S2_DIV, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
698 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
699 RK3399_CLKGATE_CON(8), 9, GFLAGS),
700 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
701 RK3399_CLKSEL_CON(98), 0,
702 RK3399_CLKGATE_CON(8), 10, GFLAGS,
703 &rk3399_i2s2_fracmux),
704 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
705 RK3399_CLKGATE_CON(8), 11, GFLAGS),
706
707 MUX(SCLK_I2SOUT_SRC, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
708 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
709 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
710 RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
711 RK3399_CLKGATE_CON(8), 12, GFLAGS),
712
713 /* uart */
714 MUX(SCLK_UART0_SRC, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
715 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
716 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
717 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
718 RK3399_CLKGATE_CON(9), 0, GFLAGS),
719 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
720 RK3399_CLKSEL_CON(100), 0,
721 RK3399_CLKGATE_CON(9), 1, GFLAGS,
722 &rk3399_uart0_fracmux),
723
724 MUX(SCLK_UART_SRC, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
725 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
726 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
727 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
728 RK3399_CLKGATE_CON(9), 2, GFLAGS),
729 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
730 RK3399_CLKSEL_CON(101), 0,
731 RK3399_CLKGATE_CON(9), 3, GFLAGS,
732 &rk3399_uart1_fracmux),
733
734 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
735 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
736 RK3399_CLKGATE_CON(9), 4, GFLAGS),
737 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
738 RK3399_CLKSEL_CON(102), 0,
739 RK3399_CLKGATE_CON(9), 5, GFLAGS,
740 &rk3399_uart2_fracmux),
741
742 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
743 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
744 RK3399_CLKGATE_CON(9), 6, GFLAGS),
745 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
746 RK3399_CLKSEL_CON(103), 0,
747 RK3399_CLKGATE_CON(9), 7, GFLAGS,
748 &rk3399_uart3_fracmux),
749
750 COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
751 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
752 RK3399_CLKGATE_CON(3), 4, GFLAGS),
753
754 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IS_CRITICAL,
755 RK3399_CLKGATE_CON(18), 10, GFLAGS),
756 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
757 RK3399_CLKGATE_CON(18), 12, GFLAGS),
758 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
759 RK3399_CLKGATE_CON(18), 15, GFLAGS),
760 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
761 RK3399_CLKGATE_CON(19), 2, GFLAGS),
762
763 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0,
764 RK3399_CLKGATE_CON(4), 11, GFLAGS),
765 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0,
766 RK3399_CLKGATE_CON(3), 5, GFLAGS),
767 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0,
768 RK3399_CLKGATE_CON(3), 6, GFLAGS),
769
770 /* cci */
771 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IS_CRITICAL,
772 RK3399_CLKGATE_CON(2), 0, GFLAGS),
773 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IS_CRITICAL,
774 RK3399_CLKGATE_CON(2), 1, GFLAGS),
775 GATE(0, "npll_aclk_cci_src", "npll", CLK_IS_CRITICAL,
776 RK3399_CLKGATE_CON(2), 2, GFLAGS),
777 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IS_CRITICAL,
778 RK3399_CLKGATE_CON(2), 3, GFLAGS),
779
780 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IS_CRITICAL,
781 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
782 RK3399_CLKGATE_CON(2), 4, GFLAGS),
783
784 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IS_CRITICAL,
785 RK3399_CLKGATE_CON(15), 0, GFLAGS),
786 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IS_CRITICAL,
787 RK3399_CLKGATE_CON(15), 1, GFLAGS),
788 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IS_CRITICAL,
789 RK3399_CLKGATE_CON(15), 2, GFLAGS),
790 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IS_CRITICAL,
791 RK3399_CLKGATE_CON(15), 3, GFLAGS),
792 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IS_CRITICAL,
793 RK3399_CLKGATE_CON(15), 4, GFLAGS),
794 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IS_CRITICAL,
795 RK3399_CLKGATE_CON(15), 7, GFLAGS),
796
797 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
798 RK3399_CLKGATE_CON(2), 5, GFLAGS),
799 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
800 RK3399_CLKGATE_CON(2), 6, GFLAGS),
801 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
802 RK3399_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
803 RK3399_CLKGATE_CON(2), 7, GFLAGS),
804
805 GATE(0, "cpll_cs", "cpll", CLK_IS_CRITICAL,
806 RK3399_CLKGATE_CON(2), 8, GFLAGS),
807 GATE(0, "gpll_cs", "gpll", CLK_IS_CRITICAL,
808 RK3399_CLKGATE_CON(2), 9, GFLAGS),
809 GATE(0, "npll_cs", "npll", CLK_IS_CRITICAL,
810 RK3399_CLKGATE_CON(2), 10, GFLAGS),
811 COMPOSITE_NOGATE(SCLK_CS, "clk_cs", mux_cs_p, CLK_IS_CRITICAL,
812 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
813 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
814 RK3399_CLKGATE_CON(15), 5, GFLAGS),
815 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IS_CRITICAL,
816 RK3399_CLKGATE_CON(15), 6, GFLAGS),
817
818 /* vcodec */
819 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
820 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
821 RK3399_CLKGATE_CON(4), 0, GFLAGS),
822 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
823 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
824 RK3399_CLKGATE_CON(4), 1, GFLAGS),
825 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
826 RK3399_CLKGATE_CON(17), 2, GFLAGS),
827 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IS_CRITICAL,
828 RK3399_CLKGATE_CON(17), 3, GFLAGS),
829
830 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
831 RK3399_CLKGATE_CON(17), 0, GFLAGS),
832 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IS_CRITICAL,
833 RK3399_CLKGATE_CON(17), 1, GFLAGS),
834
835 /* vdu */
836 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
837 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
838 RK3399_CLKGATE_CON(4), 4, GFLAGS),
839 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
840 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
841 RK3399_CLKGATE_CON(4), 5, GFLAGS),
842
843 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
844 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
845 RK3399_CLKGATE_CON(4), 2, GFLAGS),
846 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
847 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
848 RK3399_CLKGATE_CON(4), 3, GFLAGS),
849 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
850 RK3399_CLKGATE_CON(17), 10, GFLAGS),
851 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IS_CRITICAL,
852 RK3399_CLKGATE_CON(17), 11, GFLAGS),
853
854 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
855 RK3399_CLKGATE_CON(17), 8, GFLAGS),
856 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IS_CRITICAL,
857 RK3399_CLKGATE_CON(17), 9, GFLAGS),
858
859 /* iep */
860 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
861 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
862 RK3399_CLKGATE_CON(4), 6, GFLAGS),
863 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
864 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
865 RK3399_CLKGATE_CON(4), 7, GFLAGS),
866 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
867 RK3399_CLKGATE_CON(16), 2, GFLAGS),
868 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IS_CRITICAL,
869 RK3399_CLKGATE_CON(16), 3, GFLAGS),
870
871 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
872 RK3399_CLKGATE_CON(16), 0, GFLAGS),
873 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IS_CRITICAL,
874 RK3399_CLKGATE_CON(16), 1, GFLAGS),
875
876 /* rga */
877 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
878 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
879 RK3399_CLKGATE_CON(4), 10, GFLAGS),
880
881 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
882 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
883 RK3399_CLKGATE_CON(4), 8, GFLAGS),
884 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
885 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
886 RK3399_CLKGATE_CON(4), 9, GFLAGS),
887 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
888 RK3399_CLKGATE_CON(16), 10, GFLAGS),
889 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IS_CRITICAL,
890 RK3399_CLKGATE_CON(16), 11, GFLAGS),
891
892 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
893 RK3399_CLKGATE_CON(16), 8, GFLAGS),
894 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IS_CRITICAL,
895 RK3399_CLKGATE_CON(16), 9, GFLAGS),
896
897 /* center */
898 COMPOSITE(ACLK_CENTER, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IS_CRITICAL,
899 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
900 RK3399_CLKGATE_CON(3), 7, GFLAGS),
901 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IS_CRITICAL,
902 RK3399_CLKGATE_CON(19), 0, GFLAGS),
903 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IS_CRITICAL,
904 RK3399_CLKGATE_CON(19), 1, GFLAGS),
905
906 /* gpu */
907 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
908 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
909 RK3399_CLKGATE_CON(13), 0, GFLAGS),
910 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
911 RK3399_CLKGATE_CON(30), 8, GFLAGS),
912 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
913 RK3399_CLKGATE_CON(30), 10, GFLAGS),
914 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
915 RK3399_CLKGATE_CON(30), 11, GFLAGS),
916 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
917 RK3399_CLKGATE_CON(13), 1, GFLAGS),
918
919 /* perihp */
920 GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IS_CRITICAL,
921 RK3399_CLKGATE_CON(5), 1, GFLAGS),
922 GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IS_CRITICAL,
923 RK3399_CLKGATE_CON(5), 0, GFLAGS),
924 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IS_CRITICAL,
925 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
926 RK3399_CLKGATE_CON(5), 2, GFLAGS),
927 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IS_CRITICAL,
928 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
929 RK3399_CLKGATE_CON(5), 3, GFLAGS),
930 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IS_CRITICAL,
931 RK3399_CLKSEL_CON(14), 12, 3, DFLAGS,
932 RK3399_CLKGATE_CON(5), 4, GFLAGS),
933
934 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
935 RK3399_CLKGATE_CON(20), 2, GFLAGS),
936 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
937 RK3399_CLKGATE_CON(20), 10, GFLAGS),
938 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IS_CRITICAL,
939 RK3399_CLKGATE_CON(20), 12, GFLAGS),
940
941 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
942 RK3399_CLKGATE_CON(20), 5, GFLAGS),
943 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
944 RK3399_CLKGATE_CON(20), 6, GFLAGS),
945 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
946 RK3399_CLKGATE_CON(20), 7, GFLAGS),
947 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
948 RK3399_CLKGATE_CON(20), 8, GFLAGS),
949 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
950 RK3399_CLKGATE_CON(20), 9, GFLAGS),
951 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IS_CRITICAL,
952 RK3399_CLKGATE_CON(20), 13, GFLAGS),
953 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
954 RK3399_CLKGATE_CON(20), 15, GFLAGS),
955
956 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IS_CRITICAL,
957 RK3399_CLKGATE_CON(20), 4, GFLAGS),
958 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
959 RK3399_CLKGATE_CON(20), 11, GFLAGS),
960 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IS_CRITICAL,
961 RK3399_CLKGATE_CON(20), 14, GFLAGS),
962 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
963 RK3399_CLKGATE_CON(31), 8, GFLAGS),
964
965 /* sdio & sdmmc */
966 COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
967 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
968 RK3399_CLKGATE_CON(12), 13, GFLAGS),
969 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
970 RK3399_CLKGATE_CON(33), 8, GFLAGS),
971 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IS_CRITICAL,
972 RK3399_CLKGATE_CON(33), 9, GFLAGS),
973
974 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
975 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
976 RK3399_CLKGATE_CON(6), 0, GFLAGS),
977
978 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
979 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
980 RK3399_CLKGATE_CON(6), 1, GFLAGS),
981
982 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
983 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
984
985 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
986 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
987
988 /* pcie */
989 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
990 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
991 RK3399_CLKGATE_CON(6), 2, GFLAGS),
992
993 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
994 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
995 RK3399_CLKGATE_CON(12), 6, GFLAGS),
996 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
997 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
998
999 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
1000 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
1001 RK3399_CLKGATE_CON(6), 3, GFLAGS),
1002 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
1003 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
1004
1005 /* emmc */
1006 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
1007 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
1008 RK3399_CLKGATE_CON(6), 14, GFLAGS),
1009
1010 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
1011 RK3399_CLKGATE_CON(6), 13, GFLAGS),
1012 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
1013 RK3399_CLKGATE_CON(6), 12, GFLAGS),
1014 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
1015 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
1016 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
1017 RK3399_CLKGATE_CON(32), 8, GFLAGS),
1018 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IS_CRITICAL,
1019 RK3399_CLKGATE_CON(32), 9, GFLAGS),
1020 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
1021 RK3399_CLKGATE_CON(32), 10, GFLAGS),
1022
1023 /* perilp0 */
1024 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IS_CRITICAL,
1025 RK3399_CLKGATE_CON(7), 1, GFLAGS),
1026 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IS_CRITICAL,
1027 RK3399_CLKGATE_CON(7), 0, GFLAGS),
1028 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IS_CRITICAL,
1029 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
1030 RK3399_CLKGATE_CON(7), 2, GFLAGS),
1031 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IS_CRITICAL,
1032 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
1033 RK3399_CLKGATE_CON(7), 3, GFLAGS),
1034 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", CLK_IS_CRITICAL,
1035 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
1036 RK3399_CLKGATE_CON(7), 4, GFLAGS),
1037
1038 /* aclk_perilp0 gates */
1039 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
1040 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
1041 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
1042 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
1043 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
1044 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
1045 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
1046 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
1047 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
1048 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
1049 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 6, GFLAGS),
1050 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 7, GFLAGS),
1051
1052 /* hclk_perilp0 gates */
1053 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
1054 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
1055 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
1056 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
1057 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
1058 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 8, GFLAGS),
1059
1060 /* pclk_perilp0 gates */
1061 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
1062
1063 /* crypto */
1064 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
1065 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
1066 RK3399_CLKGATE_CON(7), 7, GFLAGS),
1067
1068 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
1069 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
1070 RK3399_CLKGATE_CON(7), 8, GFLAGS),
1071
1072 /* cm0s_perilp */
1073 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
1074 RK3399_CLKGATE_CON(7), 6, GFLAGS),
1075 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
1076 RK3399_CLKGATE_CON(7), 5, GFLAGS),
1077 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
1078 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
1079 RK3399_CLKGATE_CON(7), 9, GFLAGS),
1080
1081 /* fclk_cm0s gates */
1082 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
1083 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
1084 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
1085 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
1086 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 11, GFLAGS),
1087
1088 /* perilp1 */
1089 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IS_CRITICAL,
1090 RK3399_CLKGATE_CON(8), 1, GFLAGS),
1091 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IS_CRITICAL,
1092 RK3399_CLKGATE_CON(8), 0, GFLAGS),
1093 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IS_CRITICAL,
1094 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
1095 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IS_CRITICAL,
1096 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
1097 RK3399_CLKGATE_CON(8), 2, GFLAGS),
1098
1099 /* hclk_perilp1 gates */
1100 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1101 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 12, GFLAGS),
1102 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
1103 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
1104 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
1105 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
1106 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
1107 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
1108 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1109
1110 /* pclk_perilp1 gates */
1111 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
1112 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
1113 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
1114 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
1115 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
1116 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1117 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1118 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1119 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1120 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1121 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1122 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1123 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1124 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1125 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1126 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1127 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1128 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1129 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1130 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1131 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1132
1133 /* saradc */
1134 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1135 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1136 RK3399_CLKGATE_CON(9), 11, GFLAGS),
1137
1138 /* tsadc */
1139 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
1140 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1141 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1142
1143 /* cif_testout */
1144 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1145 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1146 COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0,
1147 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1148 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1149
1150 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1151 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1152 COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0,
1153 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1154 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1155
1156 /* vio */
1157 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1158 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1159 RK3399_CLKGATE_CON(11), 0, GFLAGS),
1160 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", CLK_IS_CRITICAL,
1161 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1162 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1163
1164 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IS_CRITICAL,
1165 RK3399_CLKGATE_CON(29), 0, GFLAGS),
1166
1167 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
1168 RK3399_CLKGATE_CON(29), 1, GFLAGS),
1169 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
1170 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1171 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IS_CRITICAL,
1172 RK3399_CLKGATE_CON(29), 12, GFLAGS),
1173
1174 /* hdcp */
1175 COMPOSITE_NOGATE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
1176 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS),
1177 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
1178 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1179 RK3399_CLKGATE_CON(11), 3, GFLAGS),
1180 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
1181 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1182 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1183
1184 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IS_CRITICAL,
1185 RK3399_CLKGATE_CON(29), 4, GFLAGS),
1186 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
1187 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1188
1189 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IS_CRITICAL,
1190 RK3399_CLKGATE_CON(29), 5, GFLAGS),
1191 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
1192 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1193
1194 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IS_CRITICAL,
1195 RK3399_CLKGATE_CON(29), 3, GFLAGS),
1196 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
1197 RK3399_CLKGATE_CON(29), 6, GFLAGS),
1198 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
1199 RK3399_CLKGATE_CON(29), 7, GFLAGS),
1200 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
1201 RK3399_CLKGATE_CON(29), 8, GFLAGS),
1202 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
1203 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1204
1205 /* edp */
1206 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
1207 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1208 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1209
1210 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
1211 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
1212 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1213 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IS_CRITICAL,
1214 RK3399_CLKGATE_CON(32), 12, GFLAGS),
1215 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
1216 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1217
1218 /* hdmi */
1219 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1220 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1221
1222 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
1223 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1224 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1225
1226 /* vop0 */
1227 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1228 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1229 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1230 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1231 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1232 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1233
1234 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
1235 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1236 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IS_CRITICAL,
1237 RK3399_CLKGATE_CON(28), 1, GFLAGS),
1238
1239 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
1240 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1241 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IS_CRITICAL,
1242 RK3399_CLKGATE_CON(28), 0, GFLAGS),
1243
1244 #ifdef RK3399_TWO_PLL_FOR_VOP
1245 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1246 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1247 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1248 #else
1249 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
1250 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1251 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1252 #endif
1253
1254 /* The VOP0 is main screen, it is able to re-set parent rate. */
1255 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1256 RK3399_CLKSEL_CON(106), 0,
1257 &rk3399_dclk_vop0_fracmux),
1258
1259 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
1260 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1261 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1262
1263 /* vop1 */
1264 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1265 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1266 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1267 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1268 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1269 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1270
1271 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
1272 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1273 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IS_CRITICAL,
1274 RK3399_CLKGATE_CON(28), 5, GFLAGS),
1275
1276 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
1277 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1278 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IS_CRITICAL,
1279 RK3399_CLKGATE_CON(28), 4, GFLAGS),
1280
1281 /* The VOP1 is sub screen, it is note able to re-set parent rate. */
1282 #ifdef RK3399_TWO_PLL_FOR_VOP
1283 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1284 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1285 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1286 #else
1287 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_dmyvpll_cpll_gpll_p, 0,
1288 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1289 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1290 #endif
1291
1292 COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
1293 RK3399_CLKSEL_CON(107), 0,
1294 &rk3399_dclk_vop1_fracmux),
1295
1296 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
1297 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1298 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1299
1300 /* isp */
1301 COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
1302 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1303 RK3399_CLKGATE_CON(12), 8, GFLAGS),
1304 COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
1305 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1306 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1307
1308 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IS_CRITICAL,
1309 RK3399_CLKGATE_CON(27), 1, GFLAGS),
1310 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
1311 RK3399_CLKGATE_CON(27), 5, GFLAGS),
1312
1313 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IS_CRITICAL,
1314 RK3399_CLKGATE_CON(27), 0, GFLAGS),
1315 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
1316 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1317
1318 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
1319 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1320 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1321
1322 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
1323 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1324 RK3399_CLKGATE_CON(12), 10, GFLAGS),
1325 COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
1326 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1327 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1328
1329 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IS_CRITICAL,
1330 RK3399_CLKGATE_CON(27), 3, GFLAGS),
1331 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "aclk_isp1", 0,
1332 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1333
1334 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IS_CRITICAL,
1335 RK3399_CLKGATE_CON(27), 2, GFLAGS),
1336 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "hclk_isp1", 0,
1337 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1338
1339 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
1340 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1341 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1342
1343 /*
1344 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1345 * so we ignore the mux and make clocks nodes as following,
1346 *
1347 * pclkin_cifinv --|-------\
1348 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1349 * pclkin_cif --|-------/
1350 */
1351 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
1352 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1353
1354 /* cif */
1355 COMPOSITE_NODIV(SCLK_CIF_OUT_SRC, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
1356 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
1357 RK3399_CLKGATE_CON(10), 7, GFLAGS),
1358
1359 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1360 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
1361
1362 /* gic */
1363 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
1364 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1365 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1366
1367 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1368 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1369 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1370 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1371 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1372 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1373
1374 /* alive */
1375 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1376 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1377 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1378
1379 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1380 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1381 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1382 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1383 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1384
1385 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1386 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1387 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1388 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1389 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1390 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1391 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1392 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1393 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1394
1395 /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1396 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"),
1397
1398 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1399 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 0, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1400
1401 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1402 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1403 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1404 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1405
1406 /* testout */
1407 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1408 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1409 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
1410 RK3399_CLKSEL_CON(105), 0,
1411 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1412
1413 DIV(0, "clk_test_24m", "xin24m", 0,
1414 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1415
1416 /* spi */
1417 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1418 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1419 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1420
1421 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1422 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1423 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1424
1425 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1426 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1427 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1428
1429 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1430 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1431 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1432
1433 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1434 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1435 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1436
1437 /* i2c */
1438 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1439 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1440 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1441
1442 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1443 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1444 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1445
1446 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1447 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1448 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1449
1450 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1451 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1452 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1453
1454 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1455 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1456 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1457
1458 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1459 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1460 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1461
1462 /* timer */
1463 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1464 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1465 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1466 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1467 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1468 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1469 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1470 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1471 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1472 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1473 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1474 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1475
1476 /* clk_test */
1477 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1478 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1479 RK3399_CLKSEL_CON(58), 0, 5, DFLAGS,
1480 RK3399_CLKGATE_CON(13), 11, GFLAGS),
1481
1482 /* ddrc */
1483 GATE(0, "clk_ddrc_lpll_src", "lpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
1484 0, GFLAGS),
1485 GATE(0, "clk_ddrc_bpll_src", "bpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
1486 1, GFLAGS),
1487 GATE(0, "clk_ddrc_dpll_src", "dpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
1488 2, GFLAGS),
1489 GATE(0, "clk_ddrc_gpll_src", "gpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
1490 3, GFLAGS),
1491 COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0,
1492 RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
1493 };
1494
1495 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1496 /*
1497 * PMU CRU Clock-Architecture
1498 */
1499
1500 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IS_CRITICAL,
1501 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1502
1503 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IS_CRITICAL,
1504 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1505
1506 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
1507 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1508 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1509
1510 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1511 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1512 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1513
1514 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1515 RK3399_PMU_CLKSEL_CON(7), 0,
1516 &rk3399_pmuclk_wifi_fracmux),
1517
1518 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1519 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1520
1521 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1522 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1523 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1524
1525 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1526 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1527 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1528
1529 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1530 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1531 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1532
1533 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1534 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1535 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1536 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1537
1538 MUX(SCLK_UART4_SRC, "clk_uart4_src", mux_24m_ppll_p, CLK_SET_RATE_NO_REPARENT,
1539 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS),
1540
1541 COMPOSITE_NOMUX(0, "clk_uart4_div", "clk_uart4_src", CLK_SET_RATE_PARENT,
1542 RK3399_PMU_CLKSEL_CON(5), 0, 7, DFLAGS,
1543 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1544
1545 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1546 RK3399_PMU_CLKSEL_CON(6), 0,
1547 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1548 &rk3399_uart4_pmu_fracmux),
1549
1550 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IS_CRITICAL,
1551 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1552
1553 /* pmu clock gates */
1554 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1555 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1556
1557 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1558
1559 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1560 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1561 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1562 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1563 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1564 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1565 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1566 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1567 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1568 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1569 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1570 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1571 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1572 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1573 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1574 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1575
1576 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1577 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1578 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1579 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1580 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1581 };
1582
1583 static void __iomem *rk3399_cru_base;
1584 static void __iomem *rk3399_pmucru_base;
1585
rk3399_dump_cru(void)1586 void rk3399_dump_cru(void)
1587 {
1588 if (rk3399_cru_base) {
1589 pr_warn("CRU:\n");
1590 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1591 32, 4, rk3399_cru_base,
1592 0x594, false);
1593 }
1594 if (rk3399_pmucru_base) {
1595 pr_warn("PMU CRU:\n");
1596 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1597 32, 4, rk3399_pmucru_base,
1598 0x134, false);
1599 }
1600 }
1601 EXPORT_SYMBOL_GPL(rk3399_dump_cru);
1602
rk3399_clk_panic(struct notifier_block * this,unsigned long ev,void * ptr)1603 static int rk3399_clk_panic(struct notifier_block *this,
1604 unsigned long ev, void *ptr)
1605 {
1606 rk3399_dump_cru();
1607 return NOTIFY_DONE;
1608 }
1609
1610 static struct notifier_block rk3399_clk_panic_block = {
1611 .notifier_call = rk3399_clk_panic,
1612 };
1613
rk3399_clk_init(struct device_node * np)1614 static void __init rk3399_clk_init(struct device_node *np)
1615 {
1616 struct rockchip_clk_provider *ctx;
1617 void __iomem *reg_base;
1618 struct clk **clks;
1619
1620 reg_base = of_iomap(np, 0);
1621 if (!reg_base) {
1622 pr_err("%s: could not map cru region\n", __func__);
1623 return;
1624 }
1625
1626 rk3399_cru_base = reg_base;
1627
1628 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1629 if (IS_ERR(ctx)) {
1630 pr_err("%s: rockchip clk init failed\n", __func__);
1631 iounmap(reg_base);
1632 return;
1633 }
1634 clks = ctx->clk_data.clks;
1635
1636 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1637 ARRAY_SIZE(rk3399_pll_clks), -1);
1638
1639 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1640 ARRAY_SIZE(rk3399_clk_branches));
1641
1642 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1643 4, clks[PLL_APLLL], clks[PLL_GPLL],
1644 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1645 ARRAY_SIZE(rk3399_cpuclkl_rates));
1646
1647 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1648 4, clks[PLL_APLLB], clks[PLL_GPLL],
1649 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1650 ARRAY_SIZE(rk3399_cpuclkb_rates));
1651
1652 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1653 ROCKCHIP_SOFTRST_HIWORD_MASK);
1654
1655 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1656
1657 rockchip_clk_of_add_provider(np, ctx);
1658 }
1659 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1660
rk3399_pmu_clk_init(struct device_node * np)1661 static void __init rk3399_pmu_clk_init(struct device_node *np)
1662 {
1663 struct rockchip_clk_provider *ctx;
1664 void __iomem *reg_base;
1665
1666 reg_base = of_iomap(np, 0);
1667 if (!reg_base) {
1668 pr_err("%s: could not map cru pmu region\n", __func__);
1669 return;
1670 }
1671
1672 rk3399_pmucru_base = reg_base;
1673
1674 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1675 if (IS_ERR(ctx)) {
1676 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1677 iounmap(reg_base);
1678 return;
1679 }
1680
1681 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1682 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1683
1684 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1685 ARRAY_SIZE(rk3399_clk_pmu_branches));
1686
1687 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1688 ROCKCHIP_SOFTRST_HIWORD_MASK);
1689
1690 rockchip_clk_of_add_provider(np, ctx);
1691
1692 atomic_notifier_chain_register(&panic_notifier_list,
1693 &rk3399_clk_panic_block);
1694 }
1695 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
1696
1697 #ifdef MODULE
1698 struct clk_rk3399_inits {
1699 void (*inits)(struct device_node *np);
1700 };
1701
1702 static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
1703 .inits = rk3399_pmu_clk_init,
1704 };
1705
1706 static const struct clk_rk3399_inits clk_rk3399_cru_init = {
1707 .inits = rk3399_clk_init,
1708 };
1709
1710 static const struct of_device_id clk_rk3399_match_table[] = {
1711 {
1712 .compatible = "rockchip,rk3399-cru",
1713 .data = &clk_rk3399_cru_init,
1714 }, {
1715 .compatible = "rockchip,rk3399-pmucru",
1716 .data = &clk_rk3399_pmucru_init,
1717 },
1718 { }
1719 };
1720 MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
1721
clk_rk3399_probe(struct platform_device * pdev)1722 static int clk_rk3399_probe(struct platform_device *pdev)
1723 {
1724 struct device_node *np = pdev->dev.of_node;
1725 const struct of_device_id *match;
1726 const struct clk_rk3399_inits *init_data;
1727
1728 match = of_match_device(clk_rk3399_match_table, &pdev->dev);
1729 if (!match || !match->data)
1730 return -EINVAL;
1731
1732 init_data = match->data;
1733 if (init_data->inits)
1734 init_data->inits(np);
1735
1736 return 0;
1737 }
1738
1739 static struct platform_driver clk_rk3399_driver = {
1740 .probe = clk_rk3399_probe,
1741 .driver = {
1742 .name = "clk-rk3399",
1743 .of_match_table = clk_rk3399_match_table,
1744 .suppress_bind_attrs = true,
1745 },
1746 };
1747 module_platform_driver(clk_rk3399_driver);
1748
1749 MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
1750 MODULE_LICENSE("GPL");
1751 MODULE_ALIAS("platform:clk-rk3399");
1752 #endif /* MODULE */
1753