clk/rockchip/clk-rk3228.c

134 PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };
138 PNAME(mux_usb480m_p)		= { "usb480m_phy", "xin24m" };
139 PNAME(mux_hdmiphy_p)		= { "hdmiphy_phy", "xin24m" };
145 PNAME(mux_sclk_hdmi_cec_p)	= { "cpll", "gpll", "xin24m" };
147 PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "xin24m", "usb480m" };
161 PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
162 PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
163 PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
217 	DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
330 	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
355 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
357 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
359 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
361 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
363 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
365 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
416 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
462 	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
464 	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0,
467 	COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,