1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/module.h>
9 #include <linux/clk-provider.h>
10 #include <linux/io.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_device.h>
14 #include <dt-bindings/clock/rk3188-cru-common.h>
15 #include "clk.h"
16
17 #define RK3066_GRF_SOC_STATUS 0x15c
18 #define RK3188_GRF_SOC_STATUS 0xac
19
20 enum rk3188_plls {
21 apll, cpll, dpll, gpll,
22 };
23
24 static struct rockchip_pll_rate_table rk3188_pll_rates[] = {
25 RK3066_PLL_RATE(2208000000, 1, 92, 1),
26 RK3066_PLL_RATE(2184000000, 1, 91, 1),
27 RK3066_PLL_RATE(2160000000, 1, 90, 1),
28 RK3066_PLL_RATE(2136000000, 1, 89, 1),
29 RK3066_PLL_RATE(2112000000, 1, 88, 1),
30 RK3066_PLL_RATE(2088000000, 1, 87, 1),
31 RK3066_PLL_RATE(2064000000, 1, 86, 1),
32 RK3066_PLL_RATE(2040000000, 1, 85, 1),
33 RK3066_PLL_RATE(2016000000, 1, 84, 1),
34 RK3066_PLL_RATE(1992000000, 1, 83, 1),
35 RK3066_PLL_RATE(1968000000, 1, 82, 1),
36 RK3066_PLL_RATE(1944000000, 1, 81, 1),
37 RK3066_PLL_RATE(1920000000, 1, 80, 1),
38 RK3066_PLL_RATE(1896000000, 1, 79, 1),
39 RK3066_PLL_RATE(1872000000, 1, 78, 1),
40 RK3066_PLL_RATE(1848000000, 1, 77, 1),
41 RK3066_PLL_RATE(1824000000, 1, 76, 1),
42 RK3066_PLL_RATE(1800000000, 1, 75, 1),
43 RK3066_PLL_RATE(1776000000, 1, 74, 1),
44 RK3066_PLL_RATE(1752000000, 1, 73, 1),
45 RK3066_PLL_RATE(1728000000, 1, 72, 1),
46 RK3066_PLL_RATE(1704000000, 1, 71, 1),
47 RK3066_PLL_RATE(1680000000, 1, 70, 1),
48 RK3066_PLL_RATE(1656000000, 1, 69, 1),
49 RK3066_PLL_RATE(1632000000, 1, 68, 1),
50 RK3066_PLL_RATE(1608000000, 1, 67, 1),
51 RK3066_PLL_RATE(1560000000, 1, 65, 1),
52 RK3066_PLL_RATE(1512000000, 1, 63, 1),
53 RK3066_PLL_RATE(1488000000, 1, 62, 1),
54 RK3066_PLL_RATE(1464000000, 1, 61, 1),
55 RK3066_PLL_RATE(1440000000, 1, 60, 1),
56 RK3066_PLL_RATE(1416000000, 1, 59, 1),
57 RK3066_PLL_RATE(1392000000, 1, 58, 1),
58 RK3066_PLL_RATE(1368000000, 1, 57, 1),
59 RK3066_PLL_RATE(1344000000, 1, 56, 1),
60 RK3066_PLL_RATE(1320000000, 1, 55, 1),
61 RK3066_PLL_RATE(1296000000, 1, 54, 1),
62 RK3066_PLL_RATE(1272000000, 1, 53, 1),
63 RK3066_PLL_RATE(1248000000, 1, 52, 1),
64 RK3066_PLL_RATE(1224000000, 1, 51, 1),
65 RK3066_PLL_RATE(1200000000, 1, 50, 1),
66 RK3066_PLL_RATE(1188000000, 2, 99, 1),
67 RK3066_PLL_RATE(1176000000, 1, 49, 1),
68 RK3066_PLL_RATE(1128000000, 1, 47, 1),
69 RK3066_PLL_RATE(1104000000, 1, 46, 1),
70 RK3066_PLL_RATE(1008000000, 1, 84, 2),
71 RK3066_PLL_RATE( 912000000, 1, 76, 2),
72 RK3066_PLL_RATE( 891000000, 8, 594, 2),
73 RK3066_PLL_RATE( 888000000, 1, 74, 2),
74 RK3066_PLL_RATE( 816000000, 1, 68, 2),
75 RK3066_PLL_RATE( 798000000, 2, 133, 2),
76 RK3066_PLL_RATE( 792000000, 1, 66, 2),
77 RK3066_PLL_RATE( 768000000, 1, 64, 2),
78 RK3066_PLL_RATE( 742500000, 8, 495, 2),
79 RK3066_PLL_RATE( 696000000, 1, 58, 2),
80 RK3066_PLL_RATE( 600000000, 1, 50, 2),
81 RK3066_PLL_RATE( 594000000, 2, 198, 4),
82 RK3066_PLL_RATE( 552000000, 1, 46, 2),
83 RK3066_PLL_RATE( 504000000, 1, 84, 4),
84 RK3066_PLL_RATE( 456000000, 1, 76, 4),
85 RK3066_PLL_RATE( 408000000, 1, 68, 4),
86 RK3066_PLL_RATE( 400000000, 3, 100, 2),
87 RK3066_PLL_RATE( 384000000, 2, 128, 4),
88 RK3066_PLL_RATE( 360000000, 1, 60, 4),
89 RK3066_PLL_RATE( 312000000, 1, 52, 4),
90 RK3066_PLL_RATE( 300000000, 1, 50, 4),
91 RK3066_PLL_RATE( 297000000, 2, 198, 8),
92 RK3066_PLL_RATE( 252000000, 1, 84, 8),
93 RK3066_PLL_RATE( 216000000, 1, 72, 8),
94 RK3066_PLL_RATE( 148500000, 2, 99, 8),
95 RK3066_PLL_RATE( 126000000, 1, 84, 16),
96 RK3066_PLL_RATE( 48000000, 1, 64, 32),
97 { /* sentinel */ },
98 };
99
100 #define RK3066_DIV_CORE_PERIPH_MASK 0x3
101 #define RK3066_DIV_CORE_PERIPH_SHIFT 6
102 #define RK3066_DIV_ACLK_CORE_MASK 0x7
103 #define RK3066_DIV_ACLK_CORE_SHIFT 0
104 #define RK3066_DIV_ACLK_HCLK_MASK 0x3
105 #define RK3066_DIV_ACLK_HCLK_SHIFT 8
106 #define RK3066_DIV_ACLK_PCLK_MASK 0x3
107 #define RK3066_DIV_ACLK_PCLK_SHIFT 12
108 #define RK3066_DIV_AHB2APB_MASK 0x3
109 #define RK3066_DIV_AHB2APB_SHIFT 14
110
111 #define RK3066_CLKSEL0(_core_peri) \
112 { \
113 .reg = RK2928_CLKSEL_CON(0), \
114 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
115 RK3066_DIV_CORE_PERIPH_SHIFT) \
116 }
117 #define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb) \
118 { \
119 .reg = RK2928_CLKSEL_CON(1), \
120 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
121 RK3066_DIV_ACLK_CORE_SHIFT) | \
122 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
123 RK3066_DIV_ACLK_HCLK_SHIFT) | \
124 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
125 RK3066_DIV_ACLK_PCLK_SHIFT) | \
126 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
127 RK3066_DIV_AHB2APB_SHIFT), \
128 }
129
130 #define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \
131 { \
132 .prate = _prate, \
133 .divs = { \
134 RK3066_CLKSEL0(_core_peri), \
135 RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p), \
136 }, \
137 }
138
139 static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
140 RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1),
141 RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1),
142 RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1),
143 RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1),
144 RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1),
145 RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1),
146 RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0),
147 };
148
149 static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
150 .core_reg[0] = RK2928_CLKSEL_CON(0),
151 .div_core_shift[0] = 0,
152 .div_core_mask[0] = 0x1f,
153 .num_cores = 1,
154 .mux_core_alt = 1,
155 .mux_core_main = 0,
156 .mux_core_shift = 8,
157 .mux_core_mask = 0x1,
158 };
159
160 #define RK3188_DIV_ACLK_CORE_MASK 0x7
161 #define RK3188_DIV_ACLK_CORE_SHIFT 3
162
163 #define RK3188_CLKSEL1(_aclk_core) \
164 { \
165 .reg = RK2928_CLKSEL_CON(1), \
166 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
167 RK3188_DIV_ACLK_CORE_SHIFT) \
168 }
169 #define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core) \
170 { \
171 .prate = _prate, \
172 .divs = { \
173 RK3066_CLKSEL0(_core_peri), \
174 RK3188_CLKSEL1(_aclk_core), \
175 }, \
176 }
177
178 static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
179 RK3188_CPUCLK_RATE(1608000000, 2, 3),
180 RK3188_CPUCLK_RATE(1416000000, 2, 3),
181 RK3188_CPUCLK_RATE(1200000000, 2, 3),
182 RK3188_CPUCLK_RATE(1008000000, 2, 3),
183 RK3188_CPUCLK_RATE( 816000000, 2, 3),
184 RK3188_CPUCLK_RATE( 600000000, 1, 3),
185 RK3188_CPUCLK_RATE( 504000000, 1, 3),
186 RK3188_CPUCLK_RATE( 312000000, 0, 1),
187 };
188
189 static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
190 .core_reg[0] = RK2928_CLKSEL_CON(0),
191 .div_core_shift[0] = 9,
192 .div_core_mask[0] = 0x1f,
193 .num_cores = 1,
194 .mux_core_alt = 1,
195 .mux_core_main = 0,
196 .mux_core_shift = 8,
197 .mux_core_mask = 0x1,
198 };
199
200 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
201 PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
202 PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" };
203 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
204 PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
205 PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
206 PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" };
207 PNAME(mux_sclk_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
208 PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
209 PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" };
210 PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" };
211 PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" };
212 PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
213 PNAME(mux_mac_p) = { "gpll", "dpll" };
214 PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
215
216 static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
217 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
218 RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
219 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
220 RK2928_MODE_CON, 4, 4, 0, NULL),
221 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
222 RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
223 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
224 RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
225 };
226
227 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
228 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
229 RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
230 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
231 RK2928_MODE_CON, 4, 5, 0, NULL),
232 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
233 RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
234 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
235 RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
236 };
237
238 #define MFLAGS CLK_MUX_HIWORD_MASK
239 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
240 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
241 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
242
243 /* 2 ^ (val + 1) */
244 static struct clk_div_table div_core_peri_t[] = {
245 { .val = 0, .div = 2 },
246 { .val = 1, .div = 4 },
247 { .val = 2, .div = 8 },
248 { .val = 3, .div = 16 },
249 { /* sentinel */ },
250 };
251
252 static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata =
253 MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
254 RK2928_CLKSEL_CON(22), 4, 2, MFLAGS);
255
256 static struct rockchip_clk_branch common_spdif_fracmux __initdata =
257 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
258 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
259
260 static struct rockchip_clk_branch common_uart0_fracmux __initdata =
261 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
262 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
263
264 static struct rockchip_clk_branch common_uart1_fracmux __initdata =
265 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
266 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
267
268 static struct rockchip_clk_branch common_uart2_fracmux __initdata =
269 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
270 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
271
272 static struct rockchip_clk_branch common_uart3_fracmux __initdata =
273 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
274 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
275
276 static struct rockchip_clk_branch common_clk_branches[] __initdata = {
277 /*
278 * Clock-Architecture Diagram 2
279 */
280
281 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
282
283 /* these two are set by the cpuclk and should not be changed */
284 COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
285 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
286 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
287
288 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
289 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
290 RK2928_CLKGATE_CON(3), 9, GFLAGS),
291 GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0,
292 RK2928_CLKGATE_CON(3), 10, GFLAGS),
293 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
294 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
295 RK2928_CLKGATE_CON(3), 11, GFLAGS),
296 GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0,
297 RK2928_CLKGATE_CON(3), 12, GFLAGS),
298
299 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
300 RK2928_CLKGATE_CON(1), 7, GFLAGS),
301 COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
302 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
303 RK2928_CLKGATE_CON(0), 2, GFLAGS),
304
305 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IS_CRITICAL,
306 RK2928_CLKGATE_CON(0), 3, GFLAGS),
307
308 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
309 RK2928_CLKGATE_CON(0), 6, GFLAGS),
310 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", CLK_IS_CRITICAL,
311 RK2928_CLKGATE_CON(0), 5, GFLAGS),
312 GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IS_CRITICAL,
313 RK2928_CLKGATE_CON(0), 4, GFLAGS),
314
315 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
316 RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
317 RK2928_CLKGATE_CON(3), 0, GFLAGS),
318 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
319 RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
320 RK2928_CLKGATE_CON(1), 4, GFLAGS),
321
322 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
323 RK2928_CLKGATE_CON(2), 1, GFLAGS),
324 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
325 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
326 RK2928_CLKGATE_CON(2), 2, GFLAGS),
327 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
328 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
329 RK2928_CLKGATE_CON(2), 3, GFLAGS),
330
331 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
332 RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
333 COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0,
334 RK2928_CLKSEL_CON(29), 1, 5, DFLAGS,
335 RK2928_CLKGATE_CON(3), 7, GFLAGS),
336 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
337 RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
338
339 GATE(0, "pclkin_cif0", "ext_cif0", 0,
340 RK2928_CLKGATE_CON(3), 3, GFLAGS),
341 INVERTER(0, "pclk_cif0", "pclkin_cif0",
342 RK2928_CLKSEL_CON(30), 8, IFLAGS),
343
344 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
345
346 /*
347 * the 480m are generated inside the usb block from these clocks,
348 * but they are also a source for the hsicphy clock.
349 */
350 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
351 RK2928_CLKGATE_CON(1), 5, GFLAGS),
352 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
353 RK2928_CLKGATE_CON(1), 6, GFLAGS),
354
355 COMPOSITE(0, "mac_src", mux_mac_p, 0,
356 RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS,
357 RK2928_CLKGATE_CON(2), 5, GFLAGS),
358 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
359 RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
360 GATE(0, "sclk_mac_lbtest", "sclk_macref", CLK_IS_CRITICAL,
361 RK2928_CLKGATE_CON(2), 12, GFLAGS),
362
363 COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
364 RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
365 RK2928_CLKGATE_CON(2), 6, GFLAGS),
366 COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0,
367 RK2928_CLKSEL_CON(23), 0,
368 RK2928_CLKGATE_CON(2), 7, GFLAGS,
369 &common_hsadc_out_fracmux),
370 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
371 RK2928_CLKSEL_CON(22), 7, IFLAGS),
372
373 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
374 RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
375 RK2928_CLKGATE_CON(2), 8, GFLAGS),
376
377 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
378 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
379 RK2928_CLKGATE_CON(0), 13, GFLAGS),
380 COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
381 RK2928_CLKSEL_CON(9), 0,
382 RK2928_CLKGATE_CON(0), 14, GFLAGS,
383 &common_spdif_fracmux),
384
385 /*
386 * Clock-Architecture Diagram 4
387 */
388
389 GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
390 RK2928_CLKGATE_CON(2), 4, GFLAGS),
391
392 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
393 RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
394 RK2928_CLKGATE_CON(2), 9, GFLAGS),
395 COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0,
396 RK2928_CLKSEL_CON(25), 8, 7, DFLAGS,
397 RK2928_CLKGATE_CON(2), 10, GFLAGS),
398
399 COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0,
400 RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
401 RK2928_CLKGATE_CON(2), 11, GFLAGS),
402 COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0,
403 RK2928_CLKSEL_CON(12), 0, 6, DFLAGS,
404 RK2928_CLKGATE_CON(2), 13, GFLAGS),
405 COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
406 RK2928_CLKSEL_CON(12), 8, 6, DFLAGS,
407 RK2928_CLKGATE_CON(2), 14, GFLAGS),
408
409 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
410 RK2928_CLKSEL_CON(12), 15, 1, MFLAGS),
411 COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
412 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
413 RK2928_CLKGATE_CON(1), 8, GFLAGS),
414 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0,
415 RK2928_CLKSEL_CON(17), 0,
416 RK2928_CLKGATE_CON(1), 9, GFLAGS,
417 &common_uart0_fracmux),
418 COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
419 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
420 RK2928_CLKGATE_CON(1), 10, GFLAGS),
421 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0,
422 RK2928_CLKSEL_CON(18), 0,
423 RK2928_CLKGATE_CON(1), 11, GFLAGS,
424 &common_uart1_fracmux),
425 COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
426 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
427 RK2928_CLKGATE_CON(1), 12, GFLAGS),
428 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0,
429 RK2928_CLKSEL_CON(19), 0,
430 RK2928_CLKGATE_CON(1), 13, GFLAGS,
431 &common_uart2_fracmux),
432 COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
433 RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
434 RK2928_CLKGATE_CON(1), 14, GFLAGS),
435 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0,
436 RK2928_CLKSEL_CON(20), 0,
437 RK2928_CLKGATE_CON(1), 15, GFLAGS,
438 &common_uart3_fracmux),
439
440 GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
441
442 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
443 GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS),
444
445 /* clk_core_pre gates */
446 GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
447
448 /* aclk_cpu gates */
449 GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
450 GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
451 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
452
453 /* hclk_cpu gates */
454 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
455 GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
456 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
457 GATE(0, "hclk_cpubus", "hclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(4), 8, GFLAGS),
458 /* hclk_ahb2apb is part of a clk branch */
459 GATE(0, "hclk_vio_bus", "hclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(6), 12, GFLAGS),
460 GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
461 GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
462 GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
463 GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
464 GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
465
466 /* hclk_peri gates */
467 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
468 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
469 GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
470 GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
471 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
472 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
473 GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
474 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
475 GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
476 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
477 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
478 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS),
479
480 /* aclk_lcdc0_pre gates */
481 GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
482 GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
483 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
484 GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS),
485
486 /* aclk_lcdc1_pre gates */
487 GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
488 GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS),
489 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
490
491 /* atclk_cpu gates */
492 GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS),
493 GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
494
495 /* pclk_cpu gates */
496 GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
497 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
498 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
499 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
500 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
501 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
502 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
503 GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
504 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
505 GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
506 GATE(PCLK_PUBL, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
507 GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
508 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
509 GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
510
511 /* aclk_peri */
512 GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
513 GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
514 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
515 GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
516 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
517
518 /* pclk_peri gates */
519 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
520 GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
521 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
522 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
523 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS),
524 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
525 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
526 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
527 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
528 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
529 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
530 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
531 };
532
533 PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" };
534 PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" };
535 PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" };
536 PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" };
537 PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" };
538
539 static struct clk_div_table div_aclk_cpu_t[] = {
540 { .val = 0, .div = 1 },
541 { .val = 1, .div = 2 },
542 { .val = 2, .div = 3 },
543 { .val = 3, .div = 4 },
544 { .val = 4, .div = 8 },
545 { /* sentinel */ },
546 };
547
548 static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata =
549 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
550 RK2928_CLKSEL_CON(2), 8, 2, MFLAGS);
551
552 static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata =
553 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
554 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
555
556 static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata =
557 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
558 RK2928_CLKSEL_CON(4), 8, 2, MFLAGS);
559
560 static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
561 DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
562 RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t),
563 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
564 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
565 | CLK_DIVIDER_READ_ONLY),
566 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
567 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
568 | CLK_DIVIDER_READ_ONLY),
569 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
570 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
571 | CLK_DIVIDER_READ_ONLY,
572 RK2928_CLKGATE_CON(4), 9, GFLAGS),
573
574 GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
575 RK2928_CLKGATE_CON(9), 4, GFLAGS),
576
577 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, CLK_IS_CRITICAL,
578 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
579 RK2928_CLKGATE_CON(2), 0, GFLAGS),
580
581 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
582 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
583 RK2928_CLKGATE_CON(3), 1, GFLAGS),
584 MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,
585 RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
586 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
587 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
588 RK2928_CLKGATE_CON(3), 2, GFLAGS),
589 MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,
590 RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
591
592 COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
593 RK2928_CLKSEL_CON(29), 8, 5, DFLAGS,
594 RK2928_CLKGATE_CON(3), 8, GFLAGS),
595 MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
596 RK2928_CLKSEL_CON(29), 15, 1, MFLAGS),
597
598 GATE(0, "pclkin_cif1", "ext_cif1", 0,
599 RK2928_CLKGATE_CON(3), 4, GFLAGS),
600 INVERTER(0, "pclk_cif1", "pclkin_cif1",
601 RK2928_CLKSEL_CON(30), 12, IFLAGS),
602
603 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
604 RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
605 RK2928_CLKGATE_CON(3), 13, GFLAGS),
606 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
607 RK2928_CLKGATE_CON(5), 15, GFLAGS),
608
609 GATE(SCLK_TIMER2, "timer2", "xin24m", 0,
610 RK2928_CLKGATE_CON(3), 2, GFLAGS),
611
612 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
613 RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,
614 RK2928_CLKGATE_CON(2), 15, GFLAGS),
615
616 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
617 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
618 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
619 RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
620 RK2928_CLKGATE_CON(0), 7, GFLAGS),
621 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
622 RK2928_CLKSEL_CON(6), 0,
623 RK2928_CLKGATE_CON(0), 8, GFLAGS,
624 &rk3066a_i2s0_fracmux),
625 COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
626 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
627 RK2928_CLKGATE_CON(0), 9, GFLAGS),
628 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0,
629 RK2928_CLKSEL_CON(7), 0,
630 RK2928_CLKGATE_CON(0), 10, GFLAGS,
631 &rk3066a_i2s1_fracmux),
632 COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
633 RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
634 RK2928_CLKGATE_CON(0), 11, GFLAGS),
635 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0,
636 RK2928_CLKSEL_CON(8), 0,
637 RK2928_CLKGATE_CON(0), 12, GFLAGS,
638 &rk3066a_i2s2_fracmux),
639
640 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
641 GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
642 GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
643 GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
644
645 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
646 RK2928_CLKGATE_CON(5), 14, GFLAGS),
647
648 GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
649
650 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
651 GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
652 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
653 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
654 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
655
656 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
657 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS),
658 };
659
660 static struct clk_div_table div_rk3188_aclk_core_t[] = {
661 { .val = 0, .div = 1 },
662 { .val = 1, .div = 2 },
663 { .val = 2, .div = 3 },
664 { .val = 3, .div = 4 },
665 { .val = 4, .div = 8 },
666 { /* sentinel */ },
667 };
668
669 PNAME(mux_hsicphy_p) = { "sclk_otgphy0_480m", "sclk_otgphy1_480m",
670 "gpll", "cpll" };
671
672 static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
673 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
674 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
675
676 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
677 COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
678 RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
679 div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
680
681 /* do not source aclk_cpu_pre from the apll, to keep complexity down */
682 COMPOSITE_NOGATE(ACLK_CPU_PRE, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
683 RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
684 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
685 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
686 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
687 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
688 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
689 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
690 RK2928_CLKGATE_CON(4), 9, GFLAGS),
691
692 GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
693 RK2928_CLKGATE_CON(9), 4, GFLAGS),
694
695 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
696 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
697 RK2928_CLKGATE_CON(2), 0, GFLAGS),
698
699 COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
700 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
701 RK2928_CLKGATE_CON(3), 1, GFLAGS),
702 COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
703 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
704 RK2928_CLKGATE_CON(3), 2, GFLAGS),
705
706 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
707 RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS,
708 RK2928_CLKGATE_CON(3), 15, GFLAGS),
709 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
710 RK2928_CLKGATE_CON(9), 7, GFLAGS),
711
712 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS),
713 GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS),
714 GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
715 GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
716 GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
717
718 COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0,
719 RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
720 RK2928_CLKGATE_CON(3), 6, GFLAGS),
721 DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
722 RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
723
724 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
725 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
726 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
727 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
728 RK2928_CLKGATE_CON(0), 9, GFLAGS),
729 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
730 RK2928_CLKSEL_CON(7), 0,
731 RK2928_CLKGATE_CON(0), 10, GFLAGS,
732 &rk3188_i2s0_fracmux),
733
734 GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
735 GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
736
737 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
738 RK2928_CLKGATE_CON(7), 3, GFLAGS),
739 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
740
741 GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
742
743 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
744 GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
745
746 GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
747 };
748
rk3188_common_clk_init(struct device_node * np)749 static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
750 {
751 struct rockchip_clk_provider *ctx;
752 void __iomem *reg_base;
753
754 reg_base = of_iomap(np, 0);
755 if (!reg_base) {
756 pr_err("%s: could not map cru region\n", __func__);
757 return ERR_PTR(-ENOMEM);
758 }
759
760 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
761 if (IS_ERR(ctx)) {
762 pr_err("%s: rockchip clk init failed\n", __func__);
763 iounmap(reg_base);
764 return ERR_PTR(-ENOMEM);
765 }
766
767 rockchip_clk_register_branches(ctx, common_clk_branches,
768 ARRAY_SIZE(common_clk_branches));
769
770 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
771 ROCKCHIP_SOFTRST_HIWORD_MASK);
772
773 rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
774
775 return ctx;
776 }
777
rk3066a_clk_init(struct device_node * np)778 static void __init rk3066a_clk_init(struct device_node *np)
779 {
780 struct rockchip_clk_provider *ctx;
781 struct clk **clks;
782
783 ctx = rk3188_common_clk_init(np);
784 if (IS_ERR(ctx))
785 return;
786 clks = ctx->clk_data.clks;
787
788 rockchip_clk_register_plls(ctx, rk3066_pll_clks,
789 ARRAY_SIZE(rk3066_pll_clks),
790 RK3066_GRF_SOC_STATUS);
791 rockchip_clk_register_branches(ctx, rk3066a_clk_branches,
792 ARRAY_SIZE(rk3066a_clk_branches));
793 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
794 2, clks[PLL_APLL], clks[PLL_GPLL],
795 &rk3066_cpuclk_data, rk3066_cpuclk_rates,
796 ARRAY_SIZE(rk3066_cpuclk_rates));
797 rockchip_clk_of_add_provider(np, ctx);
798 }
799 CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
800
rk3188a_clk_init(struct device_node * np)801 static void __init rk3188a_clk_init(struct device_node *np)
802 {
803 struct rockchip_clk_provider *ctx;
804 struct clk **clks;
805 unsigned long rate;
806 int ret;
807
808 ctx = rk3188_common_clk_init(np);
809 if (IS_ERR(ctx))
810 return;
811 clks = ctx->clk_data.clks;
812
813 rockchip_clk_register_plls(ctx, rk3188_pll_clks,
814 ARRAY_SIZE(rk3188_pll_clks),
815 RK3188_GRF_SOC_STATUS);
816 rockchip_clk_register_branches(ctx, rk3188_clk_branches,
817 ARRAY_SIZE(rk3188_clk_branches));
818 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
819 2, clks[PLL_APLL], clks[PLL_GPLL],
820 &rk3188_cpuclk_data, rk3188_cpuclk_rates,
821 ARRAY_SIZE(rk3188_cpuclk_rates));
822
823 /* reparent aclk_cpu_pre from apll */
824 if (clks[ACLK_CPU_PRE] && clks[PLL_GPLL]) {
825 rate = clk_get_rate(clks[ACLK_CPU_PRE]);
826
827 ret = clk_set_parent(clks[ACLK_CPU_PRE], clks[PLL_GPLL]);
828 if (ret < 0)
829 pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
830 __func__);
831
832 clk_set_rate(clks[ACLK_CPU_PRE], rate);
833 } else {
834 pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
835 __func__);
836 }
837
838 rockchip_clk_of_add_provider(np, ctx);
839 }
840 CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
841
rk3188_clk_init(struct device_node * np)842 static void __init rk3188_clk_init(struct device_node *np)
843 {
844 int i;
845
846 for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) {
847 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
848 struct rockchip_pll_rate_table *rate;
849
850 if (!pll->rate_table)
851 continue;
852
853 rate = pll->rate_table;
854 while (rate->rate > 0) {
855 rate->nb = 1;
856 rate++;
857 }
858 }
859
860 rk3188a_clk_init(np);
861 }
862 CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);
863
864 struct clk_rk3188_inits {
865 void (*inits)(struct device_node *np);
866 };
867
868 static const struct clk_rk3188_inits clk_rk3066a_init = {
869 .inits = rk3066a_clk_init,
870 };
871
872 static const struct clk_rk3188_inits clk_rk3188a_init = {
873 .inits = rk3188a_clk_init,
874 };
875
876 static const struct clk_rk3188_inits clk_rk3188_init = {
877 .inits = rk3188_clk_init,
878 };
879
880 static const struct of_device_id clk_rk3188_match_table[] = {
881 {
882 .compatible = "rockchip,rk3066a-cru",
883 .data = &clk_rk3066a_init,
884 }, {
885 .compatible = "rockchip,rk3188a-cru",
886 .data = &clk_rk3188a_init,
887 }, {
888 .compatible = "rockchip,rk3188-cru",
889 .data = &rk3188_clk_init,
890 },
891 { }
892 };
893 MODULE_DEVICE_TABLE(of, clk_rk3188_match_table);
894
clk_rk3188_probe(struct platform_device * pdev)895 static int __init clk_rk3188_probe(struct platform_device *pdev)
896 {
897 struct device_node *np = pdev->dev.of_node;
898 const struct of_device_id *match;
899 const struct clk_rk3188_inits *init_data;
900
901 match = of_match_device(clk_rk3188_match_table, &pdev->dev);
902 if (!match || !match->data)
903 return -EINVAL;
904
905 init_data = match->data;
906 if (init_data->inits)
907 init_data->inits(np);
908
909 return 0;
910 }
911
912 static struct platform_driver clk_rk3188_driver = {
913 .driver = {
914 .name = "clk-rk3188",
915 .of_match_table = clk_rk3188_match_table,
916 },
917 };
918 builtin_platform_driver_probe(clk_rk3188_driver, clk_rk3188_probe);
919
920 MODULE_DESCRIPTION("Rockchip RK3188 Clock Driver");
921 MODULE_LICENSE("GPL");
922