clk/rockchip/clk-rv1126.c

152 PNAME(mux_pll_p)			= { "xin24m" };
156 PNAME(mux_uart1_p)			= { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
157 PNAME(mux_xin24m_gpll_p)		= { "xin24m", "gpll" };
158 PNAME(mux_gpll_xin24m_p)		= { "gpll", "xin24m" };
159 PNAME(mux_xin24m_32k_p)			= { "xin24m", "clk_rtc32k" };
163 PNAME(mux_usb480m_p)			= { "xin24m", "usb480m_phy", "clk_rtc32k" };
165 PNAME(mux_uart0_p)			= { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
166 PNAME(mux_uart2_p)			= { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
167 PNAME(mux_uart3_p)			= { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
168 PNAME(mux_uart4_p)			= { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
169 PNAME(mux_uart5_p)			= { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
178 PNAME(mux_audpwm_p)			= { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
179 PNAME(mux_dclk_vop_p)			= { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
183 PNAME(mux_cif_out2io_p)			= { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
184 PNAME(mux_mipicsi_out2io_p)		= { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
200 PNAME(mux_gpll_usb480m_cpll_xin24m_p)	= { "gpll", "usb480m", "cpll", "xin24m" };
203 PNAME(mux_gpll_cpll_usb480m_xin24m_p)	= { "gpll", "cpll", "usb480m", "xin24m" };
205 PNAME(mux_gpll_cpll_xin24m_p)		= { "gpll", "cpll", "xin24m" };
211 PNAME(mux_gpll_usb480m_cpll_xin24m_p)	= { "gpll", "usb480m", "dummy_cpll", "xin24m" };
214 PNAME(mux_gpll_cpll_usb480m_xin24m_p)	= { "gpll", "dummy_cpll", "usb480m", "xin24m" };
216 PNAME(mux_gpll_cpll_xin24m_p)		= { "gpll", "dummy_cpll", "xin24m" };
328 	COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
339 	GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
370 	GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
377 	GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
399 	GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
401 	GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
407 	GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
409 	GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
421 	GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
427 	GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
452 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
465 	GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
508 	GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
596 	GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
627 	COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
633 	GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
635 	GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
637 	GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
639 	GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
641 	GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
643 	GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
663 	SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
668 	COMPOSITE_NOMUX(CLK_NPU_TSADC, "clk_npu_tsadc", "xin24m", 0,
675 	COMPOSITE_NOMUX(CLK_CPU_TSADC, "clk_cpu_tsadc", "xin24m", 0,
1092 	GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
1137 	GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
1176 	GATE(CLK_NPUPVTM, "clk_npupvtm", "xin24m", 0,
1372 	GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,