1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
5 */
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/of_address.h>
10 #include <linux/of_device.h>
11 #include <linux/syscore_ops.h>
12 #include <dt-bindings/clock/rk1808-cru.h>
13 #include "clk.h"
14
15 #define RK1808_GRF_SOC_STATUS0 0x480
16 #define RK1808_PMUGRF_SOC_CON0 0x100
17 #define RK1808_UART_FRAC_MAX_PRATE 800000000
18 #define RK1808_PDM_FRAC_MAX_PRATE 300000000
19 #define RK1808_I2S_FRAC_MAX_PRATE 600000000
20 #define RK1808_VOP_RAW_FRAC_MAX_PRATE 300000000
21 #define RK1808_VOP_LITE_FRAC_MAX_PRATE 400000000
22
23 enum rk1808_plls {
24 apll, dpll, cpll, gpll, npll, ppll,
25 };
26
27 static struct rockchip_pll_rate_table rk1808_pll_rates[] = {
28 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
29 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
30 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
31 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
32 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
47 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1100000000, 2, 275, 3, 1, 1, 0),
49 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
50 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
51 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
52 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
53 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
54 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
55 RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
56 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
57 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
58 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
59 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
60 RK3036_PLL_RATE(800000000, 1, 100, 3, 1, 1, 0),
61 RK3036_PLL_RATE(700000000, 1, 175, 2, 1, 1, 0),
62 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
63 RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
64 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
65 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
66 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
67 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
68 RK3036_PLL_RATE(416000000, 1, 52, 3, 1, 1, 0),
69 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
70 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
71 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
72 RK3036_PLL_RATE(200000000, 1, 200, 6, 4, 1, 0),
73 RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
74 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
75 { /* sentinel */ },
76 };
77
78 #define RK1808_DIV_ACLKM_MASK 0x7
79 #define RK1808_DIV_ACLKM_SHIFT 12
80 #define RK1808_DIV_PCLK_DBG_MASK 0xf
81 #define RK1808_DIV_PCLK_DBG_SHIFT 8
82
83 #define RK1808_CLKSEL0(_aclk_core, _pclk_dbg) \
84 { \
85 .reg = RK1808_CLKSEL_CON(0), \
86 .val = HIWORD_UPDATE(_aclk_core, RK1808_DIV_ACLKM_MASK, \
87 RK1808_DIV_ACLKM_SHIFT) | \
88 HIWORD_UPDATE(_pclk_dbg, RK1808_DIV_PCLK_DBG_MASK, \
89 RK1808_DIV_PCLK_DBG_SHIFT), \
90 }
91
92 #define RK1808_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
93 { \
94 .prate = _prate, \
95 .divs = { \
96 RK1808_CLKSEL0(_aclk_core, _pclk_dbg), \
97 }, \
98 }
99
100 static struct rockchip_cpuclk_rate_table rk1808_cpuclk_rates[] __initdata = {
101 RK1808_CPUCLK_RATE(1608000000, 1, 7),
102 RK1808_CPUCLK_RATE(1512000000, 1, 7),
103 RK1808_CPUCLK_RATE(1488000000, 1, 5),
104 RK1808_CPUCLK_RATE(1416000000, 1, 5),
105 RK1808_CPUCLK_RATE(1392000000, 1, 5),
106 RK1808_CPUCLK_RATE(1296000000, 1, 5),
107 RK1808_CPUCLK_RATE(1200000000, 1, 5),
108 RK1808_CPUCLK_RATE(1104000000, 1, 5),
109 RK1808_CPUCLK_RATE(1008000000, 1, 5),
110 RK1808_CPUCLK_RATE(912000000, 1, 5),
111 RK1808_CPUCLK_RATE(816000000, 1, 3),
112 RK1808_CPUCLK_RATE(696000000, 1, 3),
113 RK1808_CPUCLK_RATE(600000000, 1, 3),
114 RK1808_CPUCLK_RATE(408000000, 1, 1),
115 RK1808_CPUCLK_RATE(312000000, 1, 1),
116 RK1808_CPUCLK_RATE(216000000, 1, 1),
117 RK1808_CPUCLK_RATE(96000000, 1, 1),
118 };
119
120 static const struct rockchip_cpuclk_reg_data rk1808_cpuclk_data = {
121 .core_reg[0] = RK1808_CLKSEL_CON(0),
122 .div_core_shift[0] = 0,
123 .div_core_mask[0] = 0xf,
124 .num_cores = 1,
125 .mux_core_alt = 2,
126 .mux_core_main = 0,
127 .mux_core_shift = 6,
128 .mux_core_mask = 0x3,
129 };
130
131 PNAME(mux_pll_p) = { "xin24m", "xin32k"};
132 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "xin32k" };
133 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
134 PNAME(mux_gpll_cpll_apll_p) = { "gpll", "cpll", "apll" };
135 PNAME(mux_npu_p) = { "clk_npu_div", "clk_npu_np5" };
136 PNAME(mux_ddr_p) = { "dpll_ddr", "gpll_ddr" };
137 PNAME(mux_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
138 PNAME(mux_gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
139 PNAME(mux_dclk_vopraw_p) = { "dclk_vopraw_src", "dclk_vopraw_frac", "xin24m" };
140 PNAME(mux_dclk_voplite_p) = { "dclk_voplite_src", "dclk_voplite_frac", "xin24m" };
141 PNAME(mux_24m_npll_gpll_usb480m_p) = { "xin24m", "npll", "gpll", "usb480m" };
142 PNAME(mux_usb3_otg0_suspend_p) = { "xin32k", "xin24m" };
143 PNAME(mux_pcie_aux_p) = { "xin24m", "clk_pcie_src" };
144 PNAME(mux_gpll_cpll_npll_24m_p) = { "gpll", "cpll", "npll", "xin24m" };
145 PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
146 PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
147 PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
148 PNAME(mux_cpll_npll_ppll_p) = { "cpll", "npll", "ppll" };
149 PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" };
150 PNAME(mux_gmac_rgmii_speed_p) = { "clk_gmac_tx_src", "clk_gmac_tx_src", "clk_gmac_tx_div50", "clk_gmac_tx_div5" };
151 PNAME(mux_gmac_rmii_speed_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
152 PNAME(mux_gmac_rx_tx_p) = { "clk_gmac_rgmii_speed", "clk_gmac_rmii_speed" };
153 PNAME(mux_gpll_usb480m_cpll_npll_p) = { "gpll", "usb480m", "cpll", "npll" };
154 PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac", "xin24m" };
155 PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac", "xin24m" };
156 PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac", "xin24m" };
157 PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac", "xin24m" };
158 PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac", "xin24m" };
159 PNAME(mux_uart6_p) = { "clk_uart6_src", "clk_uart6_np5", "clk_uart6_frac", "xin24m" };
160 PNAME(mux_uart7_p) = { "clk_uart7_src", "clk_uart7_np5", "clk_uart7_frac", "xin24m" };
161 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
162 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
163 PNAME(mux_gpll_xin24m_cpll_npll_p) = { "gpll", "xin24m", "cpll", "npll" };
164 PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
165 PNAME(mux_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "mclk_i2s0_8ch_in", "xin12m" };
166 PNAME(mux_i2s0_8ch_tx_rx_p) = { "clk_i2s0_8ch_tx_mux", "clk_i2s0_8ch_rx_mux"};
167 PNAME(mux_i2s0_8ch_tx_out_p) = { "clk_i2s0_8ch_tx", "xin12m", "clk_i2s0_8ch_rx" };
168 PNAME(mux_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "mclk_i2s0_8ch_in", "xin12m" };
169 PNAME(mux_i2s0_8ch_rx_tx_p) = { "clk_i2s0_8ch_rx_mux", "clk_i2s0_8ch_tx_mux"};
170 PNAME(mux_i2s0_8ch_rx_out_p) = { "clk_i2s0_8ch_rx", "xin12m", "clk_i2s0_8ch_tx" };
171 PNAME(mux_i2s1_2ch_p) = { "clk_i2s1_2ch_src", "clk_i2s1_2ch_frac", "mclk_i2s1_2ch_in", "xin12m" };
172 PNAME(mux_i2s1_2ch_out_p) = { "clk_i2s1_2ch", "xin12m" };
173 PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac" };
174 PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" };
175 PNAME(mux_gpll_usb480m_cpll_ppll_p) = { "gpll", "usb480m", "cpll", "ppll" };
176 PNAME(mux_uart0_pmu_p) = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac", "xin24m" };
177 PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
178 PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
179 PNAME(mux_pciephy_ref_p) = { "xin24m", "clk_pciephy_src" };
180 PNAME(mux_ppll_xin24m_p) = { "ppll", "xin24m" };
181 PNAME(mux_xin24m_32k_p) = { "xin24m", "xin32k" };
182 PNAME(mux_clk_32k_ioe_p) = { "clk_rtc32k_pmu", "xin32k" };
183
184 static struct rockchip_pll_clock rk1808_pll_clks[] __initdata = {
185 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p,
186 0, RK1808_PLL_CON(0),
187 RK1808_MODE_CON, 0, 0, 0, rk1808_pll_rates),
188 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p,
189 0, RK1808_PLL_CON(8),
190 RK1808_MODE_CON, 2, 1, 0, NULL),
191 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p,
192 0, RK1808_PLL_CON(16),
193 RK1808_MODE_CON, 4, 2, 0, rk1808_pll_rates),
194 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p,
195 0, RK1808_PLL_CON(24),
196 RK1808_MODE_CON, 6, 3, 0, rk1808_pll_rates),
197 [npll] = PLL(pll_rk3036, PLL_NPLL, "npll", mux_pll_p,
198 0, RK1808_PLL_CON(32),
199 RK1808_MODE_CON, 8, 5, 0, rk1808_pll_rates),
200 [ppll] = PLL(pll_rk3036, PLL_PPLL, "ppll", mux_pll_p,
201 0, RK1808_PMU_PLL_CON(0),
202 RK1808_PMU_MODE_CON, 0, 4, 0, rk1808_pll_rates),
203 };
204
205 #define MFLAGS CLK_MUX_HIWORD_MASK
206 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
207 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
208
209 static struct rockchip_clk_branch rk1808_uart1_fracmux __initdata =
210 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
211 RK1808_CLKSEL_CON(39), 14, 2, MFLAGS);
212
213 static struct rockchip_clk_branch rk1808_uart2_fracmux __initdata =
214 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
215 RK1808_CLKSEL_CON(42), 14, 2, MFLAGS);
216
217 static struct rockchip_clk_branch rk1808_uart3_fracmux __initdata =
218 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
219 RK1808_CLKSEL_CON(45), 14, 2, MFLAGS);
220
221 static struct rockchip_clk_branch rk1808_uart4_fracmux __initdata =
222 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
223 RK1808_CLKSEL_CON(48), 14, 2, MFLAGS);
224
225 static struct rockchip_clk_branch rk1808_uart5_fracmux __initdata =
226 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
227 RK1808_CLKSEL_CON(51), 14, 2, MFLAGS);
228
229 static struct rockchip_clk_branch rk1808_uart6_fracmux __initdata =
230 MUX(0, "clk_uart6_mux", mux_uart6_p, CLK_SET_RATE_PARENT,
231 RK1808_CLKSEL_CON(54), 14, 2, MFLAGS);
232
233 static struct rockchip_clk_branch rk1808_uart7_fracmux __initdata =
234 MUX(0, "clk_uart7_mux", mux_uart7_p, CLK_SET_RATE_PARENT,
235 RK1808_CLKSEL_CON(57), 14, 2, MFLAGS);
236
237 static struct rockchip_clk_branch rk1808_dclk_vopraw_fracmux __initdata =
238 MUX(0, "dclk_vopraw_mux", mux_dclk_vopraw_p, CLK_SET_RATE_PARENT,
239 RK1808_CLKSEL_CON(5), 14, 2, MFLAGS);
240
241 static struct rockchip_clk_branch rk1808_dclk_voplite_fracmux __initdata =
242 MUX(0, "dclk_voplite_mux", mux_dclk_voplite_p, CLK_SET_RATE_PARENT,
243 RK1808_CLKSEL_CON(7), 14, 2, MFLAGS);
244
245 static struct rockchip_clk_branch rk1808_pdm_fracmux __initdata =
246 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
247 RK1808_CLKSEL_CON(30), 15, 1, MFLAGS);
248
249 static struct rockchip_clk_branch rk1808_i2s0_8ch_tx_fracmux __initdata =
250 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
251 RK1808_CLKSEL_CON(32), 10, 2, MFLAGS);
252
253 static struct rockchip_clk_branch rk1808_i2s0_8ch_rx_fracmux __initdata =
254 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
255 RK1808_CLKSEL_CON(34), 10, 2, MFLAGS);
256
257 static struct rockchip_clk_branch rk1808_i2s1_2ch_fracmux __initdata =
258 MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT,
259 RK1808_CLKSEL_CON(36), 10, 2, MFLAGS);
260
261 static struct rockchip_clk_branch rk1808_rtc32k_pmu_fracmux __initdata =
262 MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT,
263 RK1808_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
264
265 static struct rockchip_clk_branch rk1808_uart0_pmu_fracmux __initdata =
266 MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT,
267 RK1808_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
268
269 static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
270 /*
271 * Clock-Architecture Diagram 1
272 */
273
274 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
275 RK1808_MODE_CON, 10, 2, MFLAGS),
276 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
277
278 /*
279 * Clock-Architecture Diagram 2
280 */
281
282 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
283 RK1808_CLKGATE_CON(0), 0, GFLAGS),
284 GATE(0, "cpll_core", "cpll", CLK_IGNORE_UNUSED,
285 RK1808_CLKGATE_CON(0), 0, GFLAGS),
286 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
287 RK1808_CLKGATE_CON(0), 0, GFLAGS),
288 COMPOSITE_NOMUX(0, "pclk_core_dbg", "armclk", CLK_IGNORE_UNUSED,
289 RK1808_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
290 RK1808_CLKGATE_CON(0), 3, GFLAGS),
291 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
292 RK1808_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
293 RK1808_CLKGATE_CON(0), 2, GFLAGS),
294
295 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
296 RK1808_CLKGATE_CON(0), 4, GFLAGS),
297
298 GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
299 RK1808_CLKGATE_CON(0), 5, GFLAGS),
300
301 COMPOSITE_NOMUX(MSCLK_CORE_NIU, "msclk_core_niu", "gpll", CLK_IS_CRITICAL,
302 RK1808_CLKSEL_CON(18), 0, 5, DFLAGS,
303 RK1808_CLKGATE_CON(0), 1, GFLAGS),
304
305 /*
306 * Clock-Architecture Diagram 3
307 */
308
309 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL,
310 RK1808_CLKSEL_CON(15), 11, 1, MFLAGS, 12, 4, DFLAGS,
311 RK1808_CLKGATE_CON(1), 0, GFLAGS),
312 GATE(0, "aclk_gic_niu", "aclk_gic_pre", CLK_IS_CRITICAL,
313 RK1808_CLKGATE_CON(1), 1, GFLAGS),
314 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IS_CRITICAL,
315 RK1808_CLKGATE_CON(1), 2, GFLAGS),
316 GATE(0, "aclk_core2gic", "aclk_gic_pre", CLK_IGNORE_UNUSED,
317 RK1808_CLKGATE_CON(1), 3, GFLAGS),
318 GATE(0, "aclk_gic2core", "aclk_gic_pre", CLK_IGNORE_UNUSED,
319 RK1808_CLKGATE_CON(1), 4, GFLAGS),
320 GATE(0, "aclk_spinlock", "aclk_gic_pre", CLK_IGNORE_UNUSED,
321 RK1808_CLKGATE_CON(1), 4, GFLAGS),
322
323 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_p, 0,
324 RK1808_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 5, DFLAGS,
325 RK1808_CLKGATE_CON(8), 8, GFLAGS),
326 COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0,
327 RK1808_CLKSEL_CON(16), 8, 4, DFLAGS,
328 RK1808_CLKGATE_CON(8), 9, GFLAGS),
329 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
330 RK1808_CLKGATE_CON(8), 12, GFLAGS),
331 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
332 RK1808_CLKGATE_CON(8), 10, GFLAGS),
333 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
334 RK1808_CLKGATE_CON(8), 13, GFLAGS),
335 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED,
336 RK1808_CLKGATE_CON(8), 11, GFLAGS),
337
338 /*
339 * Clock-Architecture Diagram 4
340 */
341 COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE,
342 RK1808_CLKSEL_CON(1), 8, 2, MFLAGS, 0, 4, DFLAGS),
343 COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE,
344 RK1808_CLKSEL_CON(1), 10, 2, MFLAGS, 4, 4, DFLAGS),
345 MUX(0, "clk_npu_pre", mux_npu_p, CLK_SET_RATE_PARENT,
346 RK1808_CLKSEL_CON(1), 15, 1, MFLAGS),
347 FACTOR(0, "clk_npu_scan", "clk_npu_pre", 0, 1, 2),
348 GATE(SCLK_NPU, "clk_npu", "clk_npu_pre", 0,
349 RK1808_CLKGATE_CON(1), 10, GFLAGS),
350
351 COMPOSITE(0, "aclk_npu_pre", mux_gpll_cpll_p, 0,
352 RK1808_CLKSEL_CON(2), 14, 1, MFLAGS, 0, 4, DFLAGS,
353 RK1808_CLKGATE_CON(1), 8, GFLAGS),
354 COMPOSITE(0, "hclk_npu_pre", mux_gpll_cpll_p, 0,
355 RK1808_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 4, DFLAGS,
356 RK1808_CLKGATE_CON(1), 9, GFLAGS),
357 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
358 RK1808_CLKGATE_CON(1), 11, GFLAGS),
359 GATE(0, "aclk_npu_niu", "aclk_npu_pre", CLK_IS_CRITICAL,
360 RK1808_CLKGATE_CON(1), 13, GFLAGS),
361 COMPOSITE_NOMUX(0, "aclk_npu2mem", "aclk_npu_pre", CLK_IGNORE_UNUSED,
362 RK1808_CLKSEL_CON(2), 4, 4, DFLAGS,
363 RK1808_CLKGATE_CON(1), 15, GFLAGS),
364 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
365 RK1808_CLKGATE_CON(1), 12, GFLAGS),
366 GATE(0, "hclk_npu_niu", "hclk_npu_pre", CLK_IS_CRITICAL,
367 RK1808_CLKGATE_CON(1), 14, GFLAGS),
368
369 GATE(SCLK_PVTM_NPU, "clk_pvtm_npu", "xin24m", 0,
370 RK1808_CLKGATE_CON(0), 15, GFLAGS),
371
372 COMPOSITE(ACLK_IMEM_PRE, "aclk_imem_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL,
373 RK1808_CLKSEL_CON(17), 7, 1, MFLAGS, 0, 5, DFLAGS,
374 RK1808_CLKGATE_CON(7), 0, GFLAGS),
375 GATE(ACLK_IMEM0, "aclk_imem0", "aclk_imem_pre", CLK_IGNORE_UNUSED,
376 RK1808_CLKGATE_CON(7), 6, GFLAGS),
377 GATE(0, "aclk_imem0_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
378 RK1808_CLKGATE_CON(7), 10, GFLAGS),
379 GATE(ACLK_IMEM1, "aclk_imem1", "aclk_imem_pre", CLK_IGNORE_UNUSED,
380 RK1808_CLKGATE_CON(7), 7, GFLAGS),
381 GATE(0, "aclk_imem1_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
382 RK1808_CLKGATE_CON(7), 11, GFLAGS),
383 GATE(ACLK_IMEM2, "aclk_imem2", "aclk_imem_pre", CLK_IGNORE_UNUSED,
384 RK1808_CLKGATE_CON(7), 8, GFLAGS),
385 GATE(0, "aclk_imem2_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
386 RK1808_CLKGATE_CON(7), 12, GFLAGS),
387 GATE(ACLK_IMEM3, "aclk_imem3", "aclk_imem_pre", CLK_IGNORE_UNUSED,
388 RK1808_CLKGATE_CON(7), 9, GFLAGS),
389 GATE(0, "aclk_imem3_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
390 RK1808_CLKGATE_CON(7), 13, GFLAGS),
391
392 COMPOSITE(HSCLK_IMEM, "hsclk_imem", mux_gpll_cpll_p, CLK_IS_CRITICAL,
393 RK1808_CLKSEL_CON(17), 15, 1, MFLAGS, 8, 5, DFLAGS,
394 RK1808_CLKGATE_CON(7), 5, GFLAGS),
395
396 /*
397 * Clock-Architecture Diagram 5
398 */
399 GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED,
400 RK1808_CLKGATE_CON(2), 0, GFLAGS),
401
402 GATE(0, "clk_ddr_mon", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
403 RK1808_CLKGATE_CON(2), 11, GFLAGS),
404 GATE(0, "aclk_split", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
405 RK1808_CLKGATE_CON(2), 15, GFLAGS),
406 GATE(0, "clk_ddr_msch", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
407 RK1808_CLKGATE_CON(2), 8, GFLAGS),
408 GATE(0, "clk_ddrdfi_ctl", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
409 RK1808_CLKGATE_CON(2), 3, GFLAGS),
410 GATE(0, "clk_stdby", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
411 RK1808_CLKGATE_CON(2), 13, GFLAGS),
412 GATE(0, "aclk_ddrc", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
413 RK1808_CLKGATE_CON(2), 5, GFLAGS),
414 GATE(0, "clk_core_ddrc", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
415 RK1808_CLKGATE_CON(2), 6, GFLAGS),
416
417 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
418 RK1808_CLKGATE_CON(8), 5, GFLAGS),
419 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
420 RK1808_CLKGATE_CON(8), 6, GFLAGS),
421
422 COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddr_p, CLK_IGNORE_UNUSED,
423 RK1808_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS),
424 FACTOR(0, "clk_ddrphy1x_out", "sclk_ddrc", CLK_IGNORE_UNUSED, 1, 1),
425
426 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IS_CRITICAL,
427 RK1808_CLKSEL_CON(3), 8, 5, DFLAGS,
428 RK1808_CLKGATE_CON(2), 1, GFLAGS),
429 GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
430 RK1808_CLKGATE_CON(2), 10, GFLAGS),
431 GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED,
432 RK1808_CLKGATE_CON(2), 7, GFLAGS),
433 GATE(PCLK_MSCH, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
434 RK1808_CLKGATE_CON(2), 9, GFLAGS),
435 GATE(PCLK_STDBY, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
436 RK1808_CLKGATE_CON(2), 12, GFLAGS),
437 GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IS_CRITICAL,
438 RK1808_CLKGATE_CON(2), 14, GFLAGS),
439 GATE(0, "pclk_ddrdfi_ctl", "pclk_ddr", CLK_IGNORE_UNUSED,
440 RK1808_CLKGATE_CON(2), 2, GFLAGS),
441
442 /*
443 * Clock-Architecture Diagram 6
444 */
445
446 COMPOSITE(HSCLK_VIO, "hsclk_vio", mux_gpll_cpll_p, 0,
447 RK1808_CLKSEL_CON(4), 7, 1, MFLAGS, 0, 5, DFLAGS,
448 RK1808_CLKGATE_CON(3), 0, GFLAGS),
449 COMPOSITE_NOMUX(LSCLK_VIO, "lsclk_vio", "hsclk_vio", 0,
450 RK1808_CLKSEL_CON(4), 8, 4, DFLAGS,
451 RK1808_CLKGATE_CON(3), 12, GFLAGS),
452 GATE(0, "hsclk_vio_niu", "hsclk_vio", CLK_IGNORE_UNUSED,
453 RK1808_CLKGATE_CON(4), 0, GFLAGS),
454 GATE(0, "lsclk_vio_niu", "lsclk_vio", CLK_IGNORE_UNUSED,
455 RK1808_CLKGATE_CON(4), 1, GFLAGS),
456 GATE(ACLK_VOPRAW, "aclk_vopraw", "hsclk_vio", 0,
457 RK1808_CLKGATE_CON(4), 2, GFLAGS),
458 GATE(HCLK_VOPRAW, "hclk_vopraw", "lsclk_vio", 0,
459 RK1808_CLKGATE_CON(4), 3, GFLAGS),
460 GATE(ACLK_VOPLITE, "aclk_voplite", "hsclk_vio", 0,
461 RK1808_CLKGATE_CON(4), 4, GFLAGS),
462 GATE(HCLK_VOPLITE, "hclk_voplite", "lsclk_vio", 0,
463 RK1808_CLKGATE_CON(4), 5, GFLAGS),
464 GATE(PCLK_DSI_TX, "pclk_dsi_tx", "lsclk_vio", 0,
465 RK1808_CLKGATE_CON(4), 6, GFLAGS),
466 GATE(PCLK_CSI_TX, "pclk_csi_tx", "lsclk_vio", 0,
467 RK1808_CLKGATE_CON(4), 7, GFLAGS),
468 GATE(ACLK_RGA, "aclk_rga", "hsclk_vio", 0,
469 RK1808_CLKGATE_CON(4), 8, GFLAGS),
470 GATE(HCLK_RGA, "hclk_rga", "lsclk_vio", 0,
471 RK1808_CLKGATE_CON(4), 9, GFLAGS),
472 GATE(ACLK_ISP, "aclk_isp", "hsclk_vio", 0,
473 RK1808_CLKGATE_CON(4), 13, GFLAGS),
474 GATE(HCLK_ISP, "hclk_isp", "lsclk_vio", 0,
475 RK1808_CLKGATE_CON(4), 14, GFLAGS),
476 GATE(ACLK_CIF, "aclk_cif", "hsclk_vio", 0,
477 RK1808_CLKGATE_CON(4), 10, GFLAGS),
478 GATE(HCLK_CIF, "hclk_cif", "lsclk_vio", 0,
479 RK1808_CLKGATE_CON(4), 11, GFLAGS),
480 GATE(PCLK_CSI2HOST, "pclk_csi2host", "lsclk_vio", 0,
481 RK1808_CLKGATE_CON(4), 12, GFLAGS),
482
483 COMPOSITE(0, "dclk_vopraw_src", mux_cpll_gpll_npll_p, 0,
484 RK1808_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 8, DFLAGS,
485 RK1808_CLKGATE_CON(3), 1, GFLAGS),
486 COMPOSITE_FRACMUX(0, "dclk_vopraw_frac", "dclk_vopraw_src", CLK_SET_RATE_PARENT,
487 RK1808_CLKSEL_CON(6), 0,
488 RK1808_CLKGATE_CON(3), 2, GFLAGS,
489 &rk1808_dclk_vopraw_fracmux),
490 GATE(DCLK_VOPRAW, "dclk_vopraw", "dclk_vopraw_mux", 0,
491 RK1808_CLKGATE_CON(3), 3, GFLAGS),
492
493 COMPOSITE(0, "dclk_voplite_src", mux_cpll_gpll_npll_p, 0,
494 RK1808_CLKSEL_CON(7), 10, 2, MFLAGS, 0, 8, DFLAGS,
495 RK1808_CLKGATE_CON(3), 4, GFLAGS),
496 COMPOSITE_FRACMUX(0, "dclk_voplite_frac", "dclk_voplite_src", CLK_SET_RATE_PARENT,
497 RK1808_CLKSEL_CON(8), 0,
498 RK1808_CLKGATE_CON(3), 5, GFLAGS,
499 &rk1808_dclk_voplite_fracmux),
500 GATE(DCLK_VOPLITE, "dclk_voplite", "dclk_voplite_mux", 0,
501 RK1808_CLKGATE_CON(3), 6, GFLAGS),
502
503 COMPOSITE_NOMUX(SCLK_TXESC, "clk_txesc", "gpll", 0,
504 RK1808_CLKSEL_CON(9), 0, 12, DFLAGS,
505 RK1808_CLKGATE_CON(3), 7, GFLAGS),
506
507 COMPOSITE(SCLK_RGA, "clk_rga", mux_gpll_cpll_npll_p, 0,
508 RK1808_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
509 RK1808_CLKGATE_CON(3), 8, GFLAGS),
510
511 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
512 RK1808_CLKSEL_CON(10), 14, 2, MFLAGS, 8, 5, DFLAGS,
513 RK1808_CLKGATE_CON(3), 10, GFLAGS),
514
515 COMPOSITE(DCLK_CIF, "dclk_cif", mux_cpll_gpll_npll_p, 0,
516 RK1808_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
517 RK1808_CLKGATE_CON(3), 11, GFLAGS),
518
519 COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_24m_npll_gpll_usb480m_p, 0,
520 RK1808_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
521 RK1808_CLKGATE_CON(3), 9, GFLAGS),
522
523 /*
524 * Clock-Architecture Diagram 7
525 */
526
527 /* PD_PCIE */
528 COMPOSITE_NODIV(0, "clk_pcie_src", mux_gpll_cpll_p, 0,
529 RK1808_CLKSEL_CON(12), 15, 1, MFLAGS,
530 RK1808_CLKGATE_CON(5), 0, GFLAGS),
531 DIV(HSCLK_PCIE, "hsclk_pcie", "clk_pcie_src", 0,
532 RK1808_CLKSEL_CON(12), 0, 5, DFLAGS),
533 DIV(LSCLK_PCIE, "lsclk_pcie", "clk_pcie_src", 0,
534 RK1808_CLKSEL_CON(12), 8, 5, DFLAGS),
535 GATE(0, "hsclk_pcie_niu", "hsclk_pcie", CLK_IGNORE_UNUSED,
536 RK1808_CLKGATE_CON(6), 0, GFLAGS),
537 GATE(0, "lsclk_pcie_niu", "lsclk_pcie", CLK_IGNORE_UNUSED,
538 RK1808_CLKGATE_CON(6), 1, GFLAGS),
539 GATE(0, "pclk_pcie_grf", "lsclk_pcie", CLK_IGNORE_UNUSED,
540 RK1808_CLKGATE_CON(6), 5, GFLAGS),
541 GATE(ACLK_USB3OTG, "aclk_usb3otg", "hsclk_pcie", 0,
542 RK1808_CLKGATE_CON(6), 6, GFLAGS),
543 GATE(HCLK_HOST, "hclk_host", "lsclk_pcie", 0,
544 RK1808_CLKGATE_CON(6), 7, GFLAGS),
545 GATE(HCLK_HOST_ARB, "hclk_host_arb", "lsclk_pcie", CLK_IGNORE_UNUSED,
546 RK1808_CLKGATE_CON(6), 8, GFLAGS),
547
548 COMPOSITE(ACLK_PCIE, "aclk_pcie", mux_gpll_cpll_p, 0,
549 RK1808_CLKSEL_CON(15), 8, 1, MFLAGS, 0, 4, DFLAGS,
550 RK1808_CLKGATE_CON(5), 5, GFLAGS),
551 DIV(0, "pclk_pcie_pre", "aclk_pcie", 0,
552 RK1808_CLKSEL_CON(15), 4, 4, DFLAGS),
553 GATE(0, "aclk_pcie_niu", "aclk_pcie", CLK_IGNORE_UNUSED,
554 RK1808_CLKGATE_CON(6), 10, GFLAGS),
555 GATE(ACLK_PCIE_MST, "aclk_pcie_mst", "aclk_pcie", CLK_IGNORE_UNUSED,
556 RK1808_CLKGATE_CON(6), 2, GFLAGS),
557 GATE(ACLK_PCIE_SLV, "aclk_pcie_slv", "aclk_pcie", CLK_IGNORE_UNUSED,
558 RK1808_CLKGATE_CON(6), 3, GFLAGS),
559 GATE(0, "pclk_pcie_niu", "pclk_pcie_pre", CLK_IGNORE_UNUSED,
560 RK1808_CLKGATE_CON(6), 11, GFLAGS),
561 GATE(0, "pclk_pcie_dbi", "pclk_pcie_pre", CLK_IGNORE_UNUSED,
562 RK1808_CLKGATE_CON(6), 4, GFLAGS),
563 GATE(PCLK_PCIE, "pclk_pcie", "pclk_pcie_pre", 0,
564 RK1808_CLKGATE_CON(6), 9, GFLAGS),
565
566 COMPOSITE(0, "clk_pcie_aux_src", mux_cpll_gpll_npll_p, 0,
567 RK1808_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
568 RK1808_CLKGATE_CON(5), 3, GFLAGS),
569 COMPOSITE_NODIV(SCLK_PCIE_AUX, "clk_pcie_aux", mux_pcie_aux_p, CLK_SET_RATE_PARENT,
570 RK1808_CLKSEL_CON(14), 12, 1, MFLAGS,
571 RK1808_CLKGATE_CON(5), 4, GFLAGS),
572
573 GATE(SCLK_USB3_OTG0_REF, "clk_usb3_otg0_ref", "xin24m", 0,
574 RK1808_CLKGATE_CON(5), 1, GFLAGS),
575
576 COMPOSITE(SCLK_USB3_OTG0_SUSPEND, "clk_usb3_otg0_suspend", mux_usb3_otg0_suspend_p, 0,
577 RK1808_CLKSEL_CON(13), 12, 1, MFLAGS, 0, 10, DFLAGS,
578 RK1808_CLKGATE_CON(5), 2, GFLAGS),
579
580 /*
581 * Clock-Architecture Diagram 8
582 */
583
584 /* PD_PHP */
585
586 COMPOSITE_NODIV(0, "clk_peri_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
587 RK1808_CLKSEL_CON(19), 15, 1, MFLAGS,
588 RK1808_CLKGATE_CON(8), 0, GFLAGS),
589 COMPOSITE_NOMUX(MSCLK_PERI, "msclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
590 RK1808_CLKSEL_CON(19), 0, 5, DFLAGS,
591 RK1808_CLKGATE_CON(8), 1, GFLAGS),
592 COMPOSITE_NOMUX(LSCLK_PERI, "lsclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
593 RK1808_CLKSEL_CON(19), 8, 5, DFLAGS,
594 RK1808_CLKGATE_CON(8), 2, GFLAGS),
595 GATE(0, "msclk_peri_niu", "msclk_peri", CLK_IS_CRITICAL,
596 RK1808_CLKGATE_CON(8), 3, GFLAGS),
597 GATE(0, "lsclk_peri_niu", "lsclk_peri", CLK_IS_CRITICAL,
598 RK1808_CLKGATE_CON(8), 4, GFLAGS),
599
600 /* PD_MMC */
601
602 GATE(0, "hclk_mmc_sfc", "msclk_peri", CLK_IGNORE_UNUSED,
603 RK1808_CLKGATE_CON(9), 0, GFLAGS),
604 GATE(0, "hclk_mmc_sfc_niu", "hclk_mmc_sfc", CLK_IGNORE_UNUSED,
605 RK1808_CLKGATE_CON(9), 11, GFLAGS),
606 GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_sfc", 0,
607 RK1808_CLKGATE_CON(9), 12, GFLAGS),
608 GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_sfc", 0,
609 RK1808_CLKGATE_CON(9), 13, GFLAGS),
610
611 COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
612 RK1808_CLKSEL_CON(22), 14, 2, MFLAGS, 0, 8, DFLAGS,
613 RK1808_CLKGATE_CON(9), 1, GFLAGS),
614 COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
615 mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
616 RK1808_CLKSEL_CON(22), 14, 2, MFLAGS,
617 RK1808_CLKSEL_CON(23), 0, 8, DFLAGS,
618 RK1808_CLKGATE_CON(9), 2, GFLAGS),
619 COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
620 RK1808_CLKSEL_CON(23), 15, 1, MFLAGS,
621 RK1808_CLKGATE_CON(9), 3, GFLAGS),
622
623 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK1808_SDIO_CON0, 1),
624 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK1808_SDIO_CON1, 1),
625
626 COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div",
627 mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
628 RK1808_CLKSEL_CON(24), 14, 2, MFLAGS, 0, 8, DFLAGS,
629 RK1808_CLKGATE_CON(9), 4, GFLAGS),
630 COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
631 RK1808_CLKSEL_CON(24), 14, 2, MFLAGS,
632 RK1808_CLKSEL_CON(25), 0, 8, DFLAGS,
633 RK1808_CLKGATE_CON(9), 5, GFLAGS),
634 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
635 RK1808_CLKSEL_CON(25), 15, 1, MFLAGS,
636 RK1808_CLKGATE_CON(9), 6, GFLAGS),
637 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK1808_EMMC_CON0, 1),
638 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RK1808_EMMC_CON1, 1),
639
640 COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
641 RK1808_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
642 RK1808_CLKGATE_CON(9), 7, GFLAGS),
643 COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50",
644 mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
645 RK1808_CLKSEL_CON(20), 14, 2, MFLAGS,
646 RK1808_CLKSEL_CON(21), 0, 8, DFLAGS,
647 RK1808_CLKGATE_CON(9), 8, GFLAGS),
648 COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
649 RK1808_CLKSEL_CON(21), 15, 1, MFLAGS,
650 RK1808_CLKGATE_CON(9), 9, GFLAGS),
651 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK1808_SDMMC_CON0, 1),
652 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK1808_SDMMC_CON1, 1),
653
654 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
655 RK1808_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 7, DFLAGS,
656 RK1808_CLKGATE_CON(9), 10, GFLAGS),
657
658 /* PD_MAC */
659
660 GATE(0, "pclk_sd_gmac", "lsclk_peri", CLK_IGNORE_UNUSED,
661 RK1808_CLKGATE_CON(10), 2, GFLAGS),
662 GATE(0, "aclk_sd_gmac", "msclk_peri", CLK_IGNORE_UNUSED,
663 RK1808_CLKGATE_CON(10), 0, GFLAGS),
664 GATE(0, "hclk_sd_gmac", "msclk_peri", CLK_IGNORE_UNUSED,
665 RK1808_CLKGATE_CON(10), 1, GFLAGS),
666 GATE(0, "pclk_gmac_niu", "pclk_sd_gmac", CLK_IGNORE_UNUSED,
667 RK1808_CLKGATE_CON(10), 10, GFLAGS),
668 GATE(PCLK_GMAC, "pclk_gmac", "pclk_sd_gmac", 0,
669 RK1808_CLKGATE_CON(10), 12, GFLAGS),
670 GATE(0, "aclk_gmac_niu", "aclk_sd_gmac", CLK_IGNORE_UNUSED,
671 RK1808_CLKGATE_CON(10), 8, GFLAGS),
672 GATE(ACLK_GMAC, "aclk_gmac", "aclk_sd_gmac", 0,
673 RK1808_CLKGATE_CON(10), 11, GFLAGS),
674 GATE(0, "hclk_gmac_niu", "hclk_sd_gmac", CLK_IGNORE_UNUSED,
675 RK1808_CLKGATE_CON(10), 9, GFLAGS),
676 GATE(HCLK_SDIO, "hclk_sdio", "hclk_sd_gmac", 0,
677 RK1808_CLKGATE_CON(10), 13, GFLAGS),
678 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd_gmac", 0,
679 RK1808_CLKGATE_CON(10), 14, GFLAGS),
680
681 COMPOSITE(SCLK_GMAC_OUT, "clk_gmac_out", mux_cpll_npll_ppll_p, 0,
682 RK1808_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
683 RK1808_CLKGATE_CON(10), 15, GFLAGS),
684
685 COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_cpll_npll_ppll_p, 0,
686 RK1808_CLKSEL_CON(26), 14, 2, MFLAGS, 8, 5, DFLAGS,
687 RK1808_CLKGATE_CON(10), 3, GFLAGS),
688 MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
689 RK1808_CLKSEL_CON(27), 0, 1, MFLAGS),
690 GATE(SCLK_GMAC_REF, "clk_gmac_ref", "clk_gmac", 0,
691 RK1808_CLKGATE_CON(10), 4, GFLAGS),
692 GATE(0, "clk_gmac_tx_src", "clk_gmac", 0,
693 RK1808_CLKGATE_CON(10), 7, GFLAGS),
694 GATE(0, "clk_gmac_rx_src", "clk_gmac", 0,
695 RK1808_CLKGATE_CON(10), 6, GFLAGS),
696 GATE(SCLK_GMAC_REFOUT, "clk_gmac_refout", "clk_gmac", 0,
697 RK1808_CLKGATE_CON(10), 5, GFLAGS),
698 FACTOR(0, "clk_gmac_tx_div5", "clk_gmac_tx_src", 0, 1, 5),
699 FACTOR(0, "clk_gmac_tx_div50", "clk_gmac_tx_src", 0, 1, 50),
700 FACTOR(0, "clk_gmac_rx_div2", "clk_gmac_rx_src", 0, 1, 2),
701 FACTOR(0, "clk_gmac_rx_div20", "clk_gmac_rx_src", 0, 1, 20),
702 MUX(SCLK_GMAC_RGMII_SPEED, "clk_gmac_rgmii_speed", mux_gmac_rgmii_speed_p, CLK_SET_RATE_PARENT,
703 RK1808_CLKSEL_CON(27), 2, 2, MFLAGS),
704 MUX(SCLK_GMAC_RMII_SPEED, "clk_gmac_rmii_speed", mux_gmac_rmii_speed_p, CLK_SET_RATE_PARENT,
705 RK1808_CLKSEL_CON(27), 1, 1, MFLAGS),
706 MUX(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", mux_gmac_rx_tx_p, CLK_SET_RATE_PARENT,
707 RK1808_CLKSEL_CON(27), 4, 1, MFLAGS),
708
709 /*
710 * Clock-Architecture Diagram 9
711 */
712
713 /* PD_BUS */
714
715 COMPOSITE_NODIV(0, "clk_bus_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
716 RK1808_CLKSEL_CON(27), 15, 1, MFLAGS,
717 RK1808_CLKGATE_CON(11), 0, GFLAGS),
718 COMPOSITE_NOMUX(HSCLK_BUS_PRE, "hsclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
719 RK1808_CLKSEL_CON(27), 8, 5, DFLAGS,
720 RK1808_CLKGATE_CON(11), 1, GFLAGS),
721 COMPOSITE_NOMUX(MSCLK_BUS_PRE, "msclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
722 RK1808_CLKSEL_CON(28), 0, 5, DFLAGS,
723 RK1808_CLKGATE_CON(11), 2, GFLAGS),
724 COMPOSITE_NOMUX(LSCLK_BUS_PRE, "lsclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
725 RK1808_CLKSEL_CON(28), 8, 5, DFLAGS,
726 RK1808_CLKGATE_CON(11), 3, GFLAGS),
727 GATE(0, "hsclk_bus_niu", "hsclk_bus_pre", CLK_IS_CRITICAL,
728 RK1808_CLKGATE_CON(15), 0, GFLAGS),
729 GATE(0, "msclk_bus_niu", "msclk_bus_pre", CLK_IS_CRITICAL,
730 RK1808_CLKGATE_CON(15), 1, GFLAGS),
731 GATE(0, "msclk_sub", "msclk_bus_pre", CLK_IGNORE_UNUSED,
732 RK1808_CLKGATE_CON(15), 2, GFLAGS),
733 GATE(ACLK_DMAC, "aclk_dmac", "msclk_bus_pre", CLK_IGNORE_UNUSED,
734 RK1808_CLKGATE_CON(14), 15, GFLAGS),
735 GATE(HCLK_ROM, "hclk_rom", "msclk_bus_pre", CLK_IGNORE_UNUSED,
736 RK1808_CLKGATE_CON(15), 4, GFLAGS),
737 GATE(ACLK_CRYPTO, "aclk_crypto", "msclk_bus_pre", 0,
738 RK1808_CLKGATE_CON(15), 5, GFLAGS),
739 GATE(HCLK_CRYPTO, "hclk_crypto", "msclk_bus_pre", 0,
740 RK1808_CLKGATE_CON(15), 6, GFLAGS),
741 GATE(ACLK_DCF, "aclk_dcf", "msclk_bus_pre", 0,
742 RK1808_CLKGATE_CON(15), 7, GFLAGS),
743 GATE(0, "lsclk_bus_niu", "lsclk_bus_pre", CLK_IS_CRITICAL,
744 RK1808_CLKGATE_CON(15), 3, GFLAGS),
745 GATE(PCLK_DCF, "pclk_dcf", "lsclk_bus_pre", 0,
746 RK1808_CLKGATE_CON(15), 8, GFLAGS),
747 GATE(PCLK_UART1, "pclk_uart1", "lsclk_bus_pre", 0,
748 RK1808_CLKGATE_CON(15), 9, GFLAGS),
749 GATE(PCLK_UART2, "pclk_uart2", "lsclk_bus_pre", 0,
750 RK1808_CLKGATE_CON(15), 10, GFLAGS),
751 GATE(PCLK_UART3, "pclk_uart3", "lsclk_bus_pre", 0,
752 RK1808_CLKGATE_CON(15), 11, GFLAGS),
753 GATE(PCLK_UART4, "pclk_uart4", "lsclk_bus_pre", 0,
754 RK1808_CLKGATE_CON(15), 12, GFLAGS),
755 GATE(PCLK_UART5, "pclk_uart5", "lsclk_bus_pre", 0,
756 RK1808_CLKGATE_CON(15), 13, GFLAGS),
757 GATE(PCLK_UART6, "pclk_uart6", "lsclk_bus_pre", 0,
758 RK1808_CLKGATE_CON(15), 14, GFLAGS),
759 GATE(PCLK_UART7, "pclk_uart7", "lsclk_bus_pre", 0,
760 RK1808_CLKGATE_CON(15), 15, GFLAGS),
761 GATE(PCLK_I2C1, "pclk_i2c1", "lsclk_bus_pre", 0,
762 RK1808_CLKGATE_CON(16), 0, GFLAGS),
763 GATE(PCLK_I2C2, "pclk_i2c2", "lsclk_bus_pre", 0,
764 RK1808_CLKGATE_CON(16), 1, GFLAGS),
765 GATE(PCLK_I2C3, "pclk_i2c3", "lsclk_bus_pre", 0,
766 RK1808_CLKGATE_CON(16), 2, GFLAGS),
767 GATE(PCLK_I2C4, "pclk_i2c4", "lsclk_bus_pre", 0,
768 RK1808_CLKGATE_CON(17), 4, GFLAGS),
769 GATE(PCLK_I2C5, "pclk_i2c5", "lsclk_bus_pre", 0,
770 RK1808_CLKGATE_CON(17), 5, GFLAGS),
771 GATE(PCLK_SPI0, "pclk_spi0", "lsclk_bus_pre", 0,
772 RK1808_CLKGATE_CON(16), 3, GFLAGS),
773 GATE(PCLK_SPI1, "pclk_spi1", "lsclk_bus_pre", 0,
774 RK1808_CLKGATE_CON(16), 4, GFLAGS),
775 GATE(PCLK_SPI2, "pclk_spi2", "lsclk_bus_pre", 0,
776 RK1808_CLKGATE_CON(16), 5, GFLAGS),
777 GATE(PCLK_TSADC, "pclk_tsadc", "lsclk_bus_pre", 0,
778 RK1808_CLKGATE_CON(16), 9, GFLAGS),
779 GATE(PCLK_SARADC, "pclk_saradc", "lsclk_bus_pre", 0,
780 RK1808_CLKGATE_CON(16), 10, GFLAGS),
781 GATE(PCLK_EFUSE, "pclk_efuse", "lsclk_bus_pre", 0,
782 RK1808_CLKGATE_CON(16), 11, GFLAGS),
783 GATE(PCLK_GPIO1, "pclk_gpio1", "lsclk_bus_pre", 0,
784 RK1808_CLKGATE_CON(16), 12, GFLAGS),
785 GATE(PCLK_GPIO2, "pclk_gpio2", "lsclk_bus_pre", 0,
786 RK1808_CLKGATE_CON(16), 13, GFLAGS),
787 GATE(PCLK_GPIO3, "pclk_gpio3", "lsclk_bus_pre", 0,
788 RK1808_CLKGATE_CON(16), 14, GFLAGS),
789 GATE(PCLK_GPIO4, "pclk_gpio4", "lsclk_bus_pre", 0,
790 RK1808_CLKGATE_CON(16), 15, GFLAGS),
791 GATE(PCLK_PWM0, "pclk_pwm0", "lsclk_bus_pre", 0,
792 RK1808_CLKGATE_CON(16), 6, GFLAGS),
793 GATE(PCLK_PWM1, "pclk_pwm1", "lsclk_bus_pre", 0,
794 RK1808_CLKGATE_CON(16), 7, GFLAGS),
795 GATE(PCLK_PWM2, "pclk_pwm2", "lsclk_bus_pre", 0,
796 RK1808_CLKGATE_CON(16), 8, GFLAGS),
797 GATE(PCLK_TIMER, "pclk_timer", "lsclk_bus_pre", 0,
798 RK1808_CLKGATE_CON(17), 0, GFLAGS),
799 GATE(PCLK_WDT, "pclk_wdt", "lsclk_bus_pre", 0,
800 RK1808_CLKGATE_CON(17), 1, GFLAGS),
801 GATE(0, "pclk_grf", "lsclk_bus_pre", CLK_IGNORE_UNUSED,
802 RK1808_CLKGATE_CON(17), 2, GFLAGS),
803 GATE(0, "pclk_sgrf", "lsclk_bus_pre", CLK_IGNORE_UNUSED,
804 RK1808_CLKGATE_CON(17), 3, GFLAGS),
805 GATE(0, "hclk_audio_pre", "msclk_bus_pre", 0,
806 RK1808_CLKGATE_CON(17), 8, GFLAGS),
807 GATE(0, "pclk_top_pre", "lsclk_bus_pre", CLK_IS_CRITICAL,
808 RK1808_CLKGATE_CON(11), 4, GFLAGS),
809
810 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_p, 0,
811 RK1808_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 5, DFLAGS,
812 RK1808_CLKGATE_CON(11), 5, GFLAGS),
813 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_p, 0,
814 RK1808_CLKSEL_CON(29), 15, 1, MFLAGS, 8, 5, DFLAGS,
815 RK1808_CLKGATE_CON(11), 6, GFLAGS),
816
817 COMPOSITE(0, "clk_uart1_src", mux_gpll_usb480m_cpll_npll_p, 0,
818 RK1808_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 7, DFLAGS,
819 RK1808_CLKGATE_CON(11), 8, GFLAGS),
820 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0,
821 RK1808_CLKSEL_CON(39), 0, 7, DFLAGS,
822 RK1808_CLKGATE_CON(11), 9, GFLAGS),
823 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
824 RK1808_CLKSEL_CON(40), 0,
825 RK1808_CLKGATE_CON(11), 10, GFLAGS,
826 &rk1808_uart1_fracmux),
827 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
828 RK1808_CLKGATE_CON(11), 11, GFLAGS),
829
830 COMPOSITE(0, "clk_uart2_src", mux_gpll_usb480m_cpll_npll_p, 0,
831 RK1808_CLKSEL_CON(41), 14, 2, MFLAGS, 0, 7, DFLAGS,
832 RK1808_CLKGATE_CON(11), 12, GFLAGS),
833 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0,
834 RK1808_CLKSEL_CON(42), 0, 7, DFLAGS,
835 RK1808_CLKGATE_CON(11), 13, GFLAGS),
836 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
837 RK1808_CLKSEL_CON(43), 0,
838 RK1808_CLKGATE_CON(11), 14, GFLAGS,
839 &rk1808_uart2_fracmux),
840 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", 0,
841 RK1808_CLKGATE_CON(11), 15, GFLAGS),
842
843 COMPOSITE(0, "clk_uart3_src", mux_gpll_usb480m_cpll_npll_p, 0,
844 RK1808_CLKSEL_CON(44), 14, 2, MFLAGS, 0, 7, DFLAGS,
845 RK1808_CLKGATE_CON(12), 0, GFLAGS),
846 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0,
847 RK1808_CLKSEL_CON(45), 0, 7, DFLAGS,
848 RK1808_CLKGATE_CON(12), 1, GFLAGS),
849 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
850 RK1808_CLKSEL_CON(46), 0,
851 RK1808_CLKGATE_CON(12), 2, GFLAGS,
852 &rk1808_uart3_fracmux),
853 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
854 RK1808_CLKGATE_CON(12), 3, GFLAGS),
855
856 COMPOSITE(0, "clk_uart4_src", mux_gpll_usb480m_cpll_npll_p, 0,
857 RK1808_CLKSEL_CON(47), 14, 2, MFLAGS, 0, 7, DFLAGS,
858 RK1808_CLKGATE_CON(12), 4, GFLAGS),
859 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0,
860 RK1808_CLKSEL_CON(48), 0, 7, DFLAGS,
861 RK1808_CLKGATE_CON(12), 5, GFLAGS),
862 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
863 RK1808_CLKSEL_CON(49), 0,
864 RK1808_CLKGATE_CON(12), 6, GFLAGS,
865 &rk1808_uart4_fracmux),
866 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
867 RK1808_CLKGATE_CON(12), 7, GFLAGS),
868
869 COMPOSITE(0, "clk_uart5_src", mux_gpll_usb480m_cpll_npll_p, 0,
870 RK1808_CLKSEL_CON(50), 14, 2, MFLAGS, 0, 7, DFLAGS,
871 RK1808_CLKGATE_CON(12), 8, GFLAGS),
872 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0,
873 RK1808_CLKSEL_CON(51), 0, 7, DFLAGS,
874 RK1808_CLKGATE_CON(12), 9, GFLAGS),
875 COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
876 RK1808_CLKSEL_CON(52), 0,
877 RK1808_CLKGATE_CON(12), 10, GFLAGS,
878 &rk1808_uart5_fracmux),
879 GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", 0,
880 RK1808_CLKGATE_CON(12), 11, GFLAGS),
881
882 COMPOSITE(0, "clk_uart6_src", mux_gpll_usb480m_cpll_npll_p, 0,
883 RK1808_CLKSEL_CON(53), 14, 2, MFLAGS, 0, 7, DFLAGS,
884 RK1808_CLKGATE_CON(12), 12, GFLAGS),
885 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart6_np5", "clk_uart6_src", 0,
886 RK1808_CLKSEL_CON(54), 0, 7, DFLAGS,
887 RK1808_CLKGATE_CON(12), 13, GFLAGS),
888 COMPOSITE_FRACMUX(0, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
889 RK1808_CLKSEL_CON(55), 0,
890 RK1808_CLKGATE_CON(12), 14, GFLAGS,
891 &rk1808_uart6_fracmux),
892 GATE(SCLK_UART6, "clk_uart6", "clk_uart6_mux", 0,
893 RK1808_CLKGATE_CON(12), 15, GFLAGS),
894
895 COMPOSITE(0, "clk_uart7_src", mux_gpll_usb480m_cpll_npll_p, 0,
896 RK1808_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 7, DFLAGS,
897 RK1808_CLKGATE_CON(13), 0, GFLAGS),
898 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart7_np5", "clk_uart7_src", 0,
899 RK1808_CLKSEL_CON(57), 0, 7, DFLAGS,
900 RK1808_CLKGATE_CON(13), 1, GFLAGS),
901 COMPOSITE_FRACMUX(0, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
902 RK1808_CLKSEL_CON(58), 0,
903 RK1808_CLKGATE_CON(13), 2, GFLAGS,
904 &rk1808_uart7_fracmux),
905 GATE(SCLK_UART7, "clk_uart7", "clk_uart7_mux", 0,
906 RK1808_CLKGATE_CON(13), 3, GFLAGS),
907
908 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
909 RK1808_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
910 RK1808_CLKGATE_CON(13), 4, GFLAGS),
911 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
912 RK1808_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
913 RK1808_CLKGATE_CON(13), 5, GFLAGS),
914 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
915 RK1808_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
916 RK1808_CLKGATE_CON(13), 6, GFLAGS),
917 COMPOSITE(SCLK_I2C4, "clk_i2c4", mux_gpll_xin24m_p, 0,
918 RK1808_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 7, DFLAGS,
919 RK1808_CLKGATE_CON(14), 6, GFLAGS),
920 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_gpll_xin24m_p, 0,
921 RK1808_CLKSEL_CON(71), 15, 1, MFLAGS, 8, 7, DFLAGS,
922 RK1808_CLKGATE_CON(14), 7, GFLAGS),
923
924 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
925 RK1808_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
926 RK1808_CLKGATE_CON(13), 7, GFLAGS),
927 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
928 RK1808_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
929 RK1808_CLKGATE_CON(13), 8, GFLAGS),
930 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_gpll_xin24m_p, 0,
931 RK1808_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
932 RK1808_CLKGATE_CON(13), 9, GFLAGS),
933
934 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
935 RK1808_CLKSEL_CON(62), 0, 11, DFLAGS,
936 RK1808_CLKGATE_CON(13), 13, GFLAGS),
937 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
938 RK1808_CLKSEL_CON(63), 0, 11, DFLAGS,
939 RK1808_CLKGATE_CON(13), 14, GFLAGS),
940
941 COMPOSITE(SCLK_EFUSE_S, "clk_efuse_s", mux_gpll_cpll_xin24m_p, 0,
942 RK1808_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 6, DFLAGS,
943 RK1808_CLKGATE_CON(14), 0, GFLAGS),
944 COMPOSITE(SCLK_EFUSE_NS, "clk_efuse_ns", mux_gpll_cpll_xin24m_p, 0,
945 RK1808_CLKSEL_CON(64), 14, 2, MFLAGS, 8, 6, DFLAGS,
946 RK1808_CLKGATE_CON(14), 1, GFLAGS),
947
948 COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
949 RK1808_CLKSEL_CON(65), 15, 1, MFLAGS, 0, 11, DFLAGS,
950 RK1808_CLKGATE_CON(14), 2, GFLAGS),
951 COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
952 RK1808_CLKSEL_CON(66), 15, 1, MFLAGS, 0, 11, DFLAGS,
953 RK1808_CLKGATE_CON(14), 3, GFLAGS),
954 COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
955 RK1808_CLKSEL_CON(67), 15, 1, MFLAGS, 0, 11, DFLAGS,
956 RK1808_CLKGATE_CON(14), 4, GFLAGS),
957 COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
958 RK1808_CLKSEL_CON(68), 15, 1, MFLAGS, 0, 11, DFLAGS,
959 RK1808_CLKGATE_CON(14), 5, GFLAGS),
960
961 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
962 RK1808_CLKSEL_CON(69), 7, 1, MFLAGS, 0, 7, DFLAGS,
963 RK1808_CLKGATE_CON(13), 10, GFLAGS),
964 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
965 RK1808_CLKSEL_CON(69), 15, 1, MFLAGS, 8, 7, DFLAGS,
966 RK1808_CLKGATE_CON(13), 11, GFLAGS),
967 COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_gpll_xin24m_p, 0,
968 RK1808_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 7, DFLAGS,
969 RK1808_CLKGATE_CON(13), 12, GFLAGS),
970
971 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
972 RK1808_CLKGATE_CON(14), 8, GFLAGS),
973 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
974 RK1808_CLKGATE_CON(14), 9, GFLAGS),
975 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
976 RK1808_CLKGATE_CON(14), 10, GFLAGS),
977 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
978 RK1808_CLKGATE_CON(14), 11, GFLAGS),
979 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
980 RK1808_CLKGATE_CON(14), 12, GFLAGS),
981 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
982 RK1808_CLKGATE_CON(14), 13, GFLAGS),
983
984 /*
985 * Clock-Architecture Diagram 10
986 */
987
988 /* PD_AUDIO */
989
990 GATE(0, "hclk_audio_niu", "hclk_audio_pre", CLK_IGNORE_UNUSED,
991 RK1808_CLKGATE_CON(18), 11, GFLAGS),
992 GATE(HCLK_VAD, "hclk_vad", "hclk_audio_pre", 0,
993 RK1808_CLKGATE_CON(18), 12, GFLAGS),
994 GATE(HCLK_PDM, "hclk_pdm", "hclk_audio_pre", 0,
995 RK1808_CLKGATE_CON(18), 13, GFLAGS),
996 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_pre", 0,
997 RK1808_CLKGATE_CON(18), 14, GFLAGS),
998 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_audio_pre", 0,
999 RK1808_CLKGATE_CON(18), 15, GFLAGS),
1000
1001 COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_cpll_npll_p, 0,
1002 RK1808_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 7, DFLAGS,
1003 RK1808_CLKGATE_CON(17), 9, GFLAGS),
1004 COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
1005 RK1808_CLKSEL_CON(31), 0,
1006 RK1808_CLKGATE_CON(17), 10, GFLAGS,
1007 &rk1808_pdm_fracmux),
1008 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
1009 RK1808_CLKGATE_CON(17), 11, GFLAGS),
1010
1011 COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_gpll_cpll_npll_p, 0,
1012 RK1808_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 7, DFLAGS,
1013 RK1808_CLKGATE_CON(17), 12, GFLAGS),
1014 COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
1015 RK1808_CLKSEL_CON(33), 0,
1016 RK1808_CLKGATE_CON(17), 13, GFLAGS,
1017 &rk1808_i2s0_8ch_tx_fracmux),
1018 COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
1019 RK1808_CLKSEL_CON(32), 12, 1, MFLAGS,
1020 RK1808_CLKGATE_CON(17), 14, GFLAGS),
1021 COMPOSITE_NODIV(SCLK_I2S0_8CH_TX_OUT, "clk_i2s0_8ch_tx_out", mux_i2s0_8ch_tx_out_p, CLK_SET_RATE_PARENT,
1022 RK1808_CLKSEL_CON(32), 14, 2, MFLAGS,
1023 RK1808_CLKGATE_CON(17), 15, GFLAGS),
1024
1025 COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_gpll_cpll_npll_p, 0,
1026 RK1808_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 7, DFLAGS,
1027 RK1808_CLKGATE_CON(18), 0, GFLAGS),
1028 COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
1029 RK1808_CLKSEL_CON(35), 0,
1030 RK1808_CLKGATE_CON(18), 1, GFLAGS,
1031 &rk1808_i2s0_8ch_rx_fracmux),
1032 COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
1033 RK1808_CLKSEL_CON(34), 12, 1, MFLAGS,
1034 RK1808_CLKGATE_CON(18), 2, GFLAGS),
1035 COMPOSITE_NODIV(SCLK_I2S0_8CH_RX_OUT, "clk_i2s0_8ch_rx_out", mux_i2s0_8ch_rx_out_p, CLK_SET_RATE_PARENT,
1036 RK1808_CLKSEL_CON(34), 14, 2, MFLAGS,
1037 RK1808_CLKGATE_CON(18), 3, GFLAGS),
1038
1039 COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_gpll_cpll_npll_p, 0,
1040 RK1808_CLKSEL_CON(36), 8, 2, MFLAGS, 0, 7, DFLAGS,
1041 RK1808_CLKGATE_CON(18), 4, GFLAGS),
1042 COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
1043 RK1808_CLKSEL_CON(37), 0,
1044 RK1808_CLKGATE_CON(18), 5, GFLAGS,
1045 &rk1808_i2s1_2ch_fracmux),
1046 GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
1047 RK1808_CLKGATE_CON(18), 6, GFLAGS),
1048 COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
1049 RK1808_CLKSEL_CON(36), 15, 1, MFLAGS,
1050 RK1808_CLKGATE_CON(18), 7, GFLAGS),
1051
1052 /*
1053 * Clock-Architecture Diagram 10
1054 */
1055
1056 /* PD_BUS */
1057
1058 GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 0, GFLAGS),
1059 GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 1, GFLAGS),
1060 GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 2, GFLAGS),
1061 GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, RK1808_CLKGATE_CON(19), 3, GFLAGS),
1062 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, RK1808_CLKGATE_CON(19), 4, GFLAGS),
1063
1064 GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 6, GFLAGS),
1065 GATE(0, "pclk_usb3_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 7, GFLAGS),
1066 GATE(0, "pclk_usb_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 8, GFLAGS),
1067
1068 /*
1069 * Clock-Architecture Diagram 11
1070 */
1071
1072 /* PD_PMU */
1073
1074 COMPOSITE_FRACMUX(SCLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
1075 RK1808_PMU_CLKSEL_CON(1), 0,
1076 RK1808_PMU_CLKGATE_CON(0), 13, GFLAGS,
1077 &rk1808_rtc32k_pmu_fracmux),
1078
1079 COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
1080 RK1808_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
1081 RK1808_PMU_CLKGATE_CON(0), 12, GFLAGS),
1082
1083 COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "ppll", 0,
1084 RK1808_PMU_CLKSEL_CON(2), 8, 6, DFLAGS,
1085 RK1808_PMU_CLKGATE_CON(0), 14, GFLAGS),
1086 COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
1087 RK1808_PMU_CLKSEL_CON(2), 15, 1, MFLAGS,
1088 RK1808_PMU_CLKGATE_CON(0), 15, GFLAGS),
1089
1090 COMPOSITE(0, "clk_uart0_pmu_src", mux_gpll_usb480m_cpll_ppll_p, 0,
1091 RK1808_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
1092 RK1808_PMU_CLKGATE_CON(1), 0, GFLAGS),
1093 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0,
1094 RK1808_PMU_CLKSEL_CON(4), 0, 7, DFLAGS,
1095 RK1808_PMU_CLKGATE_CON(1), 1, GFLAGS),
1096 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
1097 RK1808_PMU_CLKSEL_CON(5), 0,
1098 RK1808_PMU_CLKGATE_CON(1), 2, GFLAGS,
1099 &rk1808_uart0_pmu_fracmux),
1100 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
1101 RK1808_PMU_CLKGATE_CON(1), 3, GFLAGS),
1102
1103 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
1104 RK1808_PMU_CLKGATE_CON(1), 4, GFLAGS),
1105
1106 COMPOSITE(SCLK_PMU_I2C0, "clk_pmu_i2c0", mux_ppll_xin24m_p, 0,
1107 RK1808_PMU_CLKSEL_CON(7), 15, 1, MFLAGS, 8, 7, DFLAGS,
1108 RK1808_PMU_CLKGATE_CON(1), 5, GFLAGS),
1109
1110 COMPOSITE(DBCLK_PMU_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,
1111 RK1808_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 11, DFLAGS,
1112 RK1808_PMU_CLKGATE_CON(1), 6, GFLAGS),
1113
1114 COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "ppll", 0,
1115 RK1808_PMU_CLKSEL_CON(2), 0, 6, DFLAGS,
1116 RK1808_PMU_CLKGATE_CON(1), 8, GFLAGS),
1117 COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
1118 RK1808_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
1119 RK1808_PMU_CLKGATE_CON(1), 9, GFLAGS),
1120 COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
1121 RK1808_PMU_CLKSEL_CON(2), 7, 1, MFLAGS,
1122 RK1808_PMU_CLKGATE_CON(1), 10, GFLAGS),
1123
1124 FACTOR(0, "clk_ppll_ph0", "ppll", 0, 1, 2),
1125 COMPOSITE_NOMUX(0, "clk_pciephy_src", "clk_ppll_ph0", 0,
1126 RK1808_PMU_CLKSEL_CON(7), 0, 2, DFLAGS,
1127 RK1808_PMU_CLKGATE_CON(1), 11, GFLAGS),
1128 COMPOSITE_NODIV(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pciephy_ref_p, CLK_SET_RATE_PARENT,
1129 RK1808_PMU_CLKSEL_CON(7), 4, 1, MFLAGS,
1130 RK1808_PMU_CLKGATE_CON(1), 12, GFLAGS),
1131
1132 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "ppll", CLK_IS_CRITICAL,
1133 RK1808_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
1134 RK1808_PMU_CLKGATE_CON(0), 0, GFLAGS),
1135
1136 GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IS_CRITICAL, RK1808_PMU_CLKGATE_CON(0), 1, GFLAGS),
1137 GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 2, GFLAGS),
1138 GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 3, GFLAGS),
1139 GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 4, GFLAGS),
1140 GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 5, GFLAGS),
1141 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 6, GFLAGS),
1142 GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 7, GFLAGS),
1143 GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 8, GFLAGS),
1144 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 9, GFLAGS),
1145
1146 MUXPMUGRF(SCLK_32K_IOE, "clk_32k_ioe", mux_clk_32k_ioe_p, 0,
1147 RK1808_PMUGRF_SOC_CON0, 0, 1, MFLAGS)
1148 };
1149
1150 static void __iomem *rk1808_cru_base;
1151
rk1808_dump_cru(void)1152 void rk1808_dump_cru(void)
1153 {
1154 if (rk1808_cru_base) {
1155 pr_warn("CRU:\n");
1156 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1157 32, 4, rk1808_cru_base,
1158 0x500, false);
1159 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1160 32, 4, rk1808_cru_base + 0x4000,
1161 0x100, false);
1162 }
1163 }
1164 EXPORT_SYMBOL_GPL(rk1808_dump_cru);
1165
rk1808_clk_panic(struct notifier_block * this,unsigned long ev,void * ptr)1166 static int rk1808_clk_panic(struct notifier_block *this,
1167 unsigned long ev, void *ptr)
1168 {
1169 rk1808_dump_cru();
1170 return NOTIFY_DONE;
1171 }
1172
1173 static struct notifier_block rk1808_clk_panic_block = {
1174 .notifier_call = rk1808_clk_panic,
1175 };
1176
rk1808_clk_init(struct device_node * np)1177 static void __init rk1808_clk_init(struct device_node *np)
1178 {
1179 struct rockchip_clk_provider *ctx;
1180 void __iomem *reg_base;
1181 struct clk **clks;
1182
1183 reg_base = of_iomap(np, 0);
1184 if (!reg_base) {
1185 pr_err("%s: could not map cru region\n", __func__);
1186 return;
1187 }
1188
1189 rk1808_cru_base = reg_base;
1190
1191 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1192 if (IS_ERR(ctx)) {
1193 pr_err("%s: rockchip clk init failed\n", __func__);
1194 iounmap(reg_base);
1195 return;
1196 }
1197 clks = ctx->clk_data.clks;
1198
1199 rockchip_clk_register_plls(ctx, rk1808_pll_clks,
1200 ARRAY_SIZE(rk1808_pll_clks),
1201 RK1808_GRF_SOC_STATUS0);
1202 rockchip_clk_register_branches(ctx, rk1808_clk_branches,
1203 ARRAY_SIZE(rk1808_clk_branches));
1204
1205 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1206 3, clks[PLL_APLL], clks[PLL_GPLL],
1207 &rk1808_cpuclk_data, rk1808_cpuclk_rates,
1208 ARRAY_SIZE(rk1808_cpuclk_rates));
1209
1210 rockchip_register_softrst(np, 16, reg_base + RK1808_SOFTRST_CON(0),
1211 ROCKCHIP_SOFTRST_HIWORD_MASK);
1212
1213 rockchip_register_restart_notifier(ctx, RK1808_GLB_SRST_FST, NULL);
1214
1215 rockchip_clk_of_add_provider(np, ctx);
1216
1217 atomic_notifier_chain_register(&panic_notifier_list,
1218 &rk1808_clk_panic_block);
1219 }
1220
1221 CLK_OF_DECLARE(rk1808_cru, "rockchip,rk1808-cru", rk1808_clk_init);
1222
clk_rk1808_probe(struct platform_device * pdev)1223 static int __init clk_rk1808_probe(struct platform_device *pdev)
1224 {
1225 struct device_node *np = pdev->dev.of_node;
1226
1227 rk1808_clk_init(np);
1228
1229 return 0;
1230 }
1231
1232 static const struct of_device_id clk_rk1808_match_table[] = {
1233 {
1234 .compatible = "rockchip,rk1808-cru",
1235 },
1236 { }
1237 };
1238 MODULE_DEVICE_TABLE(of, clk_rk1808_match_table);
1239
1240 static struct platform_driver clk_rk1808_driver = {
1241 .driver = {
1242 .name = "clk-rk1808",
1243 .of_match_table = clk_rk1808_match_table,
1244 },
1245 };
1246 builtin_platform_driver_probe(clk_rk1808_driver, clk_rk1808_probe);
1247
1248 MODULE_DESCRIPTION("Rockchip RK1808 Clock Driver");
1249 MODULE_LICENSE("GPL");
1250