1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 mmc0 = &emmc; 27 mmc1 = &sdmmc; 28 spi0 = &spi0; 29 spi1 = &spi1; 30 spi2 = &spi2; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a35", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35", "arm,armv8"; 47 reg = <0x0 0x1>; 48 enable-method = "psci"; 49 }; 50 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a35", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 58 cpu3: cpu@3 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a35", "arm,armv8"; 61 reg = <0x0 0x3>; 62 enable-method = "psci"; 63 }; 64 }; 65 66 arm-pmu { 67 compatible = "arm,cortex-a53-pmu"; 68 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 72 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 73 }; 74 75 mac_clkin: external-mac-clock { 76 compatible = "fixed-clock"; 77 clock-frequency = <50000000>; 78 clock-output-names = "mac_clkin"; 79 #clock-cells = <0>; 80 }; 81 82 display_subsystem: display-subsystem { 83 compatible = "rockchip,display-subsystem"; 84 ports = <&vop_out>; 85 status = "disabled"; 86 87 route { 88 route_rgb: route-rgb { 89 status = "okay"; 90 logo,uboot = "logo.bmp"; 91 logo,kernel = "logo_kernel.bmp"; 92 logo,mode = "center"; 93 charge_logo,mode = "center"; 94 connect = <&vop_out_rgb>; 95 }; 96 }; 97 }; 98 99 dmc: dmc@20004000 { 100 compatible = "rockchip,rk3308-dmc"; 101 reg = <0x0 0xff010000 0x0 0x10000>; 102 }; 103 104 psci: psci { 105 compatible = "arm,psci-1.0"; 106 method = "smc"; 107 }; 108 109 timer { 110 compatible = "arm,armv8-timer"; 111 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 114 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 115 clock-frequency = <24000000>; 116 }; 117 118 clocks { 119 xin24m: xin24m { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <24000000>; 123 clock-output-names = "xin24m"; 124 }; 125 }; 126 127 grf: grf@ff000000 { 128 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 129 reg = <0x0 0xff000000 0x0 0x10000>; 130 }; 131 132 usb2phy_grf: syscon@ff008000 { 133 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 134 "simple-mfd"; 135 reg = <0x0 0xff008000 0x0 0x4000>; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 139 u2phy: usb2-phy@100 { 140 compatible = "rockchip,rk3308-usb2phy", 141 "rockchip,rk3328-usb2phy"; 142 reg = <0x100 0x10>; 143 clocks = <&cru SCLK_USBPHY_REF>; 144 clock-names = "phyclk"; 145 #clock-cells = <0>; 146 assigned-clocks = <&cru USB480M>; 147 assigned-clock-parents = <&u2phy>; 148 clock-output-names = "usb480m_phy"; 149 status = "disabled"; 150 151 u2phy_host: host-port { 152 #phy-cells = <0>; 153 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 154 interrupt-names = "linestate"; 155 status = "disabled"; 156 }; 157 158 u2phy_otg: otg-port { 159 #phy-cells = <0>; 160 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 163 interrupt-names = "otg-bvalid", "otg-id", 164 "linestate"; 165 status = "disabled"; 166 }; 167 }; 168 }; 169 170 uart0: serial@ff0a0000 { 171 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 172 reg = <0x0 0xff0a0000 0x0 0x100>; 173 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 175 clock-names = "baudclk", "apb_pclk"; 176 reg-shift = <2>; 177 reg-io-width = <4>; 178 status = "disabled"; 179 }; 180 181 uart1: serial@ff0b0000 { 182 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 183 reg = <0x0 0xff0b0000 0x0 0x100>; 184 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 186 clock-names = "baudclk", "apb_pclk"; 187 reg-shift = <2>; 188 reg-io-width = <4>; 189 status = "disabled"; 190 }; 191 192 uart2: serial@ff0c0000 { 193 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 194 reg = <0x0 0xff0c0000 0x0 0x100>; 195 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 197 clock-names = "baudclk", "apb_pclk"; 198 reg-shift = <2>; 199 reg-io-width = <4>; 200 status = "disabled"; 201 }; 202 203 uart3: serial@ff0d0000 { 204 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 205 reg = <0x0 0xff0d0000 0x0 0x100>; 206 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 208 clock-names = "baudclk", "apb_pclk"; 209 reg-shift = <2>; 210 reg-io-width = <4>; 211 status = "disabled"; 212 }; 213 214 uart4: serial@ff0e0000 { 215 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 216 reg = <0x0 0xff0e0000 0x0 0x100>; 217 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 219 clock-names = "baudclk", "apb_pclk"; 220 reg-shift = <2>; 221 reg-io-width = <4>; 222 status = "disabled"; 223 }; 224 225 spi0: spi@ff120000 { 226 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 227 reg = <0x0 0xff120000 0x0 0x1000>; 228 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 232 clock-names = "spiclk", "apb_pclk"; 233 pinctrl-names = "default", "high_speed"; 234 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 235 pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>; 236 status = "disabled"; 237 }; 238 239 spi1: spi@ff130000 { 240 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 241 reg = <0x0 0xff130000 0x0 0x1000>; 242 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 246 clock-names = "spiclk", "apb_pclk"; 247 pinctrl-names = "default", "high_speed"; 248 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 249 pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>; 250 status = "disabled"; 251 }; 252 253 spi2: spi@ff140000 { 254 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 255 reg = <0x0 0xff140000 0x0 0x1000>; 256 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 260 clock-names = "spiclk", "apb_pclk"; 261 pinctrl-names = "default", "high_speed"; 262 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 263 pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>; 264 status = "disabled"; 265 }; 266 267 vop: vop@ff2e0000 { 268 compatible = "rockchip,rk3308-vop"; 269 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; 270 reg-names = "regs", "gamma_lut"; 271 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 273 <&cru HCLK_VOP>; 274 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 275 status = "disabled"; 276 277 vop_out: port { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 281 vop_out_rgb: endpoint@0 { 282 reg = <0>; 283 remote-endpoint = <&rgb_in_vop>; 284 }; 285 }; 286 }; 287 288 crypto: crypto@ff2f0000 { 289 compatible = "rockchip,rk3308-crypto"; 290 reg = <0x0 0xff2f0000 0x0 0x4000>; 291 clock-names = "sclk_crypto", "apkclk_crypto"; 292 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; 293 clock-frequency = <200000000>, <300000000>; 294 status = "disabled"; 295 }; 296 297 pwm0: pwm@ff180000 { 298 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 299 reg = <0x0 0xff180000 0x0 0x10>; 300 #pwm-cells = <3>; 301 pinctrl-names = "active"; 302 pinctrl-0 = <&pwm0_pin>; 303 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 304 clock-names = "pwm", "pclk"; 305 status = "disabled"; 306 }; 307 308 pwm1: pwm@ff180010 { 309 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 310 reg = <0x0 0xff180010 0x0 0x10>; 311 #pwm-cells = <3>; 312 pinctrl-names = "active"; 313 pinctrl-0 = <&pwm1_pin>; 314 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 315 clock-names = "pwm", "pclk"; 316 status = "disabled"; 317 }; 318 319 pwm2: pwm@ff180020 { 320 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 321 reg = <0x0 0xff180020 0x0 0x10>; 322 #pwm-cells = <3>; 323 pinctrl-names = "active"; 324 pinctrl-0 = <&pwm2_pin>; 325 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 326 clock-names = "pwm", "pclk"; 327 status = "disabled"; 328 }; 329 330 pwm3: pwm@ff180030 { 331 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 332 reg = <0x0 0xff180030 0x0 0x10>; 333 #pwm-cells = <3>; 334 pinctrl-names = "active"; 335 pinctrl-0 = <&pwm3_pin>; 336 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 337 clock-names = "pwm", "pclk"; 338 status = "disabled"; 339 }; 340 341 rgb: rgb { 342 compatible = "rockchip,rk3308-rgb"; 343 status = "disabled"; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&lcdc_ctl>; 346 347 ports { 348 #address-cells = <1>; 349 #size-cells = <0>; 350 351 port@0 { 352 reg = <0>; 353 354 #address-cells = <1>; 355 #size-cells = <0>; 356 357 rgb_in_vop: endpoint@0 { 358 reg = <0>; 359 remote-endpoint = <&vop_out_rgb>; 360 }; 361 }; 362 363 }; 364 }; 365 366 saradc: saradc@ff1e0000 { 367 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 368 reg = <0x0 0xff1e0000 0x0 0x100>; 369 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 370 #io-channel-cells = <1>; 371 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 372 clock-names = "saradc", "apb_pclk"; 373 resets = <&cru SRST_SARADC_P>; 374 reset-names = "saradc-apb"; 375 status = "disabled"; 376 }; 377 378 i2s0: i2s@ff300000 { 379 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 380 reg = <0x0 0xff300000 0x0 0x10000>; 381 }; 382 383 i2s1: i2s@ff310000 { 384 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 385 reg = <0x0 0xff100000 0x0 0x10000>; 386 }; 387 388 i2s2: i2s@ff320000 { 389 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 390 reg = <0x0 0xff320000 0x0 0x10000>; 391 }; 392 393 i2s3: i2s@ff330000 { 394 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 395 reg = <0x0 0xff330000 0x0 0x10000>; 396 }; 397 398 vad: vad@ff3c0000 { 399 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 400 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 401 reg-names = "vad", "vad-memory"; 402 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 403 rockchip,audio-src = <0>; 404 rockchip,audio-chnl-num = <8>; 405 rockchip,audio-chnl = <0>; 406 rockchip,mode = <0>; 407 }; 408 409 usb20_otg: usb@ff400000 { 410 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 411 "snps,dwc2"; 412 reg = <0x0 0xff400000 0x0 0x40000>; 413 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&cru HCLK_OTG>; 415 clock-names = "otg"; 416 dr_mode = "otg"; 417 g-np-tx-fifo-size = <16>; 418 g-rx-fifo-size = <275>; 419 g-tx-fifo-size = <256 128 128 64 64 32>; 420 g-use-dma; 421 phys = <&u2phy_otg>; 422 phy-names = "usb2-phy"; 423 status = "disabled"; 424 }; 425 426 usb_host0_ehci: usb@ff440000 { 427 compatible = "generic-ehci"; 428 reg = <0x0 0xff440000 0x0 0x10000>; 429 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 431 <&u2phy>; 432 clock-names = "usbhost", "arbiter", "utmi"; 433 phys = <&u2phy_host>; 434 phy-names = "usb"; 435 status = "disabled"; 436 }; 437 438 usb_host0_ohci: usb@ff450000 { 439 compatible = "generic-ohci"; 440 reg = <0x0 0xff450000 0x0 0x10000>; 441 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 443 <&u2phy>; 444 clock-names = "usbhost", "arbiter", "utmi"; 445 phys = <&u2phy_host>; 446 phy-names = "usb"; 447 }; 448 449 sdmmc: dwmmc@ff480000 { 450 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 451 reg = <0x0 0xff480000 0x0 0x4000>; 452 max-frequency = <150000000>; 453 bus-width = <4>; 454 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 455 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 456 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 457 fifo-depth = <0x100>; 458 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 461 status = "disabled"; 462 }; 463 464 emmc: dwmmc@ff490000 { 465 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 466 reg = <0x0 0xff490000 0x0 0x4000>; 467 max-frequency = <150000000>; 468 bus-width = <8>; 469 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 470 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 471 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 472 fifo-depth = <0x100>; 473 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 474 status = "disabled"; 475 }; 476 477 sdio: dwmmc@ff4a0000 { 478 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 479 reg = <0x0 0xff4a0000 0x0 0x4000>; 480 max-frequency = <150000000>; 481 bus-width = <4>; 482 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 483 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 484 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 485 fifo-depth = <0x100>; 486 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 489 status = "disabled"; 490 }; 491 492 nandc: nandc@ff4b0000 { 493 compatible = "rockchip,rk-nandc"; 494 reg = <0x0 0xff4b0000 0x0 0x4000>; 495 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 496 nandc_id = <0>; 497 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 498 clock-names = "clk_nandc", "hclk_nandc"; 499 status = "disabled"; 500 }; 501 502 503 sfc: sfc@ff4c0000 { 504 compatible = "rockchip,rksfc","rockchip,sfc"; 505 reg = <0x0 0xff4c0000 0x0 0x4000>; 506 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 508 clock-names = "clk_sfc", "hclk_sfc"; 509 status = "disabled"; 510 }; 511 512 mac: ethernet@ff4e0000 { 513 compatible = "rockchip,rk3308-mac"; 514 reg = <0x0 0xff4e0000 0x0 0x10000>; 515 rockchip,grf = <&grf>; 516 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 517 interrupt-names = "macirq"; 518 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 519 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 520 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 521 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 522 clock-names = "stmmaceth", "mac_clk_rx", 523 "mac_clk_tx", "clk_mac_ref", 524 "clk_mac_refout", "aclk_mac", 525 "pclk_mac", "clk_mac_speed"; 526 phy-mode = "rmii"; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 529 resets = <&cru SRST_MAC_A>; 530 reset-names = "stmmaceth"; 531 status = "disabled"; 532 }; 533 534 cru: clock-controller@ff500000 { 535 compatible = "rockchip,rk3308-cru"; 536 reg = <0x0 0xff500000 0x0 0x1000>; 537 rockchip,grf = <&grf>; 538 #clock-cells = <1>; 539 #reset-cells = <1>; 540 }; 541 542 gic: interrupt-controller@ff580000 { 543 compatible = "arm,gic-400"; 544 #interrupt-cells = <3>; 545 #address-cells = <0>; 546 interrupt-controller; 547 548 reg = <0x0 0xff581000 0x0 0x1000>, 549 <0x0 0xff582000 0x0 0x2000>, 550 <0x0 0xff584000 0x0 0x2000>, 551 <0x0 0xff586000 0x0 0x2000>; 552 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 553 }; 554 555 pinctrl: pinctrl { 556 compatible = "rockchip,rk3308-pinctrl"; 557 rockchip,grf = <&grf>; 558 #address-cells = <2>; 559 #size-cells = <2>; 560 ranges; 561 562 gpio0: gpio0@ff220000 { 563 compatible = "rockchip,gpio-bank"; 564 reg = <0x0 0xff220000 0x0 0x100>; 565 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 566 //clocks = <&cru PCLK_GPIO0>; 567 clocks = <&xin24m>; 568 gpio-controller; 569 #gpio-cells = <2>; 570 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 }; 574 575 gpio1: gpio1@ff230000 { 576 compatible = "rockchip,gpio-bank"; 577 reg = <0x0 0xff230000 0x0 0x100>; 578 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 579 //clocks = <&cru PCLK_GPIO1>; 580 clocks = <&xin24m>; 581 gpio-controller; 582 #gpio-cells = <2>; 583 584 interrupt-controller; 585 #interrupt-cells = <2>; 586 }; 587 588 gpio2: gpio2@ff240000 { 589 compatible = "rockchip,gpio-bank"; 590 reg = <0x0 0xff240000 0x0 0x100>; 591 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 592 //clocks = <&cru PCLK_GPIO2>; 593 clocks = <&xin24m>; 594 gpio-controller; 595 #gpio-cells = <2>; 596 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 }; 600 601 gpio3: gpio3@ff250000 { 602 compatible = "rockchip,gpio-bank"; 603 reg = <0x0 0xff250000 0x0 0x100>; 604 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 605 //clocks = <&cru PCLK_GPIO3>; 606 clocks = <&xin24m>; 607 gpio-controller; 608 #gpio-cells = <2>; 609 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 }; 613 614 gpio4: gpio4@ff260000 { 615 compatible = "rockchip,gpio-bank"; 616 reg = <0x0 0xff260000 0x0 0x100>; 617 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 618 //clocks = <&cru PCLK_GPIO4>; 619 clocks = <&xin24m>; 620 gpio-controller; 621 #gpio-cells = <2>; 622 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 }; 626 627 pcfg_pull_up: pcfg-pull-up { 628 bias-pull-up; 629 }; 630 631 pcfg_pull_down: pcfg-pull-down { 632 bias-pull-down; 633 }; 634 635 pcfg_pull_none: pcfg-pull-none { 636 bias-disable; 637 }; 638 639 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 640 bias-disable; 641 drive-strength = <2>; 642 }; 643 644 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 645 bias-pull-up; 646 drive-strength = <2>; 647 }; 648 649 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 650 bias-pull-up; 651 drive-strength = <4>; 652 }; 653 654 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 655 bias-disable; 656 drive-strength = <4>; 657 }; 658 659 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 660 bias-pull-down; 661 drive-strength = <4>; 662 }; 663 664 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 665 bias-disable; 666 drive-strength = <8>; 667 }; 668 669 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 670 bias-pull-up; 671 drive-strength = <8>; 672 }; 673 674 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 675 bias-disable; 676 drive-strength = <12>; 677 }; 678 679 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 680 bias-pull-up; 681 drive-strength = <12>; 682 }; 683 684 pcfg_pull_none_smt: pcfg-pull-none-smt { 685 bias-disable; 686 input-schmitt-enable; 687 }; 688 689 pcfg_output_high: pcfg-output-high { 690 output-high; 691 }; 692 693 pcfg_output_low: pcfg-output-low { 694 output-low; 695 }; 696 697 pcfg_input_high: pcfg-input-high { 698 bias-pull-up; 699 input-enable; 700 }; 701 702 pcfg_input: pcfg-input { 703 input-enable; 704 }; 705 706 i2c0 { 707 i2c0_xfer: i2c0-xfer { 708 rockchip,pins = 709 <1 RK_PD0 2 &pcfg_pull_none_smt>, 710 <1 RK_PD1 2 &pcfg_pull_none_smt>; 711 }; 712 }; 713 714 i2c1 { 715 i2c1_xfer: i2c1-xfer { 716 rockchip,pins = 717 <0 RK_PB3 1 &pcfg_pull_none_smt>, 718 <0 RK_PB4 1 &pcfg_pull_none_smt>; 719 }; 720 }; 721 722 i2c2 { 723 i2c2_xfer: i2c2-xfer { 724 rockchip,pins = 725 <2 RK_PA2 3 &pcfg_pull_none_smt>, 726 <2 RK_PA3 3 &pcfg_pull_none_smt>; 727 }; 728 }; 729 730 i2c3-m0 { 731 i2c3m0_xfer: i2c3m0-xfer { 732 rockchip,pins = 733 <0 RK_PB7 2 &pcfg_pull_none_smt>, 734 <0 RK_PC0 2 &pcfg_pull_none_smt>; 735 }; 736 }; 737 738 i2c3-m1 { 739 i2c3m1_xfer: i2c3m1-xfer { 740 rockchip,pins = 741 <3 RK_PB4 2 &pcfg_pull_none_smt>, 742 <3 RK_PB5 2 &pcfg_pull_none_smt>; 743 }; 744 }; 745 746 tsadc { 747 tsadc_otp_gpio: tsadc-otp-gpio { 748 rockchip,pins = 749 <0 RK_PB2 0 &pcfg_pull_none>; 750 }; 751 752 tsadc_otp_out: tsadc-otp-out { 753 rockchip,pins = 754 <0 RK_PB2 1 &pcfg_pull_none>; 755 }; 756 }; 757 758 uart0 { 759 uart0_xfer: uart0-xfer { 760 rockchip,pins = 761 <2 RK_PA1 1 &pcfg_pull_up>, 762 <2 RK_PA0 1 &pcfg_pull_none>; 763 }; 764 765 uart0_cts: uart0-cts { 766 rockchip,pins = 767 <2 RK_PA2 1 &pcfg_pull_none>; 768 }; 769 770 uart0_rts: uart0-rts { 771 rockchip,pins = 772 <2 RK_PA3 1 &pcfg_pull_none>; 773 }; 774 }; 775 776 uart1 { 777 uart1_xfer: uart1-xfer { 778 rockchip,pins = 779 <1 RK_PD1 1 &pcfg_pull_up>, 780 <1 RK_PD0 1 &pcfg_pull_none>; 781 }; 782 783 uart1_cts: uart1-cts { 784 rockchip,pins = 785 <1 RK_PC6 1 &pcfg_pull_none>; 786 }; 787 788 uart1_rts: uart1-rts { 789 rockchip,pins = 790 <1 RK_PC7 1 &pcfg_pull_none>; 791 }; 792 }; 793 794 uart2-m0 { 795 uart2m0_xfer: uart2m0-xfer { 796 rockchip,pins = 797 <1 RK_PC7 2 &pcfg_pull_up>, 798 <1 RK_PC6 2 &pcfg_pull_none>; 799 }; 800 }; 801 802 uart2-m1 { 803 uart2m1_xfer: uart2m1-xfer { 804 rockchip,pins = 805 <4 RK_PD3 2 &pcfg_pull_up>, 806 <4 RK_PD2 2 &pcfg_pull_none>; 807 }; 808 }; 809 810 uart3 { 811 uart3_xfer: uart3-xfer { 812 rockchip,pins = 813 <3 RK_PB5 4 &pcfg_pull_up>, 814 <3 RK_PB4 4 &pcfg_pull_none>; 815 }; 816 }; 817 818 uart4 { 819 820 uart4_xfer: uart4-xfer { 821 rockchip,pins = 822 <4 RK_PB1 1 &pcfg_pull_up>, 823 <4 RK_PB0 1 &pcfg_pull_none>; 824 }; 825 826 uart4_cts: uart4-cts { 827 rockchip,pins = 828 <4 RK_PA6 1 &pcfg_pull_none>; 829 830 }; 831 832 uart4_rts: uart4-rts { 833 rockchip,pins = 834 <4 RK_PA7 1 &pcfg_pull_none>; 835 }; 836 }; 837 838 spi0 { 839 spi0_clk: spi0-clk { 840 rockchip,pins = 841 <2 RK_PA2 2 &pcfg_pull_up>; 842 }; 843 844 spi0_csn0: spi0-csn0 { 845 rockchip,pins = 846 <2 RK_PA3 2 &pcfg_pull_up>; 847 }; 848 849 spi0_miso: spi0-miso { 850 rockchip,pins = 851 <2 RK_PA0 2 &pcfg_pull_up>; 852 }; 853 854 spi0_mosi: spi0-mosi { 855 rockchip,pins = 856 <2 RK_PA1 2 &pcfg_pull_up>; 857 }; 858 spi0_clk_hs: spi0-clk-hs { 859 rockchip,pins = 860 <2 RK_PA2 2 &pcfg_pull_up_8ma>; 861 }; 862 863 spi0_miso_hs: spi0-miso-hs { 864 rockchip,pins = 865 <2 RK_PA0 2 &pcfg_pull_up_8ma>; 866 }; 867 868 spi0_mosi_hs: spi0-mosi-hs { 869 rockchip,pins = 870 <2 RK_PA1 2 &pcfg_pull_up_8ma>; 871 }; 872 }; 873 874 spi1 { 875 spi1_clk: spi1-clk { 876 rockchip,pins = 877 <3 RK_PB3 3 &pcfg_pull_up>; 878 }; 879 880 spi1_csn0: spi1-csn0 { 881 rockchip,pins = 882 <3 RK_PB5 3 &pcfg_pull_up>; 883 }; 884 885 spi1_miso: spi1-miso { 886 rockchip,pins = 887 <3 RK_PB2 3 &pcfg_pull_up>; 888 }; 889 890 spi1_mosi: spi1-mosi { 891 rockchip,pins = 892 <3 RK_PB4 3 &pcfg_pull_up>; 893 }; 894 spi1_clk_hs: spi1-clk-hs { 895 rockchip,pins = 896 <3 RK_PB3 3 &pcfg_pull_up_8ma>; 897 }; 898 899 spi1_miso_hs: spi1-miso-hs { 900 rockchip,pins = 901 <3 RK_PB2 3 &pcfg_pull_up_8ma>; 902 }; 903 904 spi1_mosi_hs: spi1-mosi-hs { 905 rockchip,pins = 906 <3 RK_PB4 3 &pcfg_pull_up_8ma>; 907 }; 908 }; 909 910 spi2 { 911 spi2_clk: spi2-clk { 912 rockchip,pins = 913 <1 RK_PD0 3 &pcfg_pull_up>; 914 }; 915 916 spi2_csn0: spi2-csn0 { 917 rockchip,pins = 918 <1 RK_PD1 3 &pcfg_pull_up>; 919 }; 920 921 spi2_miso: spi2-miso { 922 rockchip,pins = 923 <1 RK_PC6 3 &pcfg_pull_up>; 924 }; 925 926 spi2_mosi: spi2-mosi { 927 rockchip,pins = 928 <1 RK_PC7 3 &pcfg_pull_up>; 929 }; 930 spi2_clk_hs: spi2-clk-hs { 931 rockchip,pins = 932 <1 RK_PD0 3 &pcfg_pull_up_8ma>; 933 }; 934 935 spi2_miso_hs: spi2-miso-hs { 936 rockchip,pins = 937 <1 RK_PC6 3 &pcfg_pull_up_8ma>; 938 }; 939 940 spi2_mosi_hs: spi2-mosi-hs { 941 rockchip,pins = 942 <1 RK_PC7 3 &pcfg_pull_up_8ma>; 943 }; 944 }; 945 946 sdmmc_pin: sdmmc_pin { 947 sdmmc_clk: sdmmc-clk { 948 rockchip,pins = 949 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 950 }; 951 952 sdmmc_cmd: sdmmc-cmd { 953 rockchip,pins = 954 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 955 }; 956 957 sdmmc_pwren: sdmmc-pwren { 958 rockchip,pins = 959 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 960 }; 961 962 sdmmc_bus1: sdmmc-bus1 { 963 rockchip,pins = 964 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 965 }; 966 967 sdmmc_bus4: sdmmc-bus4 { 968 rockchip,pins = 969 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 970 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 971 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 972 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 973 }; 974 975 sdmmc_gpio: sdmmc-gpio { 976 rockchip,pins = 977 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 978 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 979 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 980 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 981 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 982 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 983 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 984 }; 985 }; 986 987 sdio { 988 sdio_clk: sdio-clk { 989 rockchip,pins = 990 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 991 }; 992 993 sdio_cmd: sdio-cmd { 994 rockchip,pins = 995 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 996 }; 997 998 sdio_pwren: sdio-pwren { 999 rockchip,pins = 1000 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 1001 }; 1002 1003 sdio_wrpt: sdio-wrpt { 1004 rockchip,pins = 1005 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 1006 }; 1007 1008 sdio_intn: sdio-intn { 1009 rockchip,pins = 1010 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 1011 }; 1012 1013 sdio_bus1: sdio-bus1 { 1014 rockchip,pins = 1015 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 1016 }; 1017 1018 sdio_bus4: sdio-bus4 { 1019 rockchip,pins = 1020 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 1021 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 1022 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 1023 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 1024 }; 1025 1026 sdio_gpio: sdio-gpio { 1027 rockchip,pins = 1028 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 1029 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 1030 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 1031 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 1032 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 1033 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 1034 }; 1035 }; 1036 1037 emmc { 1038 emmc_clk: emmc-clk { 1039 rockchip,pins = 1040 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 1041 }; 1042 1043 emmc_cmd: emmc-cmd { 1044 rockchip,pins = 1045 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 1046 }; 1047 1048 emmc_pwren: emmc-pwren { 1049 rockchip,pins = 1050 <3 RK_PB3 2 &pcfg_pull_none>; 1051 }; 1052 1053 emmc_rstn: emmc-rstn { 1054 rockchip,pins = 1055 <3 RK_PB2 2 &pcfg_pull_none>; 1056 }; 1057 1058 emmc_bus1: emmc-bus1 { 1059 rockchip,pins = 1060 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 1061 }; 1062 1063 emmc_bus4: emmc-bus4 { 1064 rockchip,pins = 1065 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 1066 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 1067 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 1068 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 1069 }; 1070 1071 emmc_bus8: emmc-bus8 { 1072 rockchip,pins = 1073 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 1074 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 1075 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 1076 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 1077 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 1078 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 1079 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 1080 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 1081 }; 1082 }; 1083 1084 flash { 1085 flash_csn0: flash-csn0 { 1086 rockchip,pins = 1087 <3 RK_PB5 1 &pcfg_pull_none>; 1088 }; 1089 1090 flash_rdy: flash-rdy { 1091 rockchip,pins = 1092 <3 RK_PB4 1 &pcfg_pull_none>; 1093 }; 1094 1095 flash_ale: flash-ale { 1096 rockchip,pins = 1097 <3 RK_PB3 1 &pcfg_pull_none>; 1098 }; 1099 1100 flash_cle: flash-cle { 1101 rockchip,pins = 1102 <3 RK_PB1 1 &pcfg_pull_none>; 1103 }; 1104 1105 flash_wrn: flash-wrn { 1106 rockchip,pins = 1107 <3 RK_PB0 1 &pcfg_pull_none>; 1108 }; 1109 1110 flash_rdn: flash-rdn { 1111 rockchip,pins = 1112 <3 RK_PB2 1 &pcfg_pull_none>; 1113 }; 1114 1115 flash_bus8: flash-bus8 { 1116 rockchip,pins = 1117 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1118 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1119 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1120 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1121 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1122 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1123 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1124 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1125 }; 1126 }; 1127 1128 pwm0 { 1129 pwm0_pin: pwm0-pin { 1130 rockchip,pins = 1131 <0 RK_PB5 1 &pcfg_pull_none>; 1132 }; 1133 }; 1134 1135 pwm1 { 1136 pwm1_pin: pwm1-pin { 1137 rockchip,pins = 1138 <0 RK_PB6 1 &pcfg_pull_none>; 1139 }; 1140 }; 1141 1142 pwm2 { 1143 pwm2_pin: pwm2-pin { 1144 rockchip,pins = 1145 <0 RK_PB7 1 &pcfg_pull_none>; 1146 }; 1147 }; 1148 1149 pwm3 { 1150 pwm3_pin: pwm3-pin { 1151 rockchip,pins = 1152 <0 RK_PC0 1 &pcfg_pull_none>; 1153 }; 1154 }; 1155 1156 gmac { 1157 rmii_pins: rmii-pins { 1158 rockchip,pins = 1159 /* mac_txen */ 1160 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1161 /* mac_txd1 */ 1162 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1163 /* mac_txd0 */ 1164 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1165 /* mac_rxd0 */ 1166 <1 RK_PC4 3 &pcfg_pull_none>, 1167 /* mac_rxd1 */ 1168 <1 RK_PC5 3 &pcfg_pull_none>, 1169 /* mac_rxer */ 1170 <1 RK_PB7 3 &pcfg_pull_none>, 1171 /* mac_rxdv */ 1172 <1 RK_PC0 3 &pcfg_pull_none>, 1173 /* mac_mdio */ 1174 <1 RK_PB6 3 &pcfg_pull_none>, 1175 /* mac_mdc */ 1176 <1 RK_PB5 3 &pcfg_pull_none>; 1177 }; 1178 1179 mac_refclk_12ma: mac-refclk-12ma { 1180 rockchip,pins = 1181 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1182 }; 1183 1184 mac_refclk: mac-refclk { 1185 rockchip,pins = 1186 <1 RK_PB4 3 &pcfg_pull_none>; 1187 }; 1188 1189 }; 1190 1191 lcdc { 1192 lcdc_ctl: lcdc-ctl { 1193 rockchip,pins = 1194 /* dclk */ 1195 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 1196 /* hsync */ 1197 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, 1198 /* vsync */ 1199 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1200 /* den */ 1201 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1202 /* d0 */ 1203 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1204 /* d1 */ 1205 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1206 /* d2 */ 1207 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1208 /* d3 */ 1209 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1210 /* d4 */ 1211 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1212 /* d5 */ 1213 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1214 /* d6 */ 1215 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1216 /* d7 */ 1217 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1218 /* d8 */ 1219 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1220 /* d9 */ 1221 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1222 /* d10 */ 1223 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1224 /* d11 */ 1225 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, 1226 /* d12 */ 1227 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 1228 /* d13 */ 1229 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1230 /* d14 */ 1231 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, 1232 /* d15 */ 1233 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, 1234 /* d16 */ 1235 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 1236 /* d17 */ 1237 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1238 }; 1239 }; 1240 }; 1241}; 1242
