clk/rockchip/clk-rk3562.c

80 PNAME(mux_pll_p)			= { "xin24m" };
84 PNAME(gpll_cpll_hpll_xin24m_p)		= { "gpll", "cpll", "hpll", "xin24m" };
87 PNAME(gpll_cpll_xin24m_p)		= { "gpll", "cpll", "xin24m" };
88 PNAME(gpll_cpll_xin24m_dmyapll_p)	= { "gpll", "cpll", "xin24m", "dummy_apll" };
89 PNAME(gpll_cpll_xin24m_dmyhpll_p)	= { "gpll", "cpll", "xin24m", "dummy_hpll" };
91 PNAME(mux_xin24m_32k_p)			= { "xin24m", "clk_rtc_32k" };
92 PNAME(mux_50m_xin24m_p)			= { "clk_matrix_50m_src", "xin24m" };
93 PNAME(mux_100m_50m_xin24m_p)		= { "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" };
94 PNAME(mux_125m_xin24m_p)		= { "clk_matrix_125m_src", "xin24m" };
95 PNAME(mux_200m_xin24m_32k_p)		= { "clk_200m_pmu", "xin24m", "clk_rtc_32k" };
97 …m_50m_xin24m_p)	= { "clk_matrix_200m_src", "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" };
105 PNAME(clk_uart1_p)			= { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
106 PNAME(clk_uart2_p)			= { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
107 PNAME(clk_uart3_p)			= { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
108 PNAME(clk_uart4_p)			= { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
109 PNAME(clk_uart5_p)			= { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
110 PNAME(clk_uart6_p)			= { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
111 PNAME(clk_uart7_p)			= { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
112 PNAME(clk_uart8_p)			= { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
113 PNAME(clk_uart9_p)			= { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
115 PNAME(clk_pmu1_uart0_p)			= { "clk_pmu1_uart0_src", "clk_pmu1_uart0_frac", "xin24m" };
249 	FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
293 	GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
295 	GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
297 	GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
299 	GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
301 	GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
303 	GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
307 	GATE(CLK_STIMER0, "clk_stimer0", "xin24m", CLK_IGNORE_UNUSED,
309 	GATE(CLK_STIMER1, "clk_stimer1", "xin24m", CLK_IGNORE_UNUSED,
313 	GATE(CLK_WDTNS, "clk_wdtns", "xin24m", 0,
341 	COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
344 	COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
349 	COMPOSITE_NOMUX(CLK_SARADC_VCCIO156, "clk_saradc_vccio156", "xin24m", 0,
431 	GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
563 	GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
692 	GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
699 	GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
706 	GATE(CLK_CAPTURE_PWM3_PERI, "clk_capture_pwm3_peri", "xin24m", 0,
735 	GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
737 	COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
742 	GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", CLK_IGNORE_UNUSED,
744 	COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", CLK_IGNORE_UNUSED,
747 	GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
757 	COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
789 	GATE(CLK_PCIE20_AUX, "clk_pcie20_aux", "xin24m", 0,
796 	GATE(CLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0,
806 	COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IS_CRITICAL,
817 	GATE(CLK_PMU0_PMU, "clk_pmu0_pmu", "xin24m", CLK_IGNORE_UNUSED,
821 	GATE(CLK_PMU0_HP_TIMER, "clk_pmu0_hp_timer", "xin24m", CLK_IGNORE_UNUSED,
827 	GATE(CLK_PMU0_PVTM, "clk_pmu0_pvtm", "xin24m", 0,
833 	GATE(DBCLK_PMU0_GPIO0, "dbclk_pmu0_gpio0", "xin24m", 0,
839 	GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
846 	GATE(CLK_PIPEPHY_XIN24M, "clk_pipephy_xin24m", "xin24m", 0,
851 	GATE(CLK_USB2PHY_XIN24M, "clk_usb2phy_xin24m", "xin24m", 0,
856 	GATE(CLK_MIPIDSIPHY_XIN24M, "clk_mipidsiphy_xin24m", "xin24m", 0,
894 	GATE(CLK_CAPTURE_PMU1_PWM0, "clk_capture_pmu1_pwm0", "xin24m", 0,
896 	GATE(CLK_PMU1_WIFI, "clk_pmu1_wifi", "xin24m", 0,
904 	GATE(CLK_PMU1_WDTNS, "clk_pmu1_wdtns", "xin24m", 0,