1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/io.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/syscore_ops.h>
14 #include <dt-bindings/clock/rk3288-cru.h>
15 #include "clk.h"
16 #include <asm/psci.h>
17
18 #define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
19 #define RK3288_GRF_SOC_STATUS1 0x284
20
21 enum rk3288_variant {
22 RK3288_CRU,
23 RK3288W_CRU,
24 };
25
26 enum rk3288_plls {
27 apll, dpll, cpll, gpll, npll,
28 };
29
30 static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
31 RK3066_PLL_RATE(2208000000, 1, 92, 1),
32 RK3066_PLL_RATE(2184000000, 1, 91, 1),
33 RK3066_PLL_RATE(2160000000, 1, 90, 1),
34 RK3066_PLL_RATE(2136000000, 1, 89, 1),
35 RK3066_PLL_RATE(2112000000, 1, 88, 1),
36 RK3066_PLL_RATE(2088000000, 1, 87, 1),
37 RK3066_PLL_RATE(2064000000, 1, 86, 1),
38 RK3066_PLL_RATE(2040000000, 1, 85, 1),
39 RK3066_PLL_RATE(2016000000, 1, 84, 1),
40 RK3066_PLL_RATE(1992000000, 1, 83, 1),
41 RK3066_PLL_RATE(1968000000, 1, 82, 1),
42 RK3066_PLL_RATE(1944000000, 1, 81, 1),
43 RK3066_PLL_RATE(1920000000, 1, 80, 1),
44 RK3066_PLL_RATE(1896000000, 1, 79, 1),
45 RK3066_PLL_RATE(1872000000, 1, 78, 1),
46 RK3066_PLL_RATE(1848000000, 1, 77, 1),
47 RK3066_PLL_RATE(1824000000, 1, 76, 1),
48 RK3066_PLL_RATE(1800000000, 1, 75, 1),
49 RK3066_PLL_RATE(1776000000, 1, 74, 1),
50 RK3066_PLL_RATE(1752000000, 1, 73, 1),
51 RK3066_PLL_RATE(1728000000, 1, 72, 1),
52 RK3066_PLL_RATE(1704000000, 1, 71, 1),
53 RK3066_PLL_RATE(1680000000, 1, 70, 1),
54 RK3066_PLL_RATE(1656000000, 1, 69, 1),
55 RK3066_PLL_RATE(1632000000, 1, 68, 1),
56 RK3066_PLL_RATE(1608000000, 1, 67, 1),
57 RK3066_PLL_RATE(1560000000, 1, 65, 1),
58 RK3066_PLL_RATE(1512000000, 1, 63, 1),
59 RK3066_PLL_RATE(1488000000, 1, 62, 1),
60 RK3066_PLL_RATE(1464000000, 1, 61, 1),
61 RK3066_PLL_RATE(1440000000, 1, 60, 1),
62 RK3066_PLL_RATE(1416000000, 1, 59, 1),
63 RK3066_PLL_RATE(1392000000, 1, 58, 1),
64 RK3066_PLL_RATE(1368000000, 1, 57, 1),
65 RK3066_PLL_RATE(1344000000, 1, 56, 1),
66 RK3066_PLL_RATE(1320000000, 1, 55, 1),
67 RK3066_PLL_RATE(1296000000, 1, 54, 1),
68 RK3066_PLL_RATE(1272000000, 1, 53, 1),
69 RK3066_PLL_RATE(1248000000, 1, 52, 1),
70 RK3066_PLL_RATE(1224000000, 1, 51, 1),
71 RK3066_PLL_RATE(1200000000, 1, 50, 1),
72 RK3066_PLL_RATE(1188000000, 1, 99, 2),
73 RK3066_PLL_RATE(1176000000, 1, 49, 1),
74 RK3066_PLL_RATE(1128000000, 1, 47, 1),
75 RK3066_PLL_RATE(1104000000, 1, 46, 1),
76 RK3066_PLL_RATE(1008000000, 1, 84, 2),
77 RK3066_PLL_RATE( 912000000, 1, 76, 2),
78 RK3066_PLL_RATE( 891000000, 2, 297, 4),
79 RK3066_PLL_RATE( 888000000, 1, 74, 2),
80 RK3066_PLL_RATE( 816000000, 1, 68, 2),
81 RK3066_PLL_RATE( 798000000, 1, 133, 4),
82 RK3066_PLL_RATE( 792000000, 1, 66, 2),
83 RK3066_PLL_RATE( 768000000, 1, 64, 2),
84 RK3066_PLL_RATE( 742500000, 4, 495, 4),
85 RK3066_PLL_RATE( 696000000, 1, 58, 2),
86 RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1),
87 RK3066_PLL_RATE( 600000000, 1, 50, 2),
88 RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 1),
89 RK3066_PLL_RATE( 552000000, 1, 46, 2),
90 RK3066_PLL_RATE( 504000000, 1, 84, 4),
91 RK3066_PLL_RATE( 500000000, 1, 125, 6),
92 RK3066_PLL_RATE( 456000000, 1, 76, 4),
93 RK3066_PLL_RATE( 428000000, 1, 107, 6),
94 RK3066_PLL_RATE( 408000000, 1, 68, 4),
95 RK3066_PLL_RATE( 400000000, 1, 100, 6),
96 RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1),
97 RK3066_PLL_RATE( 384000000, 1, 64, 4),
98 RK3066_PLL_RATE( 360000000, 1, 60, 4),
99 RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1),
100 RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1),
101 RK3066_PLL_RATE( 312000000, 1, 52, 4),
102 RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1),
103 RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1),
104 RK3066_PLL_RATE( 300000000, 1, 75, 6),
105 RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1),
106 RK3066_PLL_RATE( 297000000, 1, 99, 8),
107 RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1),
108 RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1),
109 RK3066_PLL_RATE( 273600000, 1, 114, 10),
110 RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1),
111 RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1),
112 RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1),
113 RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1),
114 RK3066_PLL_RATE( 252000000, 1, 84, 8),
115 RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1),
116 RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1),
117 RK3066_PLL_RATE( 238000000, 1, 119, 12),
118 RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1),
119 RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1),
120 RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1),
121 RK3066_PLL_RATE( 195428571, 1, 114, 14),
122 RK3066_PLL_RATE( 160000000, 1, 80, 12),
123 RK3066_PLL_RATE( 157500000, 1, 105, 16),
124 RK3066_PLL_RATE( 148500000, 1, 99, 16),
125 RK3066_PLL_RATE( 126000000, 1, 84, 16),
126 { /* sentinel */ },
127 };
128
129 #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
130 #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
131 #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
132 #define RK3288_DIV_ACLK_CORE_MP_SHIFT 4
133 #define RK3288_DIV_L2RAM_MASK 0x7
134 #define RK3288_DIV_L2RAM_SHIFT 0
135 #define RK3288_DIV_ATCLK_MASK 0x1f
136 #define RK3288_DIV_ATCLK_SHIFT 4
137 #define RK3288_DIV_PCLK_DBGPRE_MASK 0x1f
138 #define RK3288_DIV_PCLK_DBGPRE_SHIFT 9
139
140 #define RK3288_CLKSEL0(_core_m0, _core_mp) \
141 { \
142 .reg = RK3288_CLKSEL_CON(0), \
143 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
144 RK3288_DIV_ACLK_CORE_M0_SHIFT) | \
145 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
146 RK3288_DIV_ACLK_CORE_MP_SHIFT), \
147 }
148 #define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre) \
149 { \
150 .reg = RK3288_CLKSEL_CON(37), \
151 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
152 RK3288_DIV_L2RAM_SHIFT) | \
153 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
154 RK3288_DIV_ATCLK_SHIFT) | \
155 HIWORD_UPDATE(_pclk_dbg_pre, \
156 RK3288_DIV_PCLK_DBGPRE_MASK, \
157 RK3288_DIV_PCLK_DBGPRE_SHIFT), \
158 }
159
160 #define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
161 { \
162 .prate = _prate, \
163 .divs = { \
164 RK3288_CLKSEL0(_core_m0, _core_mp), \
165 RK3288_CLKSEL37(_l2ram, _atclk, _pdbg), \
166 }, \
167 }
168
169 static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
170 RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
171 RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
172 RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
173 RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
174 RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
175 RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
176 RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
177 RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
178 RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
179 RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
180 RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
181 RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
182 RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
183 RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
184 };
185
186 static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
187 .core_reg[0] = RK3288_CLKSEL_CON(0),
188 .div_core_shift[0] = 8,
189 .div_core_mask[0] = 0x1f,
190 .num_cores = 1,
191 .mux_core_alt = 1,
192 .mux_core_main = 0,
193 .mux_core_shift = 15,
194 .mux_core_mask = 0x1,
195 };
196
197 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
198 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
199 PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
200
201 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
202 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
203 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
204 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };
205 PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
206
207 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
208 PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
209 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
210 PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
211 PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
212 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
213 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
214 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
215 PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
216 PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
217 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
218 PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
219 PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
220 PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
221 PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
222
223 PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" };
224 PNAME(mux_testout_src_p) = { "aclk_peri", "armclk", "aclk_vio0", "ddrphy",
225 "aclk_vcodec", "aclk_gpu", "sclk_rga", "aclk_cpu",
226 "xin24m", "xin27m", "xin32k", "clk_wifi",
227 "dclk_vop0", "dclk_vop1", "sclk_isp_jpe",
228 "sclk_isp" };
229
230 PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
231 "sclk_otgphy0_480m" };
232 PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
233 PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
234
235 static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
236 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
237 RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
238 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
239 RK3288_MODE_CON, 4, 5, 0, NULL),
240 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
241 RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
242 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
243 RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
244 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
245 RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
246 };
247
248 static struct clk_div_table div_hclk_cpu_t[] = {
249 { .val = 0, .div = 1 },
250 { .val = 1, .div = 2 },
251 { .val = 3, .div = 4 },
252 { /* sentinel */},
253 };
254
255 #define MFLAGS CLK_MUX_HIWORD_MASK
256 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
257 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
258 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
259
260 static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata =
261 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
262 RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);
263
264 static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata =
265 MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
266 RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);
267
268 static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata =
269 MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
270 RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);
271
272 static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata =
273 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
274 RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
275
276 static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata =
277 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
278 RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
279
280 static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata =
281 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
282 RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
283
284 static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata =
285 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
286 RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
287
288 static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata =
289 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
290 RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);
291
292 static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
293 /*
294 * Clock-Architecture Diagram 1
295 */
296
297 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
298 RK3288_CLKGATE_CON(0), 1, GFLAGS),
299 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
300 RK3288_CLKGATE_CON(0), 2, GFLAGS),
301
302 COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
303 RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
304 RK3288_CLKGATE_CON(12), 0, GFLAGS),
305 COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
306 RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
307 RK3288_CLKGATE_CON(12), 1, GFLAGS),
308 COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
309 RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
310 RK3288_CLKGATE_CON(12), 2, GFLAGS),
311 COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
312 RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
313 RK3288_CLKGATE_CON(12), 3, GFLAGS),
314 COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
315 RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
316 RK3288_CLKGATE_CON(12), 4, GFLAGS),
317 COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
318 RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
319 RK3288_CLKGATE_CON(12), 5, GFLAGS),
320 COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
321 RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
322 RK3288_CLKGATE_CON(12), 6, GFLAGS),
323 COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
324 RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
325 RK3288_CLKGATE_CON(12), 7, GFLAGS),
326 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
327 RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
328 RK3288_CLKGATE_CON(12), 8, GFLAGS),
329 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
330 RK3288_CLKGATE_CON(12), 9, GFLAGS),
331 GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
332 RK3288_CLKGATE_CON(12), 10, GFLAGS),
333 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
334 RK3288_CLKGATE_CON(12), 11, GFLAGS),
335
336 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
337 RK3288_CLKGATE_CON(0), 8, GFLAGS),
338 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
339 RK3288_CLKGATE_CON(0), 9, GFLAGS),
340 COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
341 RK3288_CLKSEL_CON(26), 2, 1, 0, 0,
342 ROCKCHIP_DDRCLK_SIP_V2),
343 COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
344 RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
345 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
346
347 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IS_CRITICAL,
348 RK3288_CLKGATE_CON(0), 10, GFLAGS),
349 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IS_CRITICAL,
350 RK3288_CLKGATE_CON(0), 11, GFLAGS),
351 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IS_CRITICAL,
352 RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
353 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
354 RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
355 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IS_CRITICAL,
356 RK3288_CLKGATE_CON(0), 3, GFLAGS),
357 COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IS_CRITICAL,
358 RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
359 RK3288_CLKGATE_CON(0), 5, GFLAGS),
360 COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IS_CRITICAL,
361 RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
362 RK3288_CLKGATE_CON(0), 4, GFLAGS),
363 GATE(0, "c2c_host", "aclk_cpu_src", 0,
364 RK3288_CLKGATE_CON(13), 8, GFLAGS),
365 COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0,
366 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
367 RK3288_CLKGATE_CON(5), 4, GFLAGS),
368 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
369 RK3288_CLKGATE_CON(0), 7, GFLAGS),
370
371 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
372
373 COMPOSITE(SCLK_I2S_SRC, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
374 RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
375 RK3288_CLKGATE_CON(4), 1, GFLAGS),
376 COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
377 RK3288_CLKSEL_CON(8), 0,
378 RK3288_CLKGATE_CON(4), 2, GFLAGS,
379 &rk3288_i2s_fracmux),
380 COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
381 RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
382 RK3288_CLKGATE_CON(4), 0, GFLAGS),
383 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
384 RK3288_CLKGATE_CON(4), 3, GFLAGS),
385
386 MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
387 RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
388 COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
389 RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
390 RK3288_CLKGATE_CON(4), 4, GFLAGS),
391 COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
392 RK3288_CLKSEL_CON(9), 0,
393 RK3288_CLKGATE_CON(4), 5, GFLAGS,
394 &rk3288_spdif_fracmux),
395 GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
396 RK3288_CLKGATE_CON(4), 6, GFLAGS),
397 COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
398 RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
399 RK3288_CLKGATE_CON(4), 7, GFLAGS),
400 COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
401 RK3288_CLKSEL_CON(41), 0,
402 RK3288_CLKGATE_CON(4), 8, GFLAGS,
403 &rk3288_spdif_8ch_fracmux),
404 GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
405 RK3288_CLKGATE_CON(4), 9, GFLAGS),
406
407 GATE(0, "sclk_acc_efuse", "xin24m", 0,
408 RK3288_CLKGATE_CON(0), 12, GFLAGS),
409
410 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
411 RK3288_CLKGATE_CON(1), 0, GFLAGS),
412 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
413 RK3288_CLKGATE_CON(1), 1, GFLAGS),
414 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
415 RK3288_CLKGATE_CON(1), 2, GFLAGS),
416 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
417 RK3288_CLKGATE_CON(1), 3, GFLAGS),
418 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
419 RK3288_CLKGATE_CON(1), 4, GFLAGS),
420 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
421 RK3288_CLKGATE_CON(1), 5, GFLAGS),
422
423 /*
424 * Clock-Architecture Diagram 2
425 */
426
427 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
428 RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
429 RK3288_CLKGATE_CON(3), 9, GFLAGS),
430 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
431 RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
432 RK3288_CLKGATE_CON(3), 11, GFLAGS),
433 MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,
434 RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),
435 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
436 RK3288_CLKGATE_CON(9), 0, GFLAGS),
437
438 FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 1, 4,
439 RK3288_CLKGATE_CON(3), 10, GFLAGS),
440
441 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
442 RK3288_CLKGATE_CON(9), 1, GFLAGS),
443
444 COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
445 RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
446 RK3288_CLKGATE_CON(3), 0, GFLAGS),
447 COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
448 RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
449 RK3288_CLKGATE_CON(3), 2, GFLAGS),
450
451 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
452 RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
453 RK3288_CLKGATE_CON(3), 5, GFLAGS),
454 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
455 RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
456 RK3288_CLKGATE_CON(3), 4, GFLAGS),
457
458 COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
459 RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
460 RK3288_CLKGATE_CON(3), 1, GFLAGS),
461 COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
462 RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
463 RK3288_CLKGATE_CON(3), 3, GFLAGS),
464
465 COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
466 RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
467 RK3288_CLKGATE_CON(3), 12, GFLAGS),
468 COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
469 RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
470 RK3288_CLKGATE_CON(3), 13, GFLAGS),
471
472 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
473 RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
474 RK3288_CLKGATE_CON(3), 14, GFLAGS),
475 COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
476 RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
477 RK3288_CLKGATE_CON(3), 15, GFLAGS),
478
479 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
480 RK3288_CLKGATE_CON(5), 12, GFLAGS),
481 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
482 RK3288_CLKGATE_CON(5), 11, GFLAGS),
483
484 COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
485 RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
486 RK3288_CLKGATE_CON(13), 13, GFLAGS),
487 DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
488 RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
489
490 COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
491 RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
492 RK3288_CLKGATE_CON(13), 14, GFLAGS),
493 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
494 RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
495 RK3288_CLKGATE_CON(13), 15, GFLAGS),
496
497 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
498 RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
499 RK3288_CLKGATE_CON(3), 7, GFLAGS),
500 COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
501 RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
502
503 DIV(PCLK_PD_ALIVE, "pclk_pd_alive", "gpll", CLK_IS_CRITICAL,
504 RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
505 COMPOSITE_NOMUX(PCLK_PD_PMU, "pclk_pd_pmu", "gpll", CLK_IS_CRITICAL,
506 RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
507 RK3288_CLKGATE_CON(5), 8, GFLAGS),
508
509 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
510 RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
511 RK3288_CLKGATE_CON(5), 7, GFLAGS),
512
513 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
514 RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
515 RK3288_CLKGATE_CON(2), 0, GFLAGS),
516 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
517 RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
518 RK3288_CLKGATE_CON(2), 3, GFLAGS),
519 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
520 RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
521 RK3288_CLKGATE_CON(2), 2, GFLAGS),
522 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
523 RK3288_CLKGATE_CON(2), 1, GFLAGS),
524
525 /*
526 * Clock-Architecture Diagram 3
527 */
528
529 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
530 RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
531 RK3288_CLKGATE_CON(2), 9, GFLAGS),
532 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
533 RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
534 RK3288_CLKGATE_CON(2), 10, GFLAGS),
535 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
536 RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
537 RK3288_CLKGATE_CON(2), 11, GFLAGS),
538
539 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
540 RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
541 RK3288_CLKGATE_CON(13), 0, GFLAGS),
542 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
543 RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
544 RK3288_CLKGATE_CON(13), 1, GFLAGS),
545 COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
546 RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
547 RK3288_CLKGATE_CON(13), 2, GFLAGS),
548 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
549 RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
550 RK3288_CLKGATE_CON(13), 3, GFLAGS),
551
552 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
553 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
554
555 MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1),
556 MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
557
558 MMC(SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1),
559 MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
560
561 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),
562 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),
563
564 COMPOSITE(SCLK_TSPOUT, "sclk_tspout", mux_tspout_p, 0,
565 RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
566 RK3288_CLKGATE_CON(4), 11, GFLAGS),
567 COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
568 RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
569 RK3288_CLKGATE_CON(4), 10, GFLAGS),
570
571 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
572 RK3288_CLKGATE_CON(13), 4, GFLAGS),
573 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
574 RK3288_CLKGATE_CON(13), 5, GFLAGS),
575 GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,
576 RK3288_CLKGATE_CON(13), 6, GFLAGS),
577 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
578 RK3288_CLKGATE_CON(13), 7, GFLAGS),
579
580 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
581 RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
582 RK3288_CLKGATE_CON(2), 7, GFLAGS),
583
584 MUX(SCLK_TESTOUT_SRC, "sclk_testout_src", mux_testout_src_p, 0,
585 RK3288_MISC_CON, 8, 4, MFLAGS),
586 COMPOSITE_NOMUX(SCLK_TESTOUT, "sclk_testout", "sclk_testout_src", 0,
587 RK3288_CLKSEL_CON(2), 8, 5, DFLAGS,
588 RK3288_CLKGATE_CON(4), 15, GFLAGS),
589
590 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
591 RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
592 RK3288_CLKGATE_CON(2), 8, GFLAGS),
593
594 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
595 RK3288_CLKGATE_CON(5), 13, GFLAGS),
596
597 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
598 RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
599 RK3288_CLKGATE_CON(5), 5, GFLAGS),
600 COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
601 RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
602 RK3288_CLKGATE_CON(5), 6, GFLAGS),
603
604 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
605 RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
606 RK3288_CLKGATE_CON(1), 8, GFLAGS),
607 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
608 RK3288_CLKSEL_CON(17), 0,
609 RK3288_CLKGATE_CON(1), 9, GFLAGS,
610 &rk3288_uart0_fracmux),
611 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
612 RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
613 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
614 RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
615 RK3288_CLKGATE_CON(1), 10, GFLAGS),
616 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
617 RK3288_CLKSEL_CON(18), 0,
618 RK3288_CLKGATE_CON(1), 11, GFLAGS,
619 &rk3288_uart1_fracmux),
620 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
621 RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
622 RK3288_CLKGATE_CON(1), 12, GFLAGS),
623 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
624 RK3288_CLKSEL_CON(19), 0,
625 RK3288_CLKGATE_CON(1), 13, GFLAGS,
626 &rk3288_uart2_fracmux),
627 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
628 RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
629 RK3288_CLKGATE_CON(1), 14, GFLAGS),
630 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
631 RK3288_CLKSEL_CON(20), 0,
632 RK3288_CLKGATE_CON(1), 15, GFLAGS,
633 &rk3288_uart3_fracmux),
634 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
635 RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
636 RK3288_CLKGATE_CON(2), 12, GFLAGS),
637 COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
638 RK3288_CLKSEL_CON(7), 0,
639 RK3288_CLKGATE_CON(2), 13, GFLAGS,
640 &rk3288_uart4_fracmux),
641
642 COMPOSITE(SCLK_MAC_PLL, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
643 RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
644 RK3288_CLKGATE_CON(2), 5, GFLAGS),
645 MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
646 RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
647 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
648 RK3288_CLKGATE_CON(5), 3, GFLAGS),
649 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
650 RK3288_CLKGATE_CON(5), 2, GFLAGS),
651 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
652 RK3288_CLKGATE_CON(5), 0, GFLAGS),
653 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
654 RK3288_CLKGATE_CON(5), 1, GFLAGS),
655
656 COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
657 RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
658 RK3288_CLKGATE_CON(2), 6, GFLAGS),
659 MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0,
660 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
661 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
662 RK3288_CLKSEL_CON(22), 7, IFLAGS),
663
664 GATE(0, "jtag", "ext_jtag", 0,
665 RK3288_CLKGATE_CON(4), 14, GFLAGS),
666
667 COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
668 RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
669 RK3288_CLKGATE_CON(5), 14, GFLAGS),
670 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
671 RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
672 RK3288_CLKGATE_CON(3), 6, GFLAGS),
673 GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
674 RK3288_CLKGATE_CON(13), 9, GFLAGS),
675 DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
676 RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
677 MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
678 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
679
680 /*
681 * Clock-Architecture Diagram 4
682 */
683
684 /* aclk_cpu gates */
685 GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
686 GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
687 GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
688 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(10), 12, GFLAGS),
689 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
690 GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
691 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
692 GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
693
694 /* hclk_cpu gates */
695 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
696 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
697 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
698 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
699 GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
700
701 /* pclk_cpu gates */
702 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
703 GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
704 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
705 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
706 GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
707 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
708 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
709 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
710 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
711 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
712 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
713 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
714 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(11), 11, GFLAGS),
715
716 /* ddrctrl [DDR Controller PHY clock] gates */
717 GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
718 GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
719
720 /* ddrphy gates */
721 GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
722 GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
723
724 /* aclk_peri gates */
725 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
726 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
727 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(7), 11, GFLAGS),
728 GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
729 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
730 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
731
732 /* hclk_peri gates */
733 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
734 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
735 GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
736 GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
737 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
738 GATE(HCLK_USB_PERI, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
739 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
740 GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
741 GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
742 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
743 GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
744 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
745 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
746 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
747 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
748 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
749 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
750 GATE(0, "pmu_hclk_otg0", "hclk_peri", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(7), 5, GFLAGS),
751
752 /* pclk_peri gates */
753 GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
754 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
755 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
756 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
757 GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
758 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
759 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
760 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
761 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
762 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
763 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
764 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
765 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
766 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
767 GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
768 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
769 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
770
771 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
772 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
773 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
774 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
775 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
776
777 /* sclk_gpu gates */
778 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
779
780 /* pclk_pd_alive gates */
781 GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
782 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
783 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
784 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
785 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
786 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
787 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
788 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
789 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
790 GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(14), 12, GFLAGS),
791
792 /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
793 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
794
795 /* pclk_pd_pmu gates */
796 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
797 GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
798 GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(17), 2, GFLAGS),
799 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
800 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
801
802 /* hclk_vio gates */
803 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
804 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
805 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
806 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
807 GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(15), 10, GFLAGS),
808 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
809 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
810 GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
811 GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
812 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
813 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
814 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
815 GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
816 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
817 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
818 GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
819
820 /* aclk_vio0 gates */
821 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
822 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
823 GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(15), 11, GFLAGS),
824 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
825
826 /* aclk_vio1 gates */
827 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
828 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
829 GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(15), 12, GFLAGS),
830
831 /* aclk_rga_pre gates */
832 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
833 GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(15), 13, GFLAGS),
834
835 /*
836 * Other ungrouped clocks.
837 */
838
839 GATE(PCLK_VIP_IN, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
840 INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
841 GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
842 INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
843
844 GATE(SCLK_HSADC0_TSP, "clk_hsadc0_tsp", "ext_hsadc0_tsp", 0, RK3288_CLKGATE_CON(8), 9, GFLAGS),
845 GATE(SCLK_HSADC1_TSP, "clk_hsadc1_tsp", "ext_hsadc0_tsp", 0, RK3288_CLKGATE_CON(8), 10, GFLAGS),
846 GATE(SCLK_27M_TSP, "clk_27m_tsp", "ext_27m_tsp", 0, RK3288_CLKGATE_CON(8), 11, GFLAGS),
847 };
848
849 static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
850 DIV(0, "hclk_vio", "aclk_vio1", 0,
851 RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
852 };
853
854 static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
855 DIV(0, "hclk_vio", "aclk_vio0", 0,
856 RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
857 };
858
859 static void __iomem *rk3288_cru_base;
860
861 /*
862 * Some CRU registers will be reset in maskrom when the system
863 * wakes up from fastboot.
864 * So save them before suspend, restore them after resume.
865 */
866 static const int rk3288_saved_cru_reg_ids[] = {
867 RK3288_MODE_CON,
868 RK3288_CLKSEL_CON(0),
869 RK3288_CLKSEL_CON(1),
870 RK3288_CLKSEL_CON(10),
871 RK3288_CLKSEL_CON(33),
872 RK3288_CLKSEL_CON(37),
873
874 /* We turn aclk_dmac1 on for suspend; this will restore it */
875 RK3288_CLKGATE_CON(10),
876 };
877
878 static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
879
rk3288_clk_suspend(void)880 static int rk3288_clk_suspend(void)
881 {
882 int i, reg_id;
883
884 for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
885 reg_id = rk3288_saved_cru_reg_ids[i];
886
887 rk3288_saved_cru_regs[i] =
888 readl_relaxed(rk3288_cru_base + reg_id);
889 }
890
891 /*
892 * Going into deep sleep (specifically setting PMU_CLR_DMA in
893 * RK3288_PMU_PWRMODE_CON1) appears to fail unless
894 * "aclk_dmac1" is on.
895 */
896 writel_relaxed(1 << (12 + 16),
897 rk3288_cru_base + RK3288_CLKGATE_CON(10));
898
899 /*
900 * Switch PLLs other than DPLL (for SDRAM) to slow mode to
901 * avoid crashes on resume. The Mask ROM on the system will
902 * put APLL, CPLL, and GPLL into slow mode at resume time
903 * anyway (which is why we restore them), but we might not
904 * even make it to the Mask ROM if this isn't done at suspend
905 * time.
906 *
907 * NOTE: only APLL truly matters here, but we'll do them all.
908 */
909
910 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
911
912 return 0;
913 }
914
rk3288_clk_resume(void)915 static void rk3288_clk_resume(void)
916 {
917 int i, reg_id;
918
919 for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
920 reg_id = rk3288_saved_cru_reg_ids[i];
921
922 writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
923 rk3288_cru_base + reg_id);
924 }
925 }
926
rk3288_clk_shutdown(void)927 static void rk3288_clk_shutdown(void)
928 {
929 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
930 }
931
932 static struct syscore_ops rk3288_clk_syscore_ops = {
933 .suspend = rk3288_clk_suspend,
934 .resume = rk3288_clk_resume,
935 };
936
rk3288_dump_cru(void)937 static void rk3288_dump_cru(void)
938 {
939 if (rk3288_cru_base) {
940 pr_warn("CRU:\n");
941 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
942 32, 4, rk3288_cru_base,
943 0x21c, false);
944 }
945 }
946
rk3288_common_init(struct device_node * np,enum rk3288_variant soc)947 static void __init rk3288_common_init(struct device_node *np,
948 enum rk3288_variant soc)
949 {
950 struct rockchip_clk_provider *ctx;
951 struct clk **clks;
952
953 rk3288_cru_base = of_iomap(np, 0);
954 if (!rk3288_cru_base) {
955 pr_err("%s: could not map cru region\n", __func__);
956 return;
957 }
958
959 ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
960 if (IS_ERR(ctx)) {
961 pr_err("%s: rockchip clk init failed\n", __func__);
962 iounmap(rk3288_cru_base);
963 return;
964 }
965 clks = ctx->clk_data.clks;
966
967 rockchip_clk_register_plls(ctx, rk3288_pll_clks,
968 ARRAY_SIZE(rk3288_pll_clks),
969 RK3288_GRF_SOC_STATUS1);
970 rockchip_clk_register_branches(ctx, rk3288_clk_branches,
971 ARRAY_SIZE(rk3288_clk_branches));
972
973 if (soc == RK3288W_CRU)
974 rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
975 ARRAY_SIZE(rk3288w_hclkvio_branch));
976 else
977 rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
978 ARRAY_SIZE(rk3288_hclkvio_branch));
979
980 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
981 2, clks[PLL_APLL], clks[PLL_GPLL],
982 &rk3288_cpuclk_data, rk3288_cpuclk_rates,
983 ARRAY_SIZE(rk3288_cpuclk_rates));
984
985 rockchip_register_softrst(np, 12,
986 rk3288_cru_base + RK3288_SOFTRST_CON(0),
987 ROCKCHIP_SOFTRST_HIWORD_MASK);
988
989 rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST,
990 rk3288_clk_shutdown);
991
992 if (!psci_smp_available())
993 register_syscore_ops(&rk3288_clk_syscore_ops);
994
995 rockchip_clk_of_add_provider(np, ctx);
996
997 if (!rk_dump_cru)
998 rk_dump_cru = rk3288_dump_cru;
999 }
1000
rk3288_clk_init(struct device_node * np)1001 static void __init rk3288_clk_init(struct device_node *np)
1002 {
1003 rk3288_common_init(np, RK3288_CRU);
1004 }
1005 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
1006
rk3288w_clk_init(struct device_node * np)1007 static void __init rk3288w_clk_init(struct device_node *np)
1008 {
1009 rk3288_common_init(np, RK3288W_CRU);
1010 }
1011 CLK_OF_DECLARE(rk3288w_cru, "rockchip,rk3288w-cru", rk3288w_clk_init);
1012
1013 struct clk_rk3288_inits {
1014 void (*inits)(struct device_node *np);
1015 };
1016
1017 static const struct clk_rk3288_inits clk_rk3288_init = {
1018 .inits = rk3288_clk_init,
1019 };
1020
1021 static const struct clk_rk3288_inits clk_rk3288w_init = {
1022 .inits = rk3288w_clk_init,
1023 };
1024
1025 static const struct of_device_id clk_rk3288_match_table[] = {
1026 {
1027 .compatible = "rockchip,rk3288-cru",
1028 .data = &clk_rk3288_init,
1029 }, {
1030 .compatible = "rockchip,rk3288w-cru",
1031 .data = &clk_rk3288w_init,
1032 },
1033 { }
1034 };
1035 MODULE_DEVICE_TABLE(of, clk_rk3288_match_table);
1036
clk_rk3288_probe(struct platform_device * pdev)1037 static int __init clk_rk3288_probe(struct platform_device *pdev)
1038 {
1039 struct device_node *np = pdev->dev.of_node;
1040 const struct of_device_id *match;
1041 const struct clk_rk3288_inits *init_data;
1042
1043 match = of_match_device(clk_rk3288_match_table, &pdev->dev);
1044 if (!match || !match->data)
1045 return -EINVAL;
1046
1047 init_data = match->data;
1048 if (init_data->inits)
1049 init_data->inits(np);
1050
1051 return 0;
1052 }
1053
1054 static struct platform_driver clk_rk3288_driver = {
1055 .driver = {
1056 .name = "clk-rk3288",
1057 .of_match_table = clk_rk3288_match_table,
1058 },
1059 };
1060 builtin_platform_driver_probe(clk_rk3288_driver, clk_rk3288_probe);
1061
1062 MODULE_DESCRIPTION("Rockchip RK3288 Clock Driver");
1063 MODULE_LICENSE("GPL");
1064