1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6/dts-v1/; 7 8#include "rv1109.dtsi" 9#include <dt-bindings/display/media-bus-format.h> 10 11/ { 12 model = "Rockchip RV1109 FPGA Board"; 13 compatible = "rockchip,rv1109-fpga", "rockchip,rv1109"; 14 15 memory@0 { 16 device_type = "memory"; 17 reg = <0x00000000 0x10000000>; 18 }; 19 20 chosen { 21 bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 initrd=0x9000000,0xb05e7 init=/init"; 22 }; 23 24 panel: panel { 25 compatible = "simple-panel"; 26 bus-format = <MEDIA_BUS_FMT_RGB888_1X24>; 27 status = "okay"; 28 29 display-timings { 30 native-mode = <&kd050fwfba002_timing>; 31 32 kd050fwfba002_timing: timing0 { 33 clock-frequency = <13500000>; 34 hactive = <800>; 35 vactive = <1280>; 36 hback-porch = <24>; 37 hfront-porch = <24>; 38 vback-porch = <4>; 39 vfront-porch = <2>; 40 hsync-len = <16>; 41 vsync-len = <2>; 42 hsync-active = <0>; 43 vsync-active = <0>; 44 de-active = <0>; 45 pixelclk-active = <0>; 46 }; 47 }; 48 49 port { 50 panel_in_rgb: endpoint { 51 remote-endpoint = <&rgb_out_panel>; 52 }; 53 }; 54 }; 55}; 56 57&display_subsystem { 58 status = "okay"; 59}; 60 61&fiq_debugger { 62 rockchip,baudrate = <115200>; 63 status = "okay"; 64}; 65 66&mpp_srv { 67 status = "okay"; 68}; 69 70&rgb { 71 status = "okay"; 72 ports { 73 port@1 { 74 reg = <1>; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 rgb_out_panel: endpoint@0 { 79 reg = <0>; 80 remote-endpoint = <&panel_in_rgb>; 81 }; 82 }; 83 }; 84}; 85 86&rkvenc { 87 status = "okay"; 88}; 89 90&rkvenc_mmu { 91 status = "okay"; 92}; 93 94&uart2 { 95 clocks = <&xin24m>, <&xin24m>; 96}; 97 98&vop { 99 status = "okay"; 100}; 101 102&vop_mmu { 103 status = "okay"; 104}; 105