1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/clock/rk3368-cru.h>
14 #include "clk.h"
15
16 #define RK3368_GRF_SOC_STATUS0 0x480
17
18 enum rk3368_plls {
19 apllb, aplll, dpll, cpll, gpll, npll,
20 };
21
22 static struct rockchip_pll_rate_table rk3368_pll_rates[] = {
23 RK3066_PLL_RATE(2208000000, 1, 92, 1),
24 RK3066_PLL_RATE(2184000000, 1, 91, 1),
25 RK3066_PLL_RATE(2160000000, 1, 90, 1),
26 RK3066_PLL_RATE(2136000000, 1, 89, 1),
27 RK3066_PLL_RATE(2112000000, 1, 88, 1),
28 RK3066_PLL_RATE(2088000000, 1, 87, 1),
29 RK3066_PLL_RATE(2064000000, 1, 86, 1),
30 RK3066_PLL_RATE(2040000000, 1, 85, 1),
31 RK3066_PLL_RATE(2016000000, 1, 84, 1),
32 RK3066_PLL_RATE(1992000000, 1, 83, 1),
33 RK3066_PLL_RATE(1968000000, 1, 82, 1),
34 RK3066_PLL_RATE(1944000000, 1, 81, 1),
35 RK3066_PLL_RATE(1920000000, 1, 80, 1),
36 RK3066_PLL_RATE(1896000000, 1, 79, 1),
37 RK3066_PLL_RATE(1872000000, 1, 78, 1),
38 RK3066_PLL_RATE(1848000000, 1, 77, 1),
39 RK3066_PLL_RATE(1824000000, 1, 76, 1),
40 RK3066_PLL_RATE(1800000000, 1, 75, 1),
41 RK3066_PLL_RATE(1776000000, 1, 74, 1),
42 RK3066_PLL_RATE(1752000000, 1, 73, 1),
43 RK3066_PLL_RATE(1728000000, 1, 72, 1),
44 RK3066_PLL_RATE(1704000000, 1, 71, 1),
45 RK3066_PLL_RATE(1680000000, 1, 70, 1),
46 RK3066_PLL_RATE(1656000000, 1, 69, 1),
47 RK3066_PLL_RATE(1632000000, 1, 68, 1),
48 RK3066_PLL_RATE(1608000000, 1, 67, 1),
49 RK3066_PLL_RATE(1560000000, 1, 65, 1),
50 RK3066_PLL_RATE(1512000000, 1, 63, 1),
51 RK3066_PLL_RATE(1488000000, 1, 62, 1),
52 RK3066_PLL_RATE(1464000000, 1, 61, 1),
53 RK3066_PLL_RATE(1440000000, 1, 60, 1),
54 RK3066_PLL_RATE(1416000000, 1, 59, 1),
55 RK3066_PLL_RATE(1392000000, 1, 58, 1),
56 RK3066_PLL_RATE(1368000000, 1, 57, 1),
57 RK3066_PLL_RATE(1344000000, 1, 56, 1),
58 RK3066_PLL_RATE(1320000000, 1, 55, 1),
59 RK3066_PLL_RATE(1296000000, 1, 54, 1),
60 RK3066_PLL_RATE(1272000000, 1, 53, 1),
61 RK3066_PLL_RATE(1248000000, 1, 52, 1),
62 RK3066_PLL_RATE(1224000000, 1, 51, 1),
63 RK3066_PLL_RATE(1200000000, 1, 50, 1),
64 RK3066_PLL_RATE(1176000000, 1, 49, 1),
65 RK3066_PLL_RATE(1128000000, 1, 47, 1),
66 RK3066_PLL_RATE(1104000000, 1, 46, 1),
67 RK3066_PLL_RATE(1008000000, 1, 84, 2),
68 RK3066_PLL_RATE( 912000000, 1, 76, 2),
69 RK3066_PLL_RATE( 888000000, 1, 74, 2),
70 RK3066_PLL_RATE( 816000000, 1, 68, 2),
71 RK3066_PLL_RATE( 792000000, 1, 66, 2),
72 RK3066_PLL_RATE( 696000000, 1, 58, 2),
73 RK3066_PLL_RATE( 672000000, 1, 56, 2),
74 RK3066_PLL_RATE( 648000000, 1, 54, 2),
75 RK3066_PLL_RATE( 624000000, 1, 52, 2),
76 RK3066_PLL_RATE( 600000000, 1, 50, 2),
77 RK3066_PLL_RATE( 576000000, 1, 48, 2),
78 RK3066_PLL_RATE( 552000000, 1, 46, 2),
79 RK3066_PLL_RATE( 528000000, 1, 88, 4),
80 RK3066_PLL_RATE( 504000000, 1, 84, 4),
81 RK3066_PLL_RATE( 480000000, 1, 80, 4),
82 RK3066_PLL_RATE( 456000000, 1, 76, 4),
83 RK3066_PLL_RATE( 408000000, 1, 68, 4),
84 RK3066_PLL_RATE( 312000000, 1, 52, 4),
85 RK3066_PLL_RATE( 252000000, 1, 84, 8),
86 RK3066_PLL_RATE( 216000000, 1, 72, 8),
87 RK3066_PLL_RATE( 126000000, 2, 84, 8),
88 RK3066_PLL_RATE( 48000000, 2, 32, 8),
89 { /* sentinel */ },
90 };
91
92 static struct rockchip_pll_rate_table rk3368_npll_rates[] = {
93 RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32),
94 RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
95 RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
96 RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
97 RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
98 RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
99 RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
100 RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
101 RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
102 RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
103 RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
104 RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
105 RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
106 RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
107 RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
108 };
109
110 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
111 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
112 PNAME(mux_cs_src_p) = { "apllb_cs", "aplll_cs", "gpll_cs"};
113 PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" };
114
115 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
116 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "dummy_npll" };
117 PNAME(mux_pll_src_dmycpll_dmygpll_npll_p) = { "dummy_cpll", "dummy_gpll", "npll" };
118 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "dummy_npll", "cpll", "gpll" };
119 PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
120 PNAME(mux_pll_src_cpll_gpll_usb_usb_p) = { "cpll", "gpll", "usbphy_480m",
121 "usbphy_480m" };
122 PNAME(mux_pll_src_cpll_gpll_usb_npll_p) = { "cpll", "gpll", "usbphy_480m",
123 "dummy_npll" };
124 PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "dummy_npll", "dummy_npll" };
125 PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "dummy_npll",
126 "usbphy_480m" };
127
128 PNAME(mux_i2s_8ch_pre_p) = { "i2s_8ch_src", "i2s_8ch_frac",
129 "ext_i2s", "xin12m" };
130 PNAME(mux_i2s_8ch_clkout_p) = { "i2s_8ch_pre", "xin12m" };
131 PNAME(mux_i2s_2ch_p) = { "i2s_2ch_src", "i2s_2ch_frac",
132 "dummy", "xin12m" };
133 PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac",
134 "ext_i2s", "xin12m" };
135 PNAME(mux_edp_24m_p) = { "xin24m", "dummy" };
136 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
137 PNAME(mux_usbphy480m_p) = { "usbotg_out", "xin24m" };
138 PNAME(mux_hsic_usbphy480m_p) = { "usbotg_out", "dummy" };
139 PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy_480m" };
140 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
141 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
142 PNAME(mux_uart2_p) = { "uart2_src", "xin24m" };
143 PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
144 PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
145 PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
146 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "usbphy_480m", "xin24m" };
147
148 static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = {
149 [apllb] = PLL(pll_rk3066, PLL_APLLB, "apllb", mux_pll_p, 0, RK3368_PLL_CON(0),
150 RK3368_PLL_CON(3), 8, 1, 0, rk3368_pll_rates),
151 [aplll] = PLL(pll_rk3066, PLL_APLLL, "aplll", mux_pll_p, 0, RK3368_PLL_CON(4),
152 RK3368_PLL_CON(7), 8, 0, 0, rk3368_pll_rates),
153 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
154 RK3368_PLL_CON(11), 8, 2, 0, NULL),
155 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
156 RK3368_PLL_CON(15), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
157 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
158 RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
159 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
160 RK3368_PLL_CON(23), 8, 5, 0, rk3368_npll_rates),
161 };
162
163 static struct clk_div_table div_ddrphy_t[] = {
164 { .val = 0, .div = 1 },
165 { .val = 1, .div = 2 },
166 { .val = 3, .div = 4 },
167 { /* sentinel */ },
168 };
169
170 #define MFLAGS CLK_MUX_HIWORD_MASK
171 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
172 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
173 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
174
175 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
176 .core_reg[0] = RK3368_CLKSEL_CON(0),
177 .div_core_shift[0] = 0,
178 .div_core_mask[0] = 0x1f,
179 .num_cores = 1,
180 .mux_core_alt = 1,
181 .mux_core_main = 0,
182 .mux_core_shift = 7,
183 .mux_core_mask = 0x1,
184 };
185
186 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
187 .core_reg[0] = RK3368_CLKSEL_CON(2),
188 .div_core_shift[0] = 0,
189 .mux_core_alt = 1,
190 .num_cores = 1,
191 .mux_core_main = 0,
192 .div_core_mask[0] = 0x1f,
193 .mux_core_shift = 7,
194 .mux_core_mask = 0x1,
195 };
196
197 #define RK3368_DIV_ACLKM_MASK 0x1f
198 #define RK3368_DIV_ACLKM_SHIFT 8
199 #define RK3368_DIV_ATCLK_MASK 0x1f
200 #define RK3368_DIV_ATCLK_SHIFT 0
201 #define RK3368_DIV_PCLK_DBG_MASK 0x1f
202 #define RK3368_DIV_PCLK_DBG_SHIFT 8
203
204 #define RK3368_CLKSEL0(_offs, _aclkm) \
205 { \
206 .reg = RK3368_CLKSEL_CON(0 + _offs), \
207 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
208 RK3368_DIV_ACLKM_SHIFT), \
209 }
210 #define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \
211 { \
212 .reg = RK3368_CLKSEL_CON(1 + _offs), \
213 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
214 RK3368_DIV_ATCLK_SHIFT) | \
215 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
216 RK3368_DIV_PCLK_DBG_SHIFT), \
217 }
218
219 /* cluster_b: aclkm in clksel0, rest in clksel1 */
220 #define RK3368_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
221 { \
222 .prate = _prate, \
223 .divs = { \
224 RK3368_CLKSEL0(0, _aclkm), \
225 RK3368_CLKSEL1(0, _atclk, _pdbg), \
226 }, \
227 }
228
229 /* cluster_l: aclkm in clksel2, rest in clksel3 */
230 #define RK3368_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
231 { \
232 .prate = _prate, \
233 .divs = { \
234 RK3368_CLKSEL0(2, _aclkm), \
235 RK3368_CLKSEL1(2, _atclk, _pdbg), \
236 }, \
237 }
238
239 static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
240 RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
241 RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
242 RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
243 RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
244 RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
245 RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
246 RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2),
247 RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
248 RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
249 RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
250 };
251
252 static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
253 RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
254 RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
255 RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
256 RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
257 RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
258 RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
259 RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2),
260 RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
261 RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
262 RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
263 };
264
265 static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
266 MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
267 RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
268
269 static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
270 MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
271 RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
272
273 static struct rockchip_clk_branch rk3368_i2s_2ch_fracmux __initdata =
274 MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
275 RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
276
277 static struct rockchip_clk_branch rk3368_uart0_fracmux __initdata =
278 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
279 RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
280
281 static struct rockchip_clk_branch rk3368_uart1_fracmux __initdata =
282 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
283 RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
284
285 static struct rockchip_clk_branch rk3368_uart3_fracmux __initdata =
286 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
287 RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
288
289 static struct rockchip_clk_branch rk3368_uart4_fracmux __initdata =
290 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
291 RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
292
293 static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
294 /*
295 * Clock-Architecture Diagram 2
296 */
297
298 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
299
300 MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT,
301 RK3368_CLKSEL_CON(13), 8, 1, MFLAGS),
302
303 GATE(0, "apllb_core", "apllb", CLK_IGNORE_UNUSED,
304 RK3368_CLKGATE_CON(0), 0, GFLAGS),
305 GATE(0, "gpllb_core", "gpll", CLK_IGNORE_UNUSED,
306 RK3368_CLKGATE_CON(0), 1, GFLAGS),
307
308 GATE(0, "aplll_core", "aplll", CLK_IGNORE_UNUSED,
309 RK3368_CLKGATE_CON(0), 4, GFLAGS),
310 GATE(0, "gplll_core", "gpll", CLK_IGNORE_UNUSED,
311 RK3368_CLKGATE_CON(0), 5, GFLAGS),
312
313 DIV(0, "aclkm_core_b", "armclkb", 0,
314 RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
315 DIV(0, "atclk_core_b", "armclkb", 0,
316 RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
317 DIV(0, "pclk_dbg_b", "armclkb", 0,
318 RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
319
320 DIV(0, "aclkm_core_l", "armclkl", 0,
321 RK3368_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
322 DIV(0, "atclk_core_l", "armclkl", 0,
323 RK3368_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
324 DIV(0, "pclk_dbg_l", "armclkl", 0,
325 RK3368_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
326
327 GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
328 RK3368_CLKGATE_CON(0), 9, GFLAGS),
329 GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
330 RK3368_CLKGATE_CON(0), 10, GFLAGS),
331 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
332 RK3368_CLKGATE_CON(0), 8, GFLAGS),
333 COMPOSITE_NOGATE(0, "sclk_cs_pre", mux_cs_src_p, CLK_IGNORE_UNUSED,
334 RK3368_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
335 COMPOSITE_NOMUX(0, "clkin_trace", "sclk_cs_pre", CLK_IGNORE_UNUSED,
336 RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
337 RK3368_CLKGATE_CON(0), 13, GFLAGS),
338
339 COMPOSITE(ACLK_CCI_PRE, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
340 RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
341 RK3368_CLKGATE_CON(0), 12, GFLAGS),
342 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
343
344 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
345 RK3368_CLKGATE_CON(1), 8, GFLAGS),
346 GATE(0, "gpll_ddr", "gpll", 0,
347 RK3368_CLKGATE_CON(1), 9, GFLAGS),
348 COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
349 RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
350
351 FACTOR_GATE(0, "sclk_ddr", "ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
352 RK3368_CLKGATE_CON(6), 14, GFLAGS),
353 GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED,
354 RK3368_CLKGATE_CON(6), 15, GFLAGS),
355
356 GATE(0, "gpll_aclk_bus", "gpll", CLK_IS_CRITICAL,
357 RK3368_CLKGATE_CON(1), 10, GFLAGS),
358 GATE(0, "cpll_aclk_bus", "cpll", CLK_IS_CRITICAL,
359 RK3368_CLKGATE_CON(1), 11, GFLAGS),
360 COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IS_CRITICAL,
361 RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS),
362
363 GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IS_CRITICAL,
364 RK3368_CLKGATE_CON(1), 0, GFLAGS),
365 COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IS_CRITICAL,
366 RK3368_CLKSEL_CON(8), 12, 3, DFLAGS,
367 RK3368_CLKGATE_CON(1), 2, GFLAGS),
368 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IS_CRITICAL,
369 RK3368_CLKSEL_CON(8), 8, 2, DFLAGS,
370 RK3368_CLKGATE_CON(1), 1, GFLAGS),
371 COMPOSITE_NOMUX(0, "sclk_crypto", "aclk_bus_src", 0,
372 RK3368_CLKSEL_CON(10), 14, 2, DFLAGS,
373 RK3368_CLKGATE_CON(7), 2, GFLAGS),
374
375 COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
376 RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS,
377 RK3368_CLKGATE_CON(1), 3, GFLAGS),
378 /*
379 * stclk_mcu is listed as child of fclk_mcu_src in diagram 5,
380 * but stclk_mcu has an additional own divider in diagram 2
381 */
382 COMPOSITE_NOMUX(0, "stclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED,
383 RK3368_CLKSEL_CON(12), 8, 3, DFLAGS,
384 RK3368_CLKGATE_CON(13), 13, GFLAGS),
385
386 COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
387 RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
388 RK3368_CLKGATE_CON(6), 1, GFLAGS),
389 COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
390 RK3368_CLKSEL_CON(28), 0,
391 RK3368_CLKGATE_CON(6), 2, GFLAGS,
392 &rk3368_i2s_8ch_fracmux),
393 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
394 RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
395 RK3368_CLKGATE_CON(6), 0, GFLAGS),
396 GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
397 RK3368_CLKGATE_CON(6), 3, GFLAGS),
398 COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
399 RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
400 RK3368_CLKGATE_CON(6), 4, GFLAGS),
401 COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
402 RK3368_CLKSEL_CON(32), 0,
403 RK3368_CLKGATE_CON(6), 5, GFLAGS,
404 &rk3368_spdif_8ch_fracmux),
405 GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
406 RK3368_CLKGATE_CON(6), 6, GFLAGS),
407 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
408 RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
409 RK3368_CLKGATE_CON(5), 13, GFLAGS),
410 COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
411 RK3368_CLKSEL_CON(54), 0,
412 RK3368_CLKGATE_CON(5), 14, GFLAGS,
413 &rk3368_i2s_2ch_fracmux),
414 GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
415 RK3368_CLKGATE_CON(5), 15, GFLAGS),
416
417 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
418 RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
419 RK3368_CLKGATE_CON(6), 12, GFLAGS),
420 GATE(0, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
421 RK3368_CLKGATE_CON(13), 7, GFLAGS),
422
423 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
424 RK3368_CLKSEL_CON(35), 12, 1, MFLAGS),
425 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
426 RK3368_CLKSEL_CON(37), 0, 7, DFLAGS,
427 RK3368_CLKGATE_CON(2), 4, GFLAGS),
428 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
429 RK3368_CLKSEL_CON(37), 8, 1, MFLAGS),
430
431 /*
432 * Clock-Architecture Diagram 3
433 */
434
435 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
436 RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
437 RK3368_CLKGATE_CON(4), 6, GFLAGS),
438 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
439 RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
440 RK3368_CLKGATE_CON(4), 7, GFLAGS),
441
442 /*
443 * We use aclk_vdpu by default ---GRF_SOC_CON0[7] setting in system,
444 * so we ignore the mux and make clocks nodes as following,
445 */
446 FACTOR_GATE(0, "hclk_video_pre", "aclk_vdpu", 0, 1, 4,
447 RK3368_CLKGATE_CON(4), 8, GFLAGS),
448
449 COMPOSITE(0, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
450 RK3368_CLKSEL_CON(17), 6, 2, MFLAGS, 0, 5, DFLAGS,
451 RK3368_CLKGATE_CON(5), 1, GFLAGS),
452 COMPOSITE(0, "sclk_hevc_core_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
453 RK3368_CLKSEL_CON(17), 14, 2, MFLAGS, 8, 5, DFLAGS,
454 RK3368_CLKGATE_CON(5), 2, GFLAGS),
455
456 COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb_p, CLK_IGNORE_UNUSED,
457 RK3368_CLKSEL_CON(19), 6, 2, MFLAGS, 0, 5, DFLAGS,
458 RK3368_CLKGATE_CON(4), 0, GFLAGS),
459 DIV(0, "hclk_vio", "aclk_vio0", 0,
460 RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
461
462 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
463 RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
464 RK3368_CLKGATE_CON(4), 3, GFLAGS),
465 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
466 RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
467 RK3368_CLKGATE_CON(4), 4, GFLAGS),
468
469 COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT,
470 RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
471 RK3368_CLKGATE_CON(4), 1, GFLAGS),
472
473 GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
474 RK3368_CLKGATE_CON(4), 2, GFLAGS),
475
476 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
477 RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS,
478 RK3368_CLKGATE_CON(4), 9, GFLAGS),
479
480 GATE(0, "pclk_isp_in", "ext_isp", 0,
481 RK3368_CLKGATE_CON(17), 2, GFLAGS),
482 INVERTER(PCLK_ISP, "pclk_isp", "pclk_isp_in",
483 RK3368_CLKSEL_CON(21), 6, IFLAGS),
484
485 GATE(0, "pclk_vip_in", "ext_vip", 0,
486 RK3368_CLKGATE_CON(16), 13, GFLAGS),
487 INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in",
488 RK3368_CLKSEL_CON(21), 13, IFLAGS),
489
490 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
491 RK3368_CLKGATE_CON(4), 13, GFLAGS),
492 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
493 RK3368_CLKGATE_CON(4), 12, GFLAGS),
494
495 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
496 RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
497 RK3368_CLKGATE_CON(4), 5, GFLAGS),
498 COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
499 RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
500
501 COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
502 RK3368_CLKSEL_CON(23), 8, 1, MFLAGS,
503 RK3368_CLKGATE_CON(5), 4, GFLAGS),
504 COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
505 RK3368_CLKSEL_CON(23), 6, 2, MFLAGS, 0, 6, DFLAGS,
506 RK3368_CLKGATE_CON(5), 3, GFLAGS),
507
508 COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
509 RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS,
510 RK3368_CLKGATE_CON(5), 5, GFLAGS),
511
512 DIV(0, "pclk_pd_alive", "gpll", CLK_IS_CRITICAL,
513 RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
514
515 /* sclk_timer has a gate in the sgrf */
516
517 COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IS_CRITICAL,
518 RK3368_CLKSEL_CON(10), 0, 5, DFLAGS,
519 RK3368_CLKGATE_CON(7), 9, GFLAGS),
520 GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
521 RK3368_CLKGATE_CON(7), 3, GFLAGS),
522 COMPOSITE(0, "sclk_gpu_core_src", mux_pll_src_cpll_gpll_usb_npll_p, 0,
523 RK3368_CLKSEL_CON(14), 6, 2, MFLAGS, 0, 5, DFLAGS,
524 RK3368_CLKGATE_CON(4), 11, GFLAGS),
525 MUX(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
526 RK3368_CLKSEL_CON(14), 14, 1, MFLAGS),
527 COMPOSITE_NOMUX(0, "aclk_gpu_mem_pre", "aclk_gpu_src", 0,
528 RK3368_CLKSEL_CON(14), 8, 5, DFLAGS,
529 RK3368_CLKGATE_CON(5), 8, GFLAGS),
530 COMPOSITE_NOMUX(0, "aclk_gpu_cfg_pre", "aclk_gpu_src", 0,
531 RK3368_CLKSEL_CON(16), 8, 5, DFLAGS,
532 RK3368_CLKGATE_CON(5), 9, GFLAGS),
533 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
534 RK3368_CLKGATE_CON(7), 11, GFLAGS),
535
536 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
537 RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS,
538 RK3368_CLKGATE_CON(3), 0, GFLAGS),
539 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
540 RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
541 RK3368_CLKGATE_CON(3), 3, GFLAGS),
542 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
543 RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
544 RK3368_CLKGATE_CON(3), 2, GFLAGS),
545 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
546 RK3368_CLKGATE_CON(3), 1, GFLAGS),
547
548 GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
549
550 /*
551 * Clock-Architecture Diagram 4
552 */
553
554 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
555 RK3368_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
556 RK3368_CLKGATE_CON(3), 7, GFLAGS),
557 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
558 RK3368_CLKSEL_CON(45), 15, 1, MFLAGS, 8, 7, DFLAGS,
559 RK3368_CLKGATE_CON(3), 8, GFLAGS),
560 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
561 RK3368_CLKSEL_CON(46), 15, 1, MFLAGS, 8, 7, DFLAGS,
562 RK3368_CLKGATE_CON(3), 9, GFLAGS),
563
564
565 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
566 RK3368_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
567 RK3368_CLKGATE_CON(7), 12, GFLAGS),
568 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
569 RK3368_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
570 RK3368_CLKGATE_CON(7), 13, GFLAGS),
571 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
572 RK3368_CLKSEL_CON(51), 8, 2, MFLAGS, 0, 7, DFLAGS,
573 RK3368_CLKGATE_CON(7), 15, GFLAGS),
574
575 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3368_SDMMC_CON0, 1),
576 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3368_SDMMC_CON1, 0),
577
578 MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3368_SDIO0_CON0, 1),
579 MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3368_SDIO0_CON1, 0),
580
581 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3368_EMMC_CON0, 1),
582 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3368_EMMC_CON1, 0),
583
584 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
585 RK3368_CLKGATE_CON(8), 1, GFLAGS),
586
587 /* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
588 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
589 RK3368_CLKGATE_CON(8), 4, GFLAGS),
590
591 /* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
592 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
593 RK3368_CLKSEL_CON(25), 0, 6, DFLAGS,
594 RK3368_CLKGATE_CON(3), 5, GFLAGS),
595
596 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
597 RK3368_CLKSEL_CON(25), 8, 8, DFLAGS,
598 RK3368_CLKGATE_CON(3), 6, GFLAGS),
599
600 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
601 RK3368_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
602 RK3368_CLKGATE_CON(7), 8, GFLAGS),
603
604 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
605 RK3368_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 5, DFLAGS,
606 RK3368_CLKGATE_CON(6), 7, GFLAGS),
607
608 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
609 RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
610 RK3368_CLKGATE_CON(2), 0, GFLAGS),
611 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
612 RK3368_CLKSEL_CON(34), 0,
613 RK3368_CLKGATE_CON(2), 1, GFLAGS,
614 &rk3368_uart0_fracmux),
615
616 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
617 RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
618 RK3368_CLKGATE_CON(2), 2, GFLAGS),
619 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
620 RK3368_CLKSEL_CON(36), 0,
621 RK3368_CLKGATE_CON(2), 3, GFLAGS,
622 &rk3368_uart1_fracmux),
623
624 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
625 RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
626 RK3368_CLKGATE_CON(2), 6, GFLAGS),
627 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
628 RK3368_CLKSEL_CON(40), 0,
629 RK3368_CLKGATE_CON(2), 7, GFLAGS,
630 &rk3368_uart3_fracmux),
631
632 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
633 RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
634 RK3368_CLKGATE_CON(2), 8, GFLAGS),
635 COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
636 RK3368_CLKSEL_CON(42), 0,
637 RK3368_CLKGATE_CON(2), 9, GFLAGS,
638 &rk3368_uart4_fracmux),
639
640 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
641 RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
642 RK3368_CLKGATE_CON(3), 4, GFLAGS),
643 MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
644 RK3368_CLKSEL_CON(43), 8, 1, MFLAGS),
645 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
646 RK3368_CLKGATE_CON(7), 7, GFLAGS),
647 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
648 RK3368_CLKGATE_CON(7), 6, GFLAGS),
649 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
650 RK3368_CLKGATE_CON(7), 4, GFLAGS),
651 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
652 RK3368_CLKGATE_CON(7), 5, GFLAGS),
653
654 GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
655 RK3368_CLKGATE_CON(7), 0, GFLAGS),
656
657 COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
658 RK3368_CLKSEL_CON(26), 8, 2, MFLAGS,
659 RK3368_CLKGATE_CON(8), 0, GFLAGS),
660 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
661 RK3368_CLKSEL_CON(26), 12, 2, MFLAGS,
662 RK3368_CLKGATE_CON(8), 7, GFLAGS),
663 GATE(SCLK_HSICPHY12M, "sclk_hsicphy12m", "xin12m", 0,
664 RK3368_CLKGATE_CON(8), 6, GFLAGS),
665
666 /*
667 * Clock-Architecture Diagram 5
668 */
669
670 /* aclk_cci_pre gates */
671 GATE(0, "aclk_core_niu_cpup", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 4, GFLAGS),
672 GATE(0, "aclk_core_niu_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 3, GFLAGS),
673 GATE(0, "aclk_cci400", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 2, GFLAGS),
674 GATE(0, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 1, GFLAGS),
675 GATE(0, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 0, GFLAGS),
676
677 /* aclkm_core_* gates */
678 GATE(0, "aclk_adb400s_pd_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 0, GFLAGS),
679 GATE(0, "aclk_adb400s_pd_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 0, GFLAGS),
680
681 /* armclk* gates */
682 GATE(0, "sclk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 1, GFLAGS),
683 GATE(0, "sclk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 1, GFLAGS),
684
685 /* sclk_cs_pre gates */
686 GATE(0, "sclk_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 7, GFLAGS),
687 GATE(0, "pclk_core_niu_sdbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 6, GFLAGS),
688 GATE(0, "hclk_core_niu_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 5, GFLAGS),
689
690 /* aclk_bus gates */
691 GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS),
692 GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(12), 11, GFLAGS),
693 GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS),
694 GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS),
695 GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS),
696 GATE(0, "aclk_gic400", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 9, GFLAGS),
697
698 /* sclk_ddr gates */
699 GATE(0, "nclk_ddrupctl", "sclk_ddr", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 2, GFLAGS),
700
701 /* clk_hsadc_tsp is part of diagram2 */
702
703 /* fclk_mcu_src gates */
704 GATE(0, "hclk_noc_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 14, GFLAGS),
705 GATE(0, "fclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 12, GFLAGS),
706 GATE(0, "hclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 11, GFLAGS),
707
708 /* hclk_cpu gates */
709 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 10, GFLAGS),
710 GATE(HCLK_ROM, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 9, GFLAGS),
711 GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 8, GFLAGS),
712 GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 7, GFLAGS),
713 GATE(HCLK_TSP, "hclk_tsp", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 10, GFLAGS),
714 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 4, GFLAGS),
715 GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS),
716
717 /* pclk_cpu gates */
718 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(12), 14, GFLAGS),
719 GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(12), 13, GFLAGS),
720 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
721 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
722 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS),
723 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 0, GFLAGS),
724 GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
725 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(13), 6, GFLAGS),
726 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
727 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
728 GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
729
730 /*
731 * video clk gates
732 * aclk_video(_pre) can actually select between parents of aclk_vdpu
733 * and aclk_vepu by setting bit GRF_SOC_CON0[7].
734 */
735 GATE(ACLK_VIDEO, "aclk_video", "aclk_vdpu", 0, RK3368_CLKGATE_CON(15), 0, GFLAGS),
736 GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_src", 0, RK3368_CLKGATE_CON(15), 3, GFLAGS),
737 GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_src", 0, RK3368_CLKGATE_CON(15), 2, GFLAGS),
738 GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS),
739
740 /* aclk_rga_pre gates */
741 GATE(ACLK_VIO1_NOC, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
742 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS),
743 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
744
745 /* aclk_vio0 gates */
746 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 11, GFLAGS),
747 GATE(ACLK_VIO0_NOC, "aclk_vio0_noc", "aclk_vio0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 9, GFLAGS),
748 GATE(ACLK_VOP, "aclk_vop", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 5, GFLAGS),
749 GATE(ACLK_VOP_IEP, "aclk_vop_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 4, GFLAGS),
750 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 2, GFLAGS),
751
752 /* sclk_isp gates */
753 GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS),
754 GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS),
755
756 /* hclk_vio gates */
757 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 12, GFLAGS),
758 GATE(HCLK_VIO_NOC, "hclk_vio_noc", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 8, GFLAGS),
759 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 7, GFLAGS),
760 GATE(HCLK_VOP, "hclk_vop", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 6, GFLAGS),
761 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 3, GFLAGS),
762 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS),
763 GATE(HCLK_VIO_HDCPMMU, "hclk_hdcpmmu", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 12, GFLAGS),
764 GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 7, GFLAGS),
765
766 /*
767 * pclk_vio gates
768 * pclk_vio comes from the exactly same source as hclk_vio
769 */
770 GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 11, GFLAGS),
771 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 9, GFLAGS),
772 GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 8, GFLAGS),
773 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 6, GFLAGS),
774 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 4, GFLAGS),
775 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 3, GFLAGS),
776
777 /* ext_vip gates in diagram3 */
778
779 /* gpu gates */
780 GATE(SCLK_GPU_CORE, "sclk_gpu_core", "sclk_gpu_core_src", 0, RK3368_CLKGATE_CON(18), 2, GFLAGS),
781 GATE(ACLK_GPU_MEM, "aclk_gpu_mem", "aclk_gpu_mem_pre", 0, RK3368_CLKGATE_CON(18), 1, GFLAGS),
782 GATE(ACLK_GPU_CFG, "aclk_gpu_cfg", "aclk_gpu_cfg_pre", 0, RK3368_CLKGATE_CON(18), 0, GFLAGS),
783
784 /* aclk_peri gates */
785 GATE(ACLK_DMAC_PERI, "aclk_dmac_peri", "aclk_peri", 0, RK3368_CLKGATE_CON(19), 3, GFLAGS),
786 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 2, GFLAGS),
787 GATE(HCLK_SFC, "hclk_sfc", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 15, GFLAGS),
788 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 13, GFLAGS),
789 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 8, GFLAGS),
790 GATE(ACLK_PERI_MMU, "aclk_peri_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(21), 4, GFLAGS),
791
792 /* hclk_peri gates */
793 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 0, GFLAGS),
794 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 11, GFLAGS),
795 GATE(0, "hclk_mmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 10, GFLAGS),
796 GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
797 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
798 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
799 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 5, GFLAGS),
800 GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
801 GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),
802 GATE(0, "pmu_hclk_otg0", "hclk_peri", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(20), 2, GFLAGS),
803 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 1, GFLAGS),
804 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 3, GFLAGS),
805 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS),
806 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
807 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 0, GFLAGS),
808
809 /* pclk_peri gates */
810 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 15, GFLAGS),
811 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 14, GFLAGS),
812 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 13, GFLAGS),
813 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 12, GFLAGS),
814 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 11, GFLAGS),
815 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 10, GFLAGS),
816 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 9, GFLAGS),
817 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 8, GFLAGS),
818 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 7, GFLAGS),
819 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 6, GFLAGS),
820 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 5, GFLAGS),
821 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS),
822 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 1, GFLAGS),
823 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 14, GFLAGS),
824 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS),
825
826 /* pclk_pd_alive gates */
827 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS),
828 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
829 GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(22), 9, GFLAGS),
830 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(22), 8, GFLAGS),
831 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
832 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
833 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
834
835 /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
836 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
837
838 /*
839 * pclk_vio gates
840 * pclk_vio comes from the exactly same source as hclk_vio
841 */
842 GATE(0, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
843 GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
844
845 /* pclk_pd_pmu gates */
846 GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
847 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS),
848 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS),
849 GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS),
850 GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS),
851 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
852
853 /* timer gates */
854 GATE(SCLK_TIMER15, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),
855 GATE(SCLK_TIMER14, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS),
856 GATE(SCLK_TIMER13, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS),
857 GATE(SCLK_TIMER12, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS),
858 GATE(SCLK_TIMER11, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS),
859 GATE(SCLK_TIMER10, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS),
860 GATE(SCLK_TIMER05, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS),
861 GATE(SCLK_TIMER04, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS),
862 GATE(SCLK_TIMER03, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS),
863 GATE(SCLK_TIMER02, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS),
864 GATE(SCLK_TIMER01, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS),
865 GATE(SCLK_TIMER00, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
866 };
867
868 static void __iomem *rk3368_cru_base;
869
rk3368_dump_cru(void)870 static void rk3368_dump_cru(void)
871 {
872 if (rk3368_cru_base) {
873 pr_warn("CRU:\n");
874 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
875 32, 4, rk3368_cru_base,
876 0x41c, false);
877 }
878 }
879
rk3368_clk_init(struct device_node * np)880 static void __init rk3368_clk_init(struct device_node *np)
881 {
882 struct rockchip_clk_provider *ctx;
883 void __iomem *reg_base;
884 struct clk **clks;
885
886 reg_base = of_iomap(np, 0);
887 if (!reg_base) {
888 pr_err("%s: could not map cru region\n", __func__);
889 return;
890 }
891
892 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
893 if (IS_ERR(ctx)) {
894 pr_err("%s: rockchip clk init failed\n", __func__);
895 iounmap(reg_base);
896 return;
897 }
898 clks = ctx->clk_data.clks;
899
900 rockchip_clk_register_plls(ctx, rk3368_pll_clks,
901 ARRAY_SIZE(rk3368_pll_clks),
902 RK3368_GRF_SOC_STATUS0);
903 rockchip_clk_register_branches(ctx, rk3368_clk_branches,
904 ARRAY_SIZE(rk3368_clk_branches));
905
906 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
907 2, clks[PLL_APLLB], clks[PLL_GPLL],
908 &rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
909 ARRAY_SIZE(rk3368_cpuclkb_rates));
910
911 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
912 2, clks[PLL_APLLL], clks[PLL_GPLL],
913 &rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
914 ARRAY_SIZE(rk3368_cpuclkl_rates));
915
916 rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
917 ROCKCHIP_SOFTRST_HIWORD_MASK);
918
919 rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL);
920
921 rockchip_clk_of_add_provider(np, ctx);
922
923 if (!rk_dump_cru) {
924 rk3368_cru_base = reg_base;
925 rk_dump_cru = rk3368_dump_cru;
926 }
927 }
928 CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);
929
clk_rk3368_probe(struct platform_device * pdev)930 static int __init clk_rk3368_probe(struct platform_device *pdev)
931 {
932 struct device_node *np = pdev->dev.of_node;
933
934 rk3368_clk_init(np);
935
936 return 0;
937 }
938
939 static const struct of_device_id clk_rk3368_match_table[] = {
940 {
941 .compatible = "rockchip,rk3368-cru",
942 },
943 { }
944 };
945 MODULE_DEVICE_TABLE(of, clk_rk3368_match_table);
946
947 static struct platform_driver clk_rk3368_driver = {
948 .driver = {
949 .name = "clk-rk3368",
950 .of_match_table = clk_rk3368_match_table,
951 },
952 };
953 builtin_platform_driver_probe(clk_rk3368_driver, clk_rk3368_probe);
954
955 MODULE_DESCRIPTION("Rockchip RK3368 Clock Driver");
956 MODULE_LICENSE("GPL");
957