1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 4/dts-v1/; 5#include "rk1808.dtsi" 6 7/ { 8 model = "Rockchip rk1808 fpga board"; 9 compatible = "rockchip,fpga", "rockchip,rk1808"; 10 11 chosen { 12 bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 root=/dev/mmcblk1p8 rootfstype=ext4 rootwait clk_ignore_unused"; 13 }; 14 15 memory@200000 { 16 device_type = "memory"; 17 reg = <0x0 0x00200000 0x0 0x0FE00000>; 18 }; 19 20 fiq_debugger: fiq-debugger { 21 compatible = "rockchip,fiq-debugger"; 22 rockchip,serial-id = <2>; 23 rockchip,wake-irq = <0>; 24 rockchip,irq-mode-enable = <1>; 25 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 26 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 27 status = "okay"; 28 }; 29}; 30 31&emmc { 32 max-frequency = <400000>; 33 clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>; 34 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 35 mmc-hs200-1_8v; 36 no-sdio; 37 no-sd; 38 num-slots = <1>; 39 status = "okay"; 40}; 41 42&npu { 43 status = "okay"; 44}; 45 46&sdmmc { 47 max-frequency = <400000>; 48 clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>; 49 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 50 no-sdio; 51 no-mmc; 52 status = "okay"; 53}; 54 55/* If fiq_debugger set okay, need to define uart2 and to be disabled */ 56&uart2 { 57 status = "disabled"; 58}; 59