clk/rockchip/clk-rk1808.c

131 PNAME(mux_pll_p)		= { "xin24m", "xin32k"};
132 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "xin32k" };
139 PNAME(mux_dclk_vopraw_p)		= { "dclk_vopraw_src", "dclk_vopraw_frac", "xin24m" };
140 PNAME(mux_dclk_voplite_p)		= { "dclk_voplite_src", "dclk_voplite_frac", "xin24m" };
141 PNAME(mux_24m_npll_gpll_usb480m_p)	= { "xin24m", "npll", "gpll", "usb480m" };
142 PNAME(mux_usb3_otg0_suspend_p)	= { "xin32k", "xin24m" };
143 PNAME(mux_pcie_aux_p)	= { "xin24m", "clk_pcie_src" };
144 PNAME(mux_gpll_cpll_npll_24m_p)	= { "gpll", "cpll", "npll", "xin24m" };
154 PNAME(mux_uart1_p)		= { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac", "xin24m" };
155 PNAME(mux_uart2_p)		= { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac", "xin24m" };
156 PNAME(mux_uart3_p)		= { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac", "xin24m" };
157 PNAME(mux_uart4_p)		= { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac", "xin24m" };
158 PNAME(mux_uart5_p)		= { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac", "xin24m" };
159 PNAME(mux_uart6_p)		= { "clk_uart6_src", "clk_uart6_np5", "clk_uart6_frac", "xin24m" };
160 PNAME(mux_uart7_p)		= { "clk_uart7_src", "clk_uart7_np5", "clk_uart7_frac", "xin24m" };
161 PNAME(mux_gpll_xin24m_p)		= { "gpll", "xin24m" };
162 PNAME(mux_gpll_cpll_xin24m_p)		= { "gpll", "cpll", "xin24m" };
163 PNAME(mux_gpll_xin24m_cpll_npll_p)	= { "gpll", "xin24m", "cpll", "npll" };
174 PNAME(mux_wifi_pmu_p)		= { "xin24m", "clk_wifi_pmu_src" };
176 PNAME(mux_uart0_pmu_p)		= { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac", "xin24m" };
177 PNAME(mux_usbphy_ref_p)		= { "xin24m", "clk_ref24m_pmu" };
178 PNAME(mux_mipidsiphy_ref_p)	= { "xin24m", "clk_ref24m_pmu" };
179 PNAME(mux_pciephy_ref_p)		= { "xin24m", "clk_pciephy_src" };
180 PNAME(mux_ppll_xin24m_p)		= { "ppll", "xin24m" };
181 PNAME(mux_xin24m_32k_p)		= { "xin24m", "xin32k" };
276 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
298 	GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
369 	GATE(SCLK_PVTM_NPU, "clk_pvtm_npu", "xin24m", 0,
399 	 GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED,
573 	GATE(SCLK_USB3_OTG0_REF, "clk_usb3_otg0_ref", "xin24m", 0,
934 	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
937 	COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
971 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
973 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
975 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
977 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
979 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
981 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
1074 	COMPOSITE_FRACMUX(SCLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
1079 	COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
1103 	GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,