1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
5 * Author: Finley Xiao <finley.xiao@rock-chips.com>
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/of_address.h>
13 #include <linux/syscore_ops.h>
14 #include <dt-bindings/clock/rk3562-cru.h>
15 #include "clk.h"
16
17 #define RK3562_GRF_SOC_STATUS0 0x430
18
19 enum rk3562_plls {
20 apll, gpll, vpll, hpll, cpll, dpll,
21 };
22
23 static struct rockchip_pll_rate_table rk3562_pll_rates[] = {
24 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
25 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
26 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
27 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
28 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
29 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
30 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
31 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
32 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
40 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
41 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
42 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
43 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
44 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
45 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
46 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
47 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
48 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
49 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
50 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
51 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
52 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
53 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
54 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
55 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
56 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
57 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
58 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
59 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
60 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
61 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
62 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
63 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
64 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
65 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
66 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
67 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
68 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
69 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
70 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
71 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
72 RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
73 RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
74 RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
75 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
76 RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
77 { /* sentinel */ },
78 };
79
80 PNAME(mux_pll_p) = { "xin24m" };
81 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
82 PNAME(gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
83 PNAME(gpll_cpll_pvtpll_dmyapll_p) = { "gpll", "cpll", "log_pvtpll", "dummy_apll" };
84 PNAME(gpll_cpll_hpll_xin24m_p) = { "gpll", "cpll", "hpll", "xin24m" };
85 PNAME(gpll_cpll_vpll_dmyhpll_p) = { "gpll", "cpll", "vpll", "dummy_hpll" };
86 PNAME(gpll_dmyhpll_vpll_apll_p) = { "gpll", "dummy_hpll", "vpll", "apll" };
87 PNAME(gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
88 PNAME(gpll_cpll_xin24m_dmyapll_p) = { "gpll", "cpll", "xin24m", "dummy_apll" };
89 PNAME(gpll_cpll_xin24m_dmyhpll_p) = { "gpll", "cpll", "xin24m", "dummy_hpll" };
90 PNAME(vpll_dmyhpll_gpll_cpll_p) = { "vpll", "dummy_hpll", "gpll", "cpll" };
91 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
92 PNAME(mux_50m_xin24m_p) = { "clk_matrix_50m_src", "xin24m" };
93 PNAME(mux_100m_50m_xin24m_p) = { "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" };
94 PNAME(mux_125m_xin24m_p) = { "clk_matrix_125m_src", "xin24m" };
95 PNAME(mux_200m_xin24m_32k_p) = { "clk_200m_pmu", "xin24m", "clk_rtc_32k" };
96 PNAME(mux_200m_100m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src" };
97 PNAME(mux_200m_100m_50m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" };
98 PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };
99 PNAME(mclk_sai0_out2io_p) = { "mclk_sai0", "xin_osc0_half" };
100 PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_from_io" };
101 PNAME(mclk_sai1_out2io_p) = { "mclk_sai1", "xin_osc0_half" };
102 PNAME(clk_sai2_p) = { "clk_sai2_src", "clk_sai2_frac", "xin_osc0_half", "mclk_sai2_from_io" };
103 PNAME(mclk_sai2_out2io_p) = { "mclk_sai2", "xin_osc0_half" };
104 PNAME(clk_spdif_p) = { "clk_spdif_src", "clk_spdif_frac", "xin_osc0_half" };
105 PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
106 PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
107 PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
108 PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
109 PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
110 PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
111 PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
112 PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
113 PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
114 PNAME(clk_rtc32k_pmu_p) = { "clk_rtc32k_frac", "xin32k", "clk_32k_pvtm" };
115 PNAME(clk_pmu1_uart0_p) = { "clk_pmu1_uart0_src", "clk_pmu1_uart0_frac", "xin24m" };
116 PNAME(clk_pipephy_ref_p) = { "clk_pipephy_div", "clk_pipephy_xin24m" };
117 PNAME(clk_usbphy_ref_p) = { "clk_usb2phy_xin24m", "clk_24m_sscsrc" };
118 PNAME(clk_mipidsi_ref_p) = { "clk_mipidsiphy_xin24m", "clk_24m_sscsrc" };
119
120 static struct rockchip_pll_clock rk3562_pll_clks[] __initdata = {
121 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
122 0, RK3562_PLL_CON(0),
123 RK3562_MODE_CON, 0, 0,
124 ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates),
125 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
126 0, RK3562_PLL_CON(24),
127 RK3562_MODE_CON, 2, 3, 0, rk3562_pll_rates),
128 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
129 0, RK3562_PLL_CON(32),
130 RK3562_MODE_CON, 6, 4,
131 ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates),
132 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
133 0, RK3562_PLL_CON(40),
134 RK3562_MODE_CON, 8, 5,
135 ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates),
136 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
137 0, RK3562_PMU1_PLL_CON(0),
138 RK3562_PMU1_MODE_CON, 0, 2, 0, rk3562_pll_rates),
139 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
140 0, RK3562_SUBDDR_PLL_CON(0),
141 RK3562_SUBDDR_MODE_CON, 0, 1, 0, NULL),
142 };
143
144 #define MFLAGS CLK_MUX_HIWORD_MASK
145 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
146 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
147
148 static struct rockchip_clk_branch rk3562_clk_sai0_fracmux __initdata =
149 MUX(CLK_SAI0, "clk_sai0", clk_sai0_p, CLK_SET_RATE_PARENT,
150 RK3562_PERI_CLKSEL_CON(3), 6, 2, MFLAGS);
151
152 static struct rockchip_clk_branch rk3562_clk_sai1_fracmux __initdata =
153 MUX(CLK_SAI1, "clk_sai1", clk_sai1_p, CLK_SET_RATE_PARENT,
154 RK3562_PERI_CLKSEL_CON(5), 6, 2, MFLAGS);
155
156 static struct rockchip_clk_branch rk3562_clk_sai2_fracmux __initdata =
157 MUX(CLK_SAI2, "clk_sai2", clk_sai2_p, CLK_SET_RATE_PARENT,
158 RK3562_PERI_CLKSEL_CON(8), 6, 2, MFLAGS);
159
160 static struct rockchip_clk_branch rk3562_clk_spdif_fracmux __initdata =
161 MUX(CLK_SPDIF, "clk_spdif", clk_spdif_p, CLK_SET_RATE_PARENT,
162 RK3562_PERI_CLKSEL_CON(15), 6, 2, MFLAGS);
163
164 static struct rockchip_clk_branch rk3562_clk_uart1_fracmux __initdata =
165 MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
166 RK3562_PERI_CLKSEL_CON(21), 14, 2, MFLAGS);
167
168 static struct rockchip_clk_branch rk3562_clk_uart2_fracmux __initdata =
169 MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
170 RK3562_PERI_CLKSEL_CON(23), 14, 2, MFLAGS);
171
172 static struct rockchip_clk_branch rk3562_clk_uart3_fracmux __initdata =
173 MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
174 RK3562_PERI_CLKSEL_CON(25), 14, 2, MFLAGS);
175
176 static struct rockchip_clk_branch rk3562_clk_uart4_fracmux __initdata =
177 MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
178 RK3562_PERI_CLKSEL_CON(27), 14, 2, MFLAGS);
179
180 static struct rockchip_clk_branch rk3562_clk_uart5_fracmux __initdata =
181 MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
182 RK3562_PERI_CLKSEL_CON(29), 14, 2, MFLAGS);
183
184 static struct rockchip_clk_branch rk3562_clk_uart6_fracmux __initdata =
185 MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT,
186 RK3562_PERI_CLKSEL_CON(31), 14, 2, MFLAGS);
187
188 static struct rockchip_clk_branch rk3562_clk_uart7_fracmux __initdata =
189 MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT,
190 RK3562_PERI_CLKSEL_CON(33), 14, 2, MFLAGS);
191
192 static struct rockchip_clk_branch rk3562_clk_uart8_fracmux __initdata =
193 MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT,
194 RK3562_PERI_CLKSEL_CON(35), 14, 2, MFLAGS);
195
196 static struct rockchip_clk_branch rk3562_clk_uart9_fracmux __initdata =
197 MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT,
198 RK3562_PERI_CLKSEL_CON(37), 14, 2, MFLAGS);
199
200 static struct rockchip_clk_branch rk3562_rtc32k_pmu_fracmux __initdata =
201 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
202 RK3562_PMU0_CLKSEL_CON(1), 0, 2, MFLAGS);
203
204 static struct rockchip_clk_branch rk3562_clk_pmu1_uart0_fracmux __initdata =
205 MUX(CLK_PMU1_UART0, "clk_pmu1_uart0", clk_pmu1_uart0_p, CLK_SET_RATE_PARENT,
206 RK3562_PMU1_CLKSEL_CON(2), 6, 2, MFLAGS);
207
208 static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = {
209 /*
210 * CRU Clock-Architecture
211 */
212 /* PD_TOP */
213 COMPOSITE(CLK_MATRIX_50M_SRC, "clk_matrix_50m_src", gpll_cpll_p, 0,
214 RK3562_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS,
215 RK3562_CLKGATE_CON(0), 0, GFLAGS),
216 COMPOSITE(CLK_MATRIX_100M_SRC, "clk_matrix_100m_src", gpll_cpll_p, CLK_IS_CRITICAL,
217 RK3562_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 4, DFLAGS,
218 RK3562_CLKGATE_CON(0), 1, GFLAGS),
219 COMPOSITE(CLK_MATRIX_125M_SRC, "clk_matrix_125m_src", gpll_cpll_p, 0,
220 RK3562_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 4, DFLAGS,
221 RK3562_CLKGATE_CON(0), 2, GFLAGS),
222 COMPOSITE(CLK_MATRIX_200M_SRC, "clk_matrix_200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
223 RK3562_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 4, DFLAGS,
224 RK3562_CLKGATE_CON(0), 4, GFLAGS),
225 COMPOSITE(CLK_MATRIX_300M_SRC, "clk_matrix_300m_src", gpll_cpll_p, CLK_IS_CRITICAL,
226 RK3562_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 4, DFLAGS,
227 RK3562_CLKGATE_CON(0), 6, GFLAGS),
228 COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_p, CLK_IS_CRITICAL,
229 RK3562_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 4, DFLAGS,
230 RK3562_CLKGATE_CON(1), 0, GFLAGS),
231 COMPOSITE(ACLK_TOP_VIO, "aclk_top_vio", gpll_cpll_p, 0,
232 RK3562_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 4, DFLAGS,
233 RK3562_CLKGATE_CON(1), 1, GFLAGS),
234 COMPOSITE(CLK_24M_SSCSRC, "clk_24m_sscsrc", vpll_dmyhpll_gpll_cpll_p, 0,
235 RK3562_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
236 RK3562_CLKGATE_CON(1), 9, GFLAGS),
237 COMPOSITE(CLK_CAM0_OUT2IO, "clk_cam0_out2io", gpll_cpll_xin24m_dmyapll_p, 0,
238 RK3562_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 6, DFLAGS,
239 RK3562_CLKGATE_CON(1), 12, GFLAGS),
240 COMPOSITE(CLK_CAM1_OUT2IO, "clk_cam1_out2io", gpll_cpll_xin24m_dmyapll_p, 0,
241 RK3562_CLKSEL_CON(8), 14, 2, MFLAGS, 8, 6, DFLAGS,
242 RK3562_CLKGATE_CON(1), 13, GFLAGS),
243 COMPOSITE(CLK_CAM2_OUT2IO, "clk_cam2_out2io", gpll_cpll_xin24m_dmyapll_p, 0,
244 RK3562_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 6, DFLAGS,
245 RK3562_CLKGATE_CON(1), 14, GFLAGS),
246 COMPOSITE(CLK_CAM3_OUT2IO, "clk_cam3_out2io", gpll_cpll_xin24m_dmyapll_p, 0,
247 RK3562_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 6, DFLAGS,
248 RK3562_CLKGATE_CON(1), 15, GFLAGS),
249 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
250
251 /* PD_BUS */
252 COMPOSITE(ACLK_BUS, "aclk_bus", gpll_cpll_p, CLK_IS_CRITICAL,
253 RK3562_CLKSEL_CON(40), 7, 1, MFLAGS, 0, 5, DFLAGS,
254 RK3562_CLKGATE_CON(18), 0, GFLAGS),
255 COMPOSITE(HCLK_BUS, "hclk_bus", gpll_cpll_p, CLK_IS_CRITICAL,
256 RK3562_CLKSEL_CON(40), 15, 1, MFLAGS, 8, 6, DFLAGS,
257 RK3562_CLKGATE_CON(18), 1, GFLAGS),
258 COMPOSITE(PCLK_BUS, "pclk_bus", gpll_cpll_p, CLK_IS_CRITICAL,
259 RK3562_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS,
260 RK3562_CLKGATE_CON(18), 2, GFLAGS),
261 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
262 RK3562_CLKGATE_CON(19), 0, GFLAGS),
263 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0,
264 RK3562_CLKGATE_CON(19), 1, GFLAGS),
265 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0,
266 RK3562_CLKGATE_CON(19), 2, GFLAGS),
267 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0,
268 RK3562_CLKGATE_CON(19), 3, GFLAGS),
269 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0,
270 RK3562_CLKGATE_CON(19), 4, GFLAGS),
271 COMPOSITE_NODIV(CLK_I2C, "clk_i2c", mux_200m_100m_50m_xin24m_p, 0,
272 RK3562_CLKSEL_CON(41), 8, 2, MFLAGS,
273 RK3562_CLKGATE_CON(19), 5, GFLAGS),
274 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
275 RK3562_CLKGATE_CON(19), 6, GFLAGS),
276 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
277 RK3562_CLKGATE_CON(19), 7, GFLAGS),
278 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
279 RK3562_CLKGATE_CON(19), 8, GFLAGS),
280 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
281 RK3562_CLKGATE_CON(19), 9, GFLAGS),
282 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
283 RK3562_CLKGATE_CON(19), 10, GFLAGS),
284 COMPOSITE_NODIV(DCLK_BUS_GPIO, "dclk_bus_gpio", mux_xin24m_32k_p, 0,
285 RK3562_CLKSEL_CON(41), 15, 1, MFLAGS,
286 RK3562_CLKGATE_CON(20), 4, GFLAGS),
287 GATE(DCLK_BUS_GPIO3, "dclk_bus_gpio3", "dclk_bus_gpio", 0,
288 RK3562_CLKGATE_CON(20), 5, GFLAGS),
289 GATE(DCLK_BUS_GPIO4, "dclk_bus_gpio4", "dclk_bus_gpio", 0,
290 RK3562_CLKGATE_CON(20), 6, GFLAGS),
291 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0,
292 RK3562_CLKGATE_CON(21), 0, GFLAGS),
293 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
294 RK3562_CLKGATE_CON(21), 1, GFLAGS),
295 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
296 RK3562_CLKGATE_CON(21), 2, GFLAGS),
297 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
298 RK3562_CLKGATE_CON(21), 3, GFLAGS),
299 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
300 RK3562_CLKGATE_CON(21), 4, GFLAGS),
301 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
302 RK3562_CLKGATE_CON(21), 5, GFLAGS),
303 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
304 RK3562_CLKGATE_CON(21), 6, GFLAGS),
305 GATE(PCLK_STIMER, "pclk_stimer", "pclk_bus", CLK_IGNORE_UNUSED,
306 RK3562_CLKGATE_CON(21), 7, GFLAGS),
307 GATE(CLK_STIMER0, "clk_stimer0", "xin24m", CLK_IGNORE_UNUSED,
308 RK3562_CLKGATE_CON(21), 8, GFLAGS),
309 GATE(CLK_STIMER1, "clk_stimer1", "xin24m", CLK_IGNORE_UNUSED,
310 RK3562_CLKGATE_CON(21), 9, GFLAGS),
311 GATE(PCLK_WDTNS, "pclk_wdtns", "pclk_bus", 0,
312 RK3562_CLKGATE_CON(22), 0, GFLAGS),
313 GATE(CLK_WDTNS, "clk_wdtns", "xin24m", 0,
314 RK3562_CLKGATE_CON(22), 1, GFLAGS),
315 GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED,
316 RK3562_CLKGATE_CON(22), 2, GFLAGS),
317 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED,
318 RK3562_CLKGATE_CON(22), 3, GFLAGS),
319 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0,
320 RK3562_CLKGATE_CON(22), 4, GFLAGS),
321 GATE(PCLK_INTC, "pclk_intc", "pclk_bus", 0,
322 RK3562_CLKGATE_CON(22), 5, GFLAGS),
323 GATE(ACLK_BUS_GIC400, "aclk_bus_gic400", "aclk_bus", CLK_IGNORE_UNUSED,
324 RK3562_CLKGATE_CON(22), 6, GFLAGS),
325 GATE(ACLK_BUS_SPINLOCK, "aclk_bus_spinlock", "aclk_bus", 0,
326 RK3562_CLKGATE_CON(23), 0, GFLAGS),
327 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus", CLK_IGNORE_UNUSED,
328 RK3562_CLKGATE_CON(23), 1, GFLAGS),
329 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", CLK_IGNORE_UNUSED,
330 RK3562_CLKGATE_CON(23), 2, GFLAGS),
331 GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus", 0,
332 RK3562_CLKGATE_CON(23), 3, GFLAGS),
333 GATE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", "clk_rtc_32k", 0,
334 RK3562_CLKGATE_CON(23), 4, GFLAGS),
335 GATE(HCLK_ICACHE, "hclk_icache", "hclk_bus", CLK_IGNORE_UNUSED,
336 RK3562_CLKGATE_CON(23), 8, GFLAGS),
337 GATE(HCLK_DCACHE, "hclk_dcache", "hclk_bus", CLK_IGNORE_UNUSED,
338 RK3562_CLKGATE_CON(23), 9, GFLAGS),
339 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
340 RK3562_CLKGATE_CON(24), 0, GFLAGS),
341 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
342 RK3562_CLKSEL_CON(43), 0, 11, DFLAGS,
343 RK3562_CLKGATE_CON(24), 1, GFLAGS),
344 COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
345 RK3562_CLKSEL_CON(43), 11, 5, DFLAGS,
346 RK3562_CLKGATE_CON(24), 3, GFLAGS),
347 GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus", CLK_IGNORE_UNUSED,
348 RK3562_CLKGATE_CON(24), 4, GFLAGS),
349 COMPOSITE_NOMUX(CLK_SARADC_VCCIO156, "clk_saradc_vccio156", "xin24m", 0,
350 RK3562_CLKSEL_CON(44), 0, 12, DFLAGS,
351 RK3562_CLKGATE_CON(24), 9, GFLAGS),
352 GATE(PCLK_GMAC, "pclk_gmac", "pclk_bus", 0,
353 RK3562_CLKGATE_CON(25), 0, GFLAGS),
354 GATE(ACLK_GMAC, "aclk_gmac", "aclk_bus", 0,
355 RK3562_CLKGATE_CON(25), 1, GFLAGS),
356 COMPOSITE_NODIV(CLK_GMAC_125M_CRU_I, "clk_gmac_125m_cru_i", mux_125m_xin24m_p, 0,
357 RK3562_CLKSEL_CON(45), 8, 1, MFLAGS,
358 RK3562_CLKGATE_CON(25), 2, GFLAGS),
359 COMPOSITE_NODIV(CLK_GMAC_50M_CRU_I, "clk_gmac_50m_cru_i", mux_50m_xin24m_p, 0,
360 RK3562_CLKSEL_CON(45), 7, 1, MFLAGS,
361 RK3562_CLKGATE_CON(25), 3, GFLAGS),
362 COMPOSITE(CLK_GMAC_ETH_OUT2IO, "clk_gmac_eth_out2io", gpll_cpll_p, 0,
363 RK3562_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 7, DFLAGS,
364 RK3562_CLKGATE_CON(25), 4, GFLAGS),
365 GATE(PCLK_APB2ASB_VCCIO156, "pclk_apb2asb_vccio156", "pclk_bus", CLK_IS_CRITICAL,
366 RK3562_CLKGATE_CON(25), 5, GFLAGS),
367 GATE(PCLK_TO_VCCIO156, "pclk_to_vccio156", "pclk_bus", CLK_IS_CRITICAL,
368 RK3562_CLKGATE_CON(25), 6, GFLAGS),
369 GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_bus", 0,
370 RK3562_CLKGATE_CON(25), 8, GFLAGS),
371 GATE(PCLK_DSITX, "pclk_dsitx", "pclk_bus", 0,
372 RK3562_CLKGATE_CON(25), 9, GFLAGS),
373 GATE(PCLK_CPU_EMA_DET, "pclk_cpu_ema_det", "pclk_bus", CLK_IGNORE_UNUSED,
374 RK3562_CLKGATE_CON(25), 10, GFLAGS),
375 GATE(PCLK_HASH, "pclk_hash", "pclk_bus", 0,
376 RK3562_CLKGATE_CON(25), 11, GFLAGS),
377 GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_bus", CLK_IGNORE_UNUSED,
378 RK3562_CLKGATE_CON(25), 15, GFLAGS),
379 GATE(PCLK_ASB2APB_VCCIO156, "pclk_asb2apb_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL,
380 RK3562_CLKGATE_CON(26), 0, GFLAGS),
381 GATE(PCLK_IOC_VCCIO156, "pclk_ioc_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL,
382 RK3562_CLKGATE_CON(26), 1, GFLAGS),
383 GATE(PCLK_GPIO3_VCCIO156, "pclk_gpio3_vccio156", "pclk_to_vccio156", 0,
384 RK3562_CLKGATE_CON(26), 2, GFLAGS),
385 GATE(PCLK_GPIO4_VCCIO156, "pclk_gpio4_vccio156", "pclk_to_vccio156", 0,
386 RK3562_CLKGATE_CON(26), 3, GFLAGS),
387 GATE(PCLK_SARADC_VCCIO156, "pclk_saradc_vccio156", "pclk_to_vccio156", 0,
388 RK3562_CLKGATE_CON(26), 4, GFLAGS),
389 GATE(PCLK_MAC100, "pclk_mac100", "pclk_bus", 0,
390 RK3562_CLKGATE_CON(27), 0, GFLAGS),
391 GATE(ACLK_MAC100, "aclk_mac100", "aclk_bus", 0,
392 RK3562_CLKGATE_CON(27), 1, GFLAGS),
393 COMPOSITE_NODIV(CLK_MAC100_50M_MATRIX, "clk_mac100_50m_matrix", mux_50m_xin24m_p, 0,
394 RK3562_CLKSEL_CON(47), 7, 1, MFLAGS,
395 RK3562_CLKGATE_CON(27), 2, GFLAGS),
396
397 /* PD_CORE */
398 COMPOSITE_NOMUX(0, "aclk_core_pre", "scmi_clk_cpu", CLK_IGNORE_UNUSED,
399 RK3562_CLKSEL_CON(11), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
400 RK3562_CLKGATE_CON(4), 3, GFLAGS),
401 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "scmi_clk_cpu", CLK_IGNORE_UNUSED,
402 RK3562_CLKSEL_CON(12), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
403 RK3562_CLKGATE_CON(4), 5, GFLAGS),
404 COMPOSITE_NOMUX(HCLK_CORE, "hclk_core", "gpll", CLK_IS_CRITICAL,
405 RK3562_CLKSEL_CON(13), 0, 6, DFLAGS,
406 RK3562_CLKGATE_CON(5), 2, GFLAGS),
407 GATE(0, "pclk_dbg_daplite", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
408 RK3562_CLKGATE_CON(4), 10, GFLAGS),
409
410 /* PD_DDR */
411 FACTOR_GATE(0, "clk_gpll_mux_to_ddr", "gpll", 0, 1, 4,
412 RK3328_CLKGATE_CON(1), 6, GFLAGS),
413 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL,
414 RK3562_DDR_CLKSEL_CON(1), 8, 5, DFLAGS,
415 RK3562_DDR_CLKGATE_CON(0), 3, GFLAGS),
416 COMPOSITE_NOMUX(CLK_MSCH_BRG_BIU, "clk_msch_brg_biu", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL,
417 RK3562_DDR_CLKSEL_CON(1), 0, 4, DFLAGS,
418 RK3562_DDR_CLKGATE_CON(0), 4, GFLAGS),
419 GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr", CLK_IGNORE_UNUSED,
420 RK3562_DDR_CLKGATE_CON(0), 6, GFLAGS),
421 GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_ddr", CLK_IGNORE_UNUSED,
422 RK3562_DDR_CLKGATE_CON(0), 7, GFLAGS),
423 GATE(PCLK_DDR_PHY, "pclk_ddr_phy", "pclk_ddr", CLK_IGNORE_UNUSED,
424 RK3562_DDR_CLKGATE_CON(0), 8, GFLAGS),
425 GATE(PCLK_DDR_DFICTL, "pclk_ddr_dfictl", "pclk_ddr", CLK_IGNORE_UNUSED,
426 RK3562_DDR_CLKGATE_CON(0), 9, GFLAGS),
427 GATE(PCLK_DDR_DMA2DDR, "pclk_ddr_dma2ddr", "pclk_ddr", CLK_IGNORE_UNUSED,
428 RK3562_DDR_CLKGATE_CON(0), 10, GFLAGS),
429 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
430 RK3562_DDR_CLKGATE_CON(1), 0, GFLAGS),
431 GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
432 RK3562_DDR_CLKGATE_CON(1), 1, GFLAGS),
433 GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
434 RK3562_DDR_CLKGATE_CON(1), 2, GFLAGS),
435 GATE(PCLK_DDR_CRU, "pclk_ddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED,
436 RK3562_DDR_CLKGATE_CON(1), 3, GFLAGS),
437 GATE(PCLK_SUBDDR_CRU, "pclk_subddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED,
438 RK3562_DDR_CLKGATE_CON(1), 4, GFLAGS),
439
440 /* PD_GPU */
441 COMPOSITE(CLK_GPU_PRE, "clk_gpu_pre", gpll_cpll_p, 0,
442 RK3562_CLKSEL_CON(18), 7, 1, MFLAGS, 0, 4, DFLAGS,
443 RK3562_CLKGATE_CON(8), 0, GFLAGS),
444 COMPOSITE_NOMUX(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre", 0,
445 RK3562_CLKSEL_CON(19), 0, 4, DFLAGS,
446 RK3562_CLKGATE_CON(8), 2, GFLAGS),
447 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre", 0,
448 RK3562_CLKGATE_CON(8), 4, GFLAGS),
449 COMPOSITE_NODIV(CLK_GPU_BRG, "clk_gpu_brg", mux_200m_100m_p, 0,
450 RK3562_CLKSEL_CON(19), 15, 1, MFLAGS,
451 RK3562_CLKGATE_CON(8), 8, GFLAGS),
452
453 /* PD_NPU */
454 COMPOSITE(CLK_NPU_PRE, "clk_npu_pre", gpll_cpll_p, 0,
455 RK3562_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 4, DFLAGS,
456 RK3562_CLKGATE_CON(6), 0, GFLAGS),
457 COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu_pre", 0,
458 RK3562_CLKSEL_CON(16), 0, 4, DFLAGS,
459 RK3562_CLKGATE_CON(6), 1, GFLAGS),
460 GATE(ACLK_RKNN, "aclk_rknn", "clk_npu_pre", 0,
461 RK3562_CLKGATE_CON(6), 4, GFLAGS),
462 GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_pre", 0,
463 RK3562_CLKGATE_CON(6), 5, GFLAGS),
464
465 /* PD_PERI */
466 COMPOSITE(ACLK_PERI, "aclk_peri", gpll_cpll_p, CLK_IS_CRITICAL,
467 RK3562_PERI_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS,
468 RK3562_PERI_CLKGATE_CON(1), 0, GFLAGS),
469 COMPOSITE(HCLK_PERI, "hclk_peri", gpll_cpll_p, CLK_IS_CRITICAL,
470 RK3562_PERI_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 6, DFLAGS,
471 RK3562_PERI_CLKGATE_CON(1), 1, GFLAGS),
472 COMPOSITE(PCLK_PERI, "pclk_peri", gpll_cpll_p, CLK_IS_CRITICAL,
473 RK3562_PERI_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 5, DFLAGS,
474 RK3562_PERI_CLKGATE_CON(1), 2, GFLAGS),
475 GATE(PCLK_PERICRU, "pclk_pericru", "pclk_peri", CLK_IGNORE_UNUSED,
476 RK3562_PERI_CLKGATE_CON(1), 6, GFLAGS),
477 GATE(HCLK_SAI0, "hclk_sai0", "hclk_peri", 0,
478 RK3562_PERI_CLKGATE_CON(2), 0, GFLAGS),
479 COMPOSITE(CLK_SAI0_SRC, "clk_sai0_src", gpll_cpll_hpll_p, 0,
480 RK3562_PERI_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS,
481 RK3562_PERI_CLKGATE_CON(2), 1, GFLAGS),
482 COMPOSITE_FRACMUX(CLK_SAI0_FRAC, "clk_sai0_frac", "clk_sai0_src", CLK_SET_RATE_PARENT,
483 RK3562_PERI_CLKSEL_CON(2), 0,
484 RK3562_PERI_CLKGATE_CON(2), 2, GFLAGS,
485 &rk3562_clk_sai0_fracmux),
486 GATE(MCLK_SAI0, "mclk_sai0", "clk_sai0", 0,
487 RK3562_PERI_CLKGATE_CON(2), 3, GFLAGS),
488 COMPOSITE_NODIV(MCLK_SAI0_OUT2IO, "mclk_sai0_out2io", mclk_sai0_out2io_p, CLK_SET_RATE_PARENT,
489 RK3562_PERI_CLKSEL_CON(3), 5, 1, MFLAGS,
490 RK3562_PERI_CLKGATE_CON(2), 4, GFLAGS),
491 GATE(HCLK_SAI1, "hclk_sai1", "hclk_peri", 0,
492 RK3562_PERI_CLKGATE_CON(2), 5, GFLAGS),
493 COMPOSITE(CLK_SAI1_SRC, "clk_sai1_src", gpll_cpll_hpll_p, 0,
494 RK3562_PERI_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 6, DFLAGS,
495 RK3562_PERI_CLKGATE_CON(2), 6, GFLAGS),
496 COMPOSITE_FRACMUX(CLK_SAI1_FRAC, "clk_sai1_frac", "clk_sai1_src", CLK_SET_RATE_PARENT,
497 RK3562_PERI_CLKSEL_CON(4), 0,
498 RK3562_PERI_CLKGATE_CON(2), 7, GFLAGS,
499 &rk3562_clk_sai1_fracmux),
500 GATE(MCLK_SAI1, "mclk_sai1", "clk_sai1", 0,
501 RK3562_PERI_CLKGATE_CON(2), 8, GFLAGS),
502 COMPOSITE_NODIV(MCLK_SAI1_OUT2IO, "mclk_sai1_out2io", mclk_sai1_out2io_p, CLK_SET_RATE_PARENT,
503 RK3562_PERI_CLKSEL_CON(5), 5, 1, MFLAGS,
504 RK3562_PERI_CLKGATE_CON(2), 9, GFLAGS),
505 GATE(HCLK_SAI2, "hclk_sai2", "hclk_peri", 0,
506 RK3562_PERI_CLKGATE_CON(2), 10, GFLAGS),
507 COMPOSITE(CLK_SAI2_SRC, "clk_sai2_src", gpll_cpll_hpll_p, 0,
508 RK3562_PERI_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
509 RK3562_PERI_CLKGATE_CON(2), 11, GFLAGS),
510 COMPOSITE_FRACMUX(CLK_SAI2_FRAC, "clk_sai2_frac", "clk_sai2_src", CLK_SET_RATE_PARENT,
511 RK3562_PERI_CLKSEL_CON(7), 0,
512 RK3562_PERI_CLKGATE_CON(2), 12, GFLAGS,
513 &rk3562_clk_sai2_fracmux),
514 GATE(MCLK_SAI2, "mclk_sai2", "clk_sai2", 0,
515 RK3562_PERI_CLKGATE_CON(2), 13, GFLAGS),
516 COMPOSITE_NODIV(MCLK_SAI2_OUT2IO, "mclk_sai2_out2io", mclk_sai2_out2io_p, CLK_SET_RATE_PARENT,
517 RK3562_PERI_CLKSEL_CON(8), 5, 1, MFLAGS,
518 RK3562_PERI_CLKGATE_CON(2), 14, GFLAGS),
519 GATE(HCLK_DSM, "hclk_dsm", "hclk_peri", 0,
520 RK3562_PERI_CLKGATE_CON(3), 1, GFLAGS),
521 GATE(CLK_DSM, "clk_dsm", "mclk_sai1", 0,
522 RK3562_PERI_CLKGATE_CON(3), 2, GFLAGS),
523 GATE(HCLK_PDM, "hclk_pdm", "hclk_peri", 0,
524 RK3562_PERI_CLKGATE_CON(3), 4, GFLAGS),
525 COMPOSITE(MCLK_PDM, "mclk_pdm", gpll_cpll_hpll_xin24m_p, 0,
526 RK3562_PERI_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
527 RK3562_PERI_CLKGATE_CON(3), 5, GFLAGS),
528 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0,
529 RK3562_PERI_CLKGATE_CON(3), 8, GFLAGS),
530 COMPOSITE(CLK_SPDIF_SRC, "clk_spdif_src", gpll_cpll_hpll_p, 0,
531 RK3562_PERI_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 6, DFLAGS,
532 RK3562_PERI_CLKGATE_CON(3), 9, GFLAGS),
533 COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT,
534 RK3562_PERI_CLKSEL_CON(14), 0,
535 RK3562_PERI_CLKGATE_CON(3), 10, GFLAGS,
536 &rk3562_clk_spdif_fracmux),
537 GATE(MCLK_SPDIF, "mclk_spdif", "clk_spdif", 0,
538 RK3562_PERI_CLKGATE_CON(3), 11, GFLAGS),
539 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_peri", 0,
540 RK3562_PERI_CLKGATE_CON(4), 0, GFLAGS),
541 COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", gpll_cpll_xin24m_dmyhpll_p, 0,
542 RK3562_PERI_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS,
543 RK3562_PERI_CLKGATE_CON(4), 1, GFLAGS),
544 MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "cclk_sdmmc0", RK3562_SDMMC0_CON0, 1),
545 MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "cclk_sdmmc0", RK3562_SDMMC0_CON1, 1),
546 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_peri", 0,
547 RK3562_PERI_CLKGATE_CON(4), 2, GFLAGS),
548 COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", gpll_cpll_xin24m_dmyhpll_p, 0,
549 RK3562_PERI_CLKSEL_CON(17), 14, 2, MFLAGS, 0, 8, DFLAGS,
550 RK3562_PERI_CLKGATE_CON(4), 3, GFLAGS),
551 MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "cclk_sdmmc1", RK3562_SDMMC1_CON0, 1),
552 MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "cclk_sdmmc1", RK3562_SDMMC1_CON1, 1),
553 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0,
554 RK3562_PERI_CLKGATE_CON(4), 8, GFLAGS),
555 GATE(ACLK_EMMC, "aclk_emmc", "aclk_peri", 0,
556 RK3562_PERI_CLKGATE_CON(4), 9, GFLAGS),
557 COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_xin24m_dmyhpll_p, 0,
558 RK3562_PERI_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS,
559 RK3562_PERI_CLKGATE_CON(4), 10, GFLAGS),
560 COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0,
561 RK3562_PERI_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS,
562 RK3562_PERI_CLKGATE_CON(4), 11, GFLAGS),
563 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
564 RK3562_PERI_CLKGATE_CON(4), 12, GFLAGS),
565 COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_xin24m_p, 0,
566 RK3562_PERI_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
567 RK3562_PERI_CLKGATE_CON(4), 13, GFLAGS),
568 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0,
569 RK3562_PERI_CLKGATE_CON(4), 14, GFLAGS),
570 GATE(HCLK_USB2HOST, "hclk_usb2host", "hclk_peri", 0,
571 RK3562_PERI_CLKGATE_CON(5), 0, GFLAGS),
572 GATE(HCLK_USB2HOST_ARB, "hclk_usb2host_arb", "hclk_peri", 0,
573 RK3562_PERI_CLKGATE_CON(5), 1, GFLAGS),
574 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0,
575 RK3562_PERI_CLKGATE_CON(6), 0, GFLAGS),
576 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_xin24m_p, 0,
577 RK3562_PERI_CLKSEL_CON(20), 12, 2, MFLAGS,
578 RK3562_PERI_CLKGATE_CON(6), 1, GFLAGS),
579 GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0,
580 RK3562_PERI_CLKGATE_CON(6), 2, GFLAGS),
581 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0,
582 RK3562_PERI_CLKGATE_CON(6), 3, GFLAGS),
583 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_xin24m_p, 0,
584 RK3562_PERI_CLKSEL_CON(20), 14, 2, MFLAGS,
585 RK3562_PERI_CLKGATE_CON(6), 4, GFLAGS),
586 GATE(SCLK_IN_SPI2, "sclk_in_spi2", "sclk_in_spi2_io", 0,
587 RK3562_PERI_CLKGATE_CON(6), 5, GFLAGS),
588 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0,
589 RK3562_PERI_CLKGATE_CON(7), 0, GFLAGS),
590 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0,
591 RK3562_PERI_CLKGATE_CON(7), 1, GFLAGS),
592 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0,
593 RK3562_PERI_CLKGATE_CON(7), 2, GFLAGS),
594 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0,
595 RK3562_PERI_CLKGATE_CON(7), 3, GFLAGS),
596 GATE(PCLK_UART5, "pclk_uart5", "pclk_peri", 0,
597 RK3562_PERI_CLKGATE_CON(7), 4, GFLAGS),
598 GATE(PCLK_UART6, "pclk_uart6", "pclk_peri", 0,
599 RK3562_PERI_CLKGATE_CON(7), 5, GFLAGS),
600 GATE(PCLK_UART7, "pclk_uart7", "pclk_peri", 0,
601 RK3562_PERI_CLKGATE_CON(7), 6, GFLAGS),
602 GATE(PCLK_UART8, "pclk_uart8", "pclk_peri", 0,
603 RK3562_PERI_CLKGATE_CON(7), 7, GFLAGS),
604 GATE(PCLK_UART9, "pclk_uart9", "pclk_peri", 0,
605 RK3562_PERI_CLKGATE_CON(7), 8, GFLAGS),
606 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0,
607 RK3562_PERI_CLKSEL_CON(21), 8, 1, MFLAGS, 0, 7, DFLAGS,
608 RK3562_PERI_CLKGATE_CON(7), 9, GFLAGS),
609 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
610 RK3562_PERI_CLKSEL_CON(22), 0,
611 RK3562_PERI_CLKGATE_CON(7), 10, GFLAGS,
612 &rk3562_clk_uart1_fracmux),
613 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
614 RK3562_PERI_CLKGATE_CON(7), 11, GFLAGS),
615 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0,
616 RK3562_PERI_CLKSEL_CON(23), 8, 1, MFLAGS, 0, 7, DFLAGS,
617 RK3562_PERI_CLKGATE_CON(7), 12, GFLAGS),
618 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
619 RK3562_PERI_CLKSEL_CON(24), 0,
620 RK3562_PERI_CLKGATE_CON(7), 13, GFLAGS,
621 &rk3562_clk_uart2_fracmux),
622 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
623 RK3562_PERI_CLKGATE_CON(7), 14, GFLAGS),
624 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0,
625 RK3562_PERI_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
626 RK3562_PERI_CLKGATE_CON(7), 15, GFLAGS),
627 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3", CLK_SET_RATE_PARENT,
628 RK3562_PERI_CLKSEL_CON(26), 0,
629 RK3562_PERI_CLKGATE_CON(8), 0, GFLAGS,
630 &rk3562_clk_uart3_fracmux),
631 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
632 RK3562_PERI_CLKGATE_CON(8), 1, GFLAGS),
633 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0,
634 RK3562_PERI_CLKSEL_CON(27), 8, 1, MFLAGS, 0, 7, DFLAGS,
635 RK3562_PERI_CLKGATE_CON(8), 2, GFLAGS),
636 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
637 RK3562_PERI_CLKSEL_CON(28), 0,
638 RK3562_PERI_CLKGATE_CON(8), 3, GFLAGS,
639 &rk3562_clk_uart4_fracmux),
640 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
641 RK3562_PERI_CLKGATE_CON(8), 4, GFLAGS),
642 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0,
643 RK3562_PERI_CLKSEL_CON(29), 8, 1, MFLAGS, 0, 7, DFLAGS,
644 RK3562_PERI_CLKGATE_CON(8), 5, GFLAGS),
645 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
646 RK3562_PERI_CLKSEL_CON(30), 0,
647 RK3562_PERI_CLKGATE_CON(8), 6, GFLAGS,
648 &rk3562_clk_uart5_fracmux),
649 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
650 RK3562_PERI_CLKGATE_CON(8), 7, GFLAGS),
651 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0,
652 RK3562_PERI_CLKSEL_CON(31), 8, 1, MFLAGS, 0, 7, DFLAGS,
653 RK3562_PERI_CLKGATE_CON(8), 8, GFLAGS),
654 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
655 RK3562_PERI_CLKSEL_CON(32), 0,
656 RK3562_PERI_CLKGATE_CON(8), 9, GFLAGS,
657 &rk3562_clk_uart6_fracmux),
658 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
659 RK3562_PERI_CLKGATE_CON(8), 10, GFLAGS),
660 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0,
661 RK3562_PERI_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 7, DFLAGS,
662 RK3562_PERI_CLKGATE_CON(8), 11, GFLAGS),
663 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
664 RK3562_PERI_CLKSEL_CON(34), 0,
665 RK3562_PERI_CLKGATE_CON(8), 12, GFLAGS,
666 &rk3562_clk_uart7_fracmux),
667 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
668 RK3562_PERI_CLKGATE_CON(8), 13, GFLAGS),
669 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0,
670 RK3562_PERI_CLKSEL_CON(35), 8, 1, MFLAGS, 0, 7, DFLAGS,
671 RK3562_PERI_CLKGATE_CON(8), 14, GFLAGS),
672 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
673 RK3562_PERI_CLKSEL_CON(36), 0,
674 RK3562_PERI_CLKGATE_CON(8), 15, GFLAGS,
675 &rk3562_clk_uart8_fracmux),
676 GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0,
677 RK3562_PERI_CLKGATE_CON(9), 0, GFLAGS),
678 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0,
679 RK3562_PERI_CLKSEL_CON(37), 8, 1, MFLAGS, 0, 7, DFLAGS,
680 RK3562_PERI_CLKGATE_CON(9), 1, GFLAGS),
681 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
682 RK3562_PERI_CLKSEL_CON(38), 0,
683 RK3562_PERI_CLKGATE_CON(9), 2, GFLAGS,
684 &rk3562_clk_uart9_fracmux),
685 GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0,
686 RK3562_PERI_CLKGATE_CON(9), 3, GFLAGS),
687 GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri", 0,
688 RK3562_PERI_CLKGATE_CON(10), 0, GFLAGS),
689 COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_xin24m_p, 0,
690 RK3562_PERI_CLKSEL_CON(40), 0, 2, MFLAGS,
691 RK3562_PERI_CLKGATE_CON(10), 1, GFLAGS),
692 GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
693 RK3562_PERI_CLKGATE_CON(10), 2, GFLAGS),
694 GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri", 0,
695 RK3562_PERI_CLKGATE_CON(10), 3, GFLAGS),
696 COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_xin24m_p, 0,
697 RK3562_PERI_CLKSEL_CON(40), 6, 2, MFLAGS,
698 RK3562_PERI_CLKGATE_CON(10), 4, GFLAGS),
699 GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
700 RK3562_PERI_CLKGATE_CON(10), 5, GFLAGS),
701 GATE(PCLK_PWM3_PERI, "pclk_pwm3_peri", "pclk_peri", 0,
702 RK3562_PERI_CLKGATE_CON(10), 6, GFLAGS),
703 COMPOSITE_NODIV(CLK_PWM3_PERI, "clk_pwm3_peri", mux_100m_50m_xin24m_p, 0,
704 RK3562_PERI_CLKSEL_CON(40), 8, 2, MFLAGS,
705 RK3562_PERI_CLKGATE_CON(10), 7, GFLAGS),
706 GATE(CLK_CAPTURE_PWM3_PERI, "clk_capture_pwm3_peri", "xin24m", 0,
707 RK3562_PERI_CLKGATE_CON(10), 8, GFLAGS),
708 GATE(PCLK_CAN0, "pclk_can0", "pclk_peri", 0,
709 RK3562_PERI_CLKGATE_CON(11), 0, GFLAGS),
710 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
711 RK3562_PERI_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS,
712 RK3562_PERI_CLKGATE_CON(11), 1, GFLAGS),
713 GATE(PCLK_CAN1, "pclk_can1", "pclk_peri", 0,
714 RK3562_PERI_CLKGATE_CON(11), 2, GFLAGS),
715 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
716 RK3562_PERI_CLKSEL_CON(41), 15, 1, MFLAGS, 8, 5, DFLAGS,
717 RK3562_PERI_CLKGATE_CON(11), 3, GFLAGS),
718 GATE(PCLK_PERI_WDT, "pclk_peri_wdt", "pclk_peri", 0,
719 RK3562_PERI_CLKGATE_CON(13), 0, GFLAGS),
720 COMPOSITE_NODIV(TCLK_PERI_WDT, "tclk_peri_wdt", mux_xin24m_32k_p, 0,
721 RK3562_PERI_CLKSEL_CON(43), 15, 1, MFLAGS,
722 RK3562_PERI_CLKGATE_CON(13), 1, GFLAGS),
723 GATE(ACLK_SYSMEM, "aclk_sysmem", "aclk_peri", CLK_IGNORE_UNUSED,
724 RK3562_PERI_CLKGATE_CON(13), 2, GFLAGS),
725 GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri", CLK_IGNORE_UNUSED,
726 RK3562_PERI_CLKGATE_CON(13), 3, GFLAGS),
727 GATE(PCLK_PERI_GRF, "pclk_peri_grf", "pclk_peri", CLK_IGNORE_UNUSED,
728 RK3562_PERI_CLKGATE_CON(13), 4, GFLAGS),
729 GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0,
730 RK3562_PERI_CLKGATE_CON(13), 5, GFLAGS),
731 GATE(ACLK_RKDMAC, "aclk_rkdmac", "aclk_peri", 0,
732 RK3562_PERI_CLKGATE_CON(13), 6, GFLAGS),
733 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri", 0,
734 RK3562_PERI_CLKGATE_CON(14), 0, GFLAGS),
735 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
736 RK3562_PERI_CLKGATE_CON(14), 1, GFLAGS),
737 COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
738 RK3562_PERI_CLKSEL_CON(44), 0, 8, DFLAGS,
739 RK3562_PERI_CLKGATE_CON(14), 2, GFLAGS),
740 GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri", CLK_IGNORE_UNUSED,
741 RK3562_PERI_CLKGATE_CON(14), 3, GFLAGS),
742 GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", CLK_IGNORE_UNUSED,
743 RK3562_PERI_CLKGATE_CON(14), 4, GFLAGS),
744 COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", CLK_IGNORE_UNUSED,
745 RK3562_PERI_CLKSEL_CON(44), 8, 8, DFLAGS,
746 RK3562_PERI_CLKGATE_CON(14), 5, GFLAGS),
747 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
748 RK3562_PERI_CLKGATE_CON(14), 6, GFLAGS),
749 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_peri", 0,
750 RK3562_PERI_CLKGATE_CON(14), 7, GFLAGS),
751 GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri", 0,
752 RK3562_PERI_CLKGATE_CON(15), 0, GFLAGS),
753 GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri", 0,
754 RK3562_PERI_CLKGATE_CON(15), 7, GFLAGS),
755 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0,
756 RK3562_PERI_CLKGATE_CON(16), 4, GFLAGS),
757 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
758 RK3562_PERI_CLKSEL_CON(46), 0, 12, DFLAGS,
759 RK3562_PERI_CLKGATE_CON(16), 5, GFLAGS),
760 GATE(PCLK_IOC_VCCIO234, "pclk_ioc_vccio234", "pclk_peri", CLK_IS_CRITICAL,
761 RK3562_PERI_CLKGATE_CON(16), 12, GFLAGS),
762 GATE(PCLK_PERI_GPIO1, "pclk_peri_gpio1", "pclk_peri", 0,
763 RK3562_PERI_CLKGATE_CON(17), 0, GFLAGS),
764 GATE(PCLK_PERI_GPIO2, "pclk_peri_gpio2", "pclk_peri", 0,
765 RK3562_PERI_CLKGATE_CON(17), 1, GFLAGS),
766 COMPOSITE_NODIV(DCLK_PERI_GPIO, "dclk_peri_gpio", mux_xin24m_32k_p, 0,
767 RK3562_PERI_CLKSEL_CON(47), 8, 1, MFLAGS,
768 RK3562_PERI_CLKGATE_CON(17), 4, GFLAGS),
769 GATE(DCLK_PERI_GPIO1, "dclk_peri_gpio1", "dclk_peri_gpio", 0,
770 RK3562_PERI_CLKGATE_CON(17), 2, GFLAGS),
771 GATE(DCLK_PERI_GPIO2, "dclk_peri_gpio2", "dclk_peri_gpio", 0,
772 RK3562_PERI_CLKGATE_CON(17), 3, GFLAGS),
773
774 /* PD_PHP */
775 COMPOSITE(ACLK_PHP, "aclk_php", gpll_cpll_p, 0,
776 RK3562_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 4, DFLAGS,
777 RK3562_CLKGATE_CON(16), 0, GFLAGS),
778 COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0,
779 RK3562_CLKSEL_CON(36), 8, 4, DFLAGS,
780 RK3562_CLKGATE_CON(16), 1, GFLAGS),
781 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_php", 0,
782 RK3562_CLKGATE_CON(16), 4, GFLAGS),
783 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_php", 0,
784 RK3562_CLKGATE_CON(16), 5, GFLAGS),
785 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_php", 0,
786 RK3562_CLKGATE_CON(16), 6, GFLAGS),
787 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_php", 0,
788 RK3562_CLKGATE_CON(16), 7, GFLAGS),
789 GATE(CLK_PCIE20_AUX, "clk_pcie20_aux", "xin24m", 0,
790 RK3562_CLKGATE_CON(16), 8, GFLAGS),
791 GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_php", 0,
792 RK3562_CLKGATE_CON(16), 10, GFLAGS),
793 COMPOSITE_NODIV(CLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0,
794 RK3562_CLKSEL_CON(36), 15, 1, MFLAGS,
795 RK3562_CLKGATE_CON(16), 11, GFLAGS),
796 GATE(CLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0,
797 RK3562_CLKGATE_CON(16), 12, GFLAGS),
798 GATE(CLK_PIPEPHY_REF_FUNC, "clk_pipephy_ref_func", "pclk_pcie20", 0,
799 RK3562_CLKGATE_CON(17), 3, GFLAGS),
800
801 /* PD_PMU1 */
802 COMPOSITE_NOMUX(CLK_200M_PMU, "clk_200m_pmu", "cpll", CLK_IS_CRITICAL,
803 RK3562_PMU1_CLKSEL_CON(0), 0, 5, DFLAGS,
804 RK3562_PMU1_CLKGATE_CON(0), 1, GFLAGS),
805 /* PD_PMU0 */
806 COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IS_CRITICAL,
807 RK3562_PMU0_CLKSEL_CON(0), 0,
808 RK3562_PMU0_CLKGATE_CON(0), 15, GFLAGS,
809 &rk3562_rtc32k_pmu_fracmux),
810 COMPOSITE_NOMUX(BUSCLK_PDPMU0, "busclk_pdpmu0", "clk_200m_pmu", CLK_IS_CRITICAL,
811 RK3562_PMU0_CLKSEL_CON(1), 3, 2, DFLAGS,
812 RK3562_PMU0_CLKGATE_CON(0), 14, GFLAGS),
813 GATE(PCLK_PMU0_CRU, "pclk_pmu0_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
814 RK3562_PMU0_CLKGATE_CON(0), 0, GFLAGS),
815 GATE(PCLK_PMU0_PMU, "pclk_pmu0_pmu", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
816 RK3562_PMU0_CLKGATE_CON(0), 1, GFLAGS),
817 GATE(CLK_PMU0_PMU, "clk_pmu0_pmu", "xin24m", CLK_IGNORE_UNUSED,
818 RK3562_PMU0_CLKGATE_CON(0), 2, GFLAGS),
819 GATE(PCLK_PMU0_HP_TIMER, "pclk_pmu0_hp_timer", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
820 RK3562_PMU0_CLKGATE_CON(0), 3, GFLAGS),
821 GATE(CLK_PMU0_HP_TIMER, "clk_pmu0_hp_timer", "xin24m", CLK_IGNORE_UNUSED,
822 RK3562_PMU0_CLKGATE_CON(0), 4, GFLAGS),
823 GATE(CLK_PMU0_32K_HP_TIMER, "clk_pmu0_32k_hp_timer", "clk_rtc_32k", CLK_IGNORE_UNUSED,
824 RK3562_PMU0_CLKGATE_CON(0), 5, GFLAGS),
825 GATE(PCLK_PMU0_PVTM, "pclk_pmu0_pvtm", "busclk_pdpmu0", 0,
826 RK3562_PMU0_CLKGATE_CON(0), 6, GFLAGS),
827 GATE(CLK_PMU0_PVTM, "clk_pmu0_pvtm", "xin24m", 0,
828 RK3562_PMU0_CLKGATE_CON(0), 7, GFLAGS),
829 GATE(PCLK_IOC_PMUIO, "pclk_ioc_pmuio", "busclk_pdpmu0", CLK_IS_CRITICAL,
830 RK3562_PMU0_CLKGATE_CON(0), 8, GFLAGS),
831 GATE(PCLK_PMU0_GPIO0, "pclk_pmu0_gpio0", "busclk_pdpmu0", 0,
832 RK3562_PMU0_CLKGATE_CON(0), 9, GFLAGS),
833 GATE(DBCLK_PMU0_GPIO0, "dbclk_pmu0_gpio0", "xin24m", 0,
834 RK3562_PMU0_CLKGATE_CON(0), 10, GFLAGS),
835 GATE(PCLK_PMU0_GRF, "pclk_pmu0_grf", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
836 RK3562_PMU0_CLKGATE_CON(0), 11, GFLAGS),
837 GATE(PCLK_PMU0_SGRF, "pclk_pmu0_sgrf", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
838 RK3562_PMU0_CLKGATE_CON(0), 12, GFLAGS),
839 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
840 RK3562_PMU0_CLKGATE_CON(1), 0, GFLAGS),
841 GATE(PCLK_PMU0_SCRKEYGEN, "pclk_pmu0_scrkeygen", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
842 RK3562_PMU0_CLKGATE_CON(1), 1, GFLAGS),
843 COMPOSITE_NOMUX(CLK_PIPEPHY_DIV, "clk_pipephy_div", "cpll", 0,
844 RK3562_PMU0_CLKSEL_CON(2), 0, 6, DFLAGS,
845 RK3562_PMU0_CLKGATE_CON(2), 0, GFLAGS),
846 GATE(CLK_PIPEPHY_XIN24M, "clk_pipephy_xin24m", "xin24m", 0,
847 RK3562_PMU0_CLKGATE_CON(2), 1, GFLAGS),
848 COMPOSITE_NODIV(CLK_PIPEPHY_REF, "clk_pipephy_ref", clk_pipephy_ref_p, 0,
849 RK3562_PMU0_CLKSEL_CON(2), 7, 1, MFLAGS,
850 RK3562_PMU0_CLKGATE_CON(2), 2, GFLAGS),
851 GATE(CLK_USB2PHY_XIN24M, "clk_usb2phy_xin24m", "xin24m", 0,
852 RK3562_PMU0_CLKGATE_CON(2), 4, GFLAGS),
853 COMPOSITE_NODIV(CLK_USB2PHY_REF, "clk_usb2phy_ref", clk_usbphy_ref_p, 0,
854 RK3562_PMU0_CLKSEL_CON(2), 8, 1, MFLAGS,
855 RK3562_PMU0_CLKGATE_CON(2), 5, GFLAGS),
856 GATE(CLK_MIPIDSIPHY_XIN24M, "clk_mipidsiphy_xin24m", "xin24m", 0,
857 RK3562_PMU0_CLKGATE_CON(2), 6, GFLAGS),
858 COMPOSITE_NODIV(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", clk_mipidsi_ref_p, 0,
859 RK3562_PMU0_CLKSEL_CON(2), 15, 1, MFLAGS,
860 RK3562_PMU0_CLKGATE_CON(2), 7, GFLAGS),
861 GATE(PCLK_PMU0_I2C0, "pclk_pmu0_i2c0", "busclk_pdpmu0", 0,
862 RK3562_PMU0_CLKGATE_CON(2), 8, GFLAGS),
863 COMPOSITE(CLK_PMU0_I2C0, "clk_pmu0_i2c0", mux_200m_xin24m_32k_p, 0,
864 RK3562_PMU0_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 5, DFLAGS,
865 RK3562_PMU0_CLKGATE_CON(2), 9, GFLAGS),
866 /* PD_PMU1 */
867 GATE(PCLK_PMU1_CRU, "pclk_pmu1_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
868 RK3562_PMU1_CLKGATE_CON(0), 0, GFLAGS),
869 GATE(HCLK_PMU1_MEM, "hclk_pmu1_mem", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
870 RK3562_PMU1_CLKGATE_CON(0), 2, GFLAGS),
871 GATE(PCLK_PMU1_UART0, "pclk_pmu1_uart0", "busclk_pdpmu0", 0,
872 RK3562_PMU1_CLKGATE_CON(0), 7, GFLAGS),
873 COMPOSITE_NOMUX(CLK_PMU1_UART0_SRC, "clk_pmu1_uart0_src", "cpll", 0,
874 RK3562_PMU1_CLKSEL_CON(2), 0, 4, DFLAGS,
875 RK3562_PMU1_CLKGATE_CON(0), 8, GFLAGS),
876 COMPOSITE_FRACMUX(CLK_PMU1_UART0_FRAC, "clk_pmu1_uart0_frac", "clk_pmu1_uart0_src", CLK_SET_RATE_PARENT,
877 RK3562_PMU1_CLKSEL_CON(3), 0,
878 RK3562_PMU1_CLKGATE_CON(0), 9, GFLAGS,
879 &rk3562_clk_pmu1_uart0_fracmux),
880 GATE(SCLK_PMU1_UART0, "sclk_pmu1_uart0", "clk_pmu1_uart0", 0,
881 RK3562_PMU1_CLKGATE_CON(0), 10, GFLAGS),
882 GATE(PCLK_PMU1_SPI0, "pclk_pmu1_spi0", "busclk_pdpmu0", 0,
883 RK3562_PMU1_CLKGATE_CON(1), 0, GFLAGS),
884 COMPOSITE(CLK_PMU1_SPI0, "clk_pmu1_spi0", mux_200m_xin24m_32k_p, 0,
885 RK3562_PMU1_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 2, DFLAGS,
886 RK3562_PMU1_CLKGATE_CON(1), 1, GFLAGS),
887 GATE(SCLK_IN_PMU1_SPI0, "sclk_in_pmu1_spi0", "sclk_in_pmu1_spi0_io", 0,
888 RK3562_PMU1_CLKGATE_CON(1), 2, GFLAGS),
889 GATE(PCLK_PMU1_PWM0, "pclk_pmu1_pwm0", "busclk_pdpmu0", 0,
890 RK3562_PMU1_CLKGATE_CON(1), 3, GFLAGS),
891 COMPOSITE(CLK_PMU1_PWM0, "clk_pmu1_pwm0", mux_200m_xin24m_32k_p, 0,
892 RK3562_PMU1_CLKSEL_CON(4), 14, 2, MFLAGS, 8, 2, DFLAGS,
893 RK3562_PMU1_CLKGATE_CON(1), 4, GFLAGS),
894 GATE(CLK_CAPTURE_PMU1_PWM0, "clk_capture_pmu1_pwm0", "xin24m", 0,
895 RK3562_PMU1_CLKGATE_CON(1), 5, GFLAGS),
896 GATE(CLK_PMU1_WIFI, "clk_pmu1_wifi", "xin24m", 0,
897 RK3562_PMU1_CLKGATE_CON(1), 6, GFLAGS),
898 GATE(FCLK_PMU1_CM0_CORE, "fclk_pmu1_cm0_core", "busclk_pdpmu0", 0,
899 RK3562_PMU1_CLKGATE_CON(2), 0, GFLAGS),
900 GATE(CLK_PMU1_CM0_RTC, "clk_pmu1_cm0_rtc", "clk_rtc_32k", 0,
901 RK3562_PMU1_CLKGATE_CON(2), 1, GFLAGS),
902 GATE(PCLK_PMU1_WDTNS, "pclk_pmu1_wdtns", "busclk_pdpmu0", 0,
903 RK3562_PMU1_CLKGATE_CON(2), 3, GFLAGS),
904 GATE(CLK_PMU1_WDTNS, "clk_pmu1_wdtns", "xin24m", 0,
905 RK3562_PMU1_CLKGATE_CON(2), 4, GFLAGS),
906 GATE(PCLK_PMU1_MAILBOX, "pclk_pmu1_mailbox", "busclk_pdpmu0", 0,
907 RK3562_PMU1_CLKGATE_CON(3), 8, GFLAGS),
908
909 /* PD_RGA */
910 COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", gpll_cpll_pvtpll_dmyapll_p, 0,
911 RK3562_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 4, DFLAGS,
912 RK3562_CLKGATE_CON(14), 0, GFLAGS),
913 COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_jdec", 0,
914 RK3562_CLKSEL_CON(32), 8, 3, DFLAGS,
915 RK3562_CLKGATE_CON(14), 1, GFLAGS),
916 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_jdec", 0,
917 RK3562_CLKGATE_CON(14), 6, GFLAGS),
918 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
919 RK3562_CLKGATE_CON(14), 7, GFLAGS),
920 COMPOSITE(CLK_RGA_CORE, "clk_rga_core", gpll_cpll_pvtpll_dmyapll_p, 0,
921 RK3562_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 4, DFLAGS,
922 RK3562_CLKGATE_CON(14), 8, GFLAGS),
923 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_jdec", 0,
924 RK3562_CLKGATE_CON(14), 9, GFLAGS),
925 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
926 RK3562_CLKGATE_CON(14), 10, GFLAGS),
927
928 /* PD_VDPU */
929 COMPOSITE(ACLK_VDPU_PRE, "aclk_vdpu_pre", gpll_cpll_pvtpll_dmyapll_p, 0,
930 RK3562_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 5, DFLAGS,
931 RK3562_CLKGATE_CON(10), 0, GFLAGS),
932 COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_pvtpll_dmyapll_p, 0,
933 RK3562_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 5, DFLAGS,
934 RK3562_CLKGATE_CON(10), 3, GFLAGS),
935 COMPOSITE_NOMUX(HCLK_VDPU_PRE, "hclk_vdpu_pre", "aclk_vdpu", 0,
936 RK3562_CLKSEL_CON(24), 0, 4, DFLAGS,
937 RK3562_CLKGATE_CON(10), 4, GFLAGS),
938 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_vdpu", 0,
939 RK3562_CLKGATE_CON(10), 7, GFLAGS),
940 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdpu_pre", 0,
941 RK3562_CLKGATE_CON(10), 8, GFLAGS),
942
943 /* PD_VEPU */
944 COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_pvtpll_dmyapll_p, 0,
945 RK3562_CLKSEL_CON(20), 6, 2, MFLAGS, 0, 5, DFLAGS,
946 RK3562_CLKGATE_CON(9), 0, GFLAGS),
947 COMPOSITE(ACLK_VEPU_PRE, "aclk_vepu_pre", gpll_cpll_pvtpll_dmyapll_p, 0,
948 RK3562_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
949 RK3562_CLKGATE_CON(9), 1, GFLAGS),
950 COMPOSITE_NOMUX(HCLK_VEPU_PRE, "hclk_vepu_pre", "aclk_vepu", 0,
951 RK3562_CLKSEL_CON(21), 0, 4, DFLAGS,
952 RK3562_CLKGATE_CON(9), 2, GFLAGS),
953 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_vepu", 0,
954 RK3562_CLKGATE_CON(9), 5, GFLAGS),
955 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_vepu", 0,
956 RK3562_CLKGATE_CON(9), 6, GFLAGS),
957
958 /* PD_VI */
959 COMPOSITE(ACLK_VI, "aclk_vi", gpll_cpll_pvtpll_dmyapll_p, 0,
960 RK3562_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 4, DFLAGS,
961 RK3562_CLKGATE_CON(11), 0, GFLAGS),
962 COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi_isp", 0,
963 RK3562_CLKSEL_CON(26), 0, 4, DFLAGS,
964 RK3562_CLKGATE_CON(11), 1, GFLAGS),
965 COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi_isp", 0,
966 RK3562_CLKSEL_CON(26), 8, 4, DFLAGS,
967 RK3562_CLKGATE_CON(11), 2, GFLAGS),
968 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_isp", 0,
969 RK3562_CLKGATE_CON(11), 6, GFLAGS),
970 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
971 RK3562_CLKGATE_CON(11), 7, GFLAGS),
972 COMPOSITE(CLK_ISP, "clk_isp", gpll_cpll_pvtpll_dmyapll_p, 0,
973 RK3562_CLKSEL_CON(27), 6, 2, MFLAGS, 0, 4, DFLAGS,
974 RK3562_CLKGATE_CON(11), 8, GFLAGS),
975 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_isp", 0,
976 RK3562_CLKGATE_CON(11), 9, GFLAGS),
977 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0,
978 RK3562_CLKGATE_CON(11), 10, GFLAGS),
979 COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_pvtpll_dmyapll_p, 0,
980 RK3562_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 4, DFLAGS,
981 RK3562_CLKGATE_CON(11), 11, GFLAGS),
982 GATE(CSIRX0_CLK_DATA, "csirx0_clk_data", "csirx0_clk_data_io", 0,
983 RK3562_CLKGATE_CON(11), 12, GFLAGS),
984 GATE(CSIRX1_CLK_DATA, "csirx1_clk_data", "csirx1_clk_data_io", 0,
985 RK3562_CLKGATE_CON(11), 13, GFLAGS),
986 GATE(CSIRX2_CLK_DATA, "csirx2_clk_data", "csirx2_clk_data_io", 0,
987 RK3562_CLKGATE_CON(11), 14, GFLAGS),
988 GATE(CSIRX3_CLK_DATA, "csirx3_clk_data", "csirx3_clk_data_io", 0,
989 RK3562_CLKGATE_CON(11), 15, GFLAGS),
990 GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi", 0,
991 RK3562_CLKGATE_CON(12), 0, GFLAGS),
992 GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi", 0,
993 RK3562_CLKGATE_CON(12), 1, GFLAGS),
994 GATE(PCLK_CSIHOST2, "pclk_csihost2", "pclk_vi", 0,
995 RK3562_CLKGATE_CON(12), 2, GFLAGS),
996 GATE(PCLK_CSIHOST3, "pclk_csihost3", "pclk_vi", 0,
997 RK3562_CLKGATE_CON(12), 3, GFLAGS),
998 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi", 0,
999 RK3562_CLKGATE_CON(12), 4, GFLAGS),
1000 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi", 0,
1001 RK3562_CLKGATE_CON(12), 5, GFLAGS),
1002
1003 /* PD_VO */
1004 COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", gpll_cpll_vpll_dmyhpll_p, 0,
1005 RK3562_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
1006 RK3562_CLKGATE_CON(13), 0, GFLAGS),
1007 COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo", 0,
1008 RK3562_CLKSEL_CON(29), 0, 5, DFLAGS,
1009 RK3562_CLKGATE_CON(13), 1, GFLAGS),
1010 GATE(ACLK_VOP, "aclk_vop", "aclk_vo", 0,
1011 RK3562_CLKGATE_CON(13), 6, GFLAGS),
1012 GATE(HCLK_VOP, "hclk_vop", "hclk_vo_pre", 0,
1013 RK3562_CLKGATE_CON(13), 7, GFLAGS),
1014 COMPOSITE(DCLK_VOP, "dclk_vop", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1015 RK3562_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 8, DFLAGS,
1016 RK3562_CLKGATE_CON(13), 8, GFLAGS),
1017 COMPOSITE(DCLK_VOP1, "dclk_vop1", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1018 RK3562_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 8, DFLAGS,
1019 RK3562_CLKGATE_CON(13), 9, GFLAGS),
1020 };
1021
1022 static void __iomem *rk3562_cru_base;
1023
rk3562_dump_cru(void)1024 static void rk3562_dump_cru(void)
1025 {
1026 if (rk3562_cru_base) {
1027 pr_warn("CRU:\n");
1028 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1029 32, 4, rk3562_cru_base,
1030 0x600, false);
1031 }
1032 }
1033
1034 static int protect_clocks[] = {
1035 ACLK_VO_PRE,
1036 HCLK_VO_PRE,
1037 ACLK_VOP,
1038 HCLK_VOP,
1039 DCLK_VOP,
1040 DCLK_VOP1,
1041 };
1042
rk3562_clk_init(struct device_node * np)1043 static void __init rk3562_clk_init(struct device_node *np)
1044 {
1045 struct rockchip_clk_provider *ctx;
1046 void __iomem *reg_base;
1047
1048 reg_base = of_iomap(np, 0);
1049 if (!reg_base) {
1050 pr_err("%s: could not map cru region\n", __func__);
1051 return;
1052 }
1053
1054 rk3562_cru_base = reg_base;
1055
1056 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1057 if (IS_ERR(ctx)) {
1058 pr_err("%s: rockchip clk init failed\n", __func__);
1059 iounmap(reg_base);
1060 return;
1061 }
1062
1063 rockchip_clk_register_plls(ctx, rk3562_pll_clks,
1064 ARRAY_SIZE(rk3562_pll_clks),
1065 RK3562_GRF_SOC_STATUS0);
1066
1067 rockchip_clk_register_branches(ctx, rk3562_clk_branches,
1068 ARRAY_SIZE(rk3562_clk_branches));
1069
1070 /* (0x30444 - 0x400) / 4 + 1 = 49170 */
1071 rockchip_register_softrst(np, 49170, reg_base + RK3562_SOFTRST_CON(0),
1072 ROCKCHIP_SOFTRST_HIWORD_MASK);
1073
1074 rockchip_register_restart_notifier(ctx, RK3562_GLB_SRST_FST, NULL);
1075
1076 rockchip_clk_of_add_provider(np, ctx);
1077
1078 if (!rk_dump_cru)
1079 rk_dump_cru = rk3562_dump_cru;
1080
1081 rockchip_clk_protect(ctx, protect_clocks, ARRAY_SIZE(protect_clocks));
1082 }
1083
1084 CLK_OF_DECLARE(rk3562_cru, "rockchip,rk3562-cru", rk3562_clk_init);
1085
1086 #ifdef MODULE
1087 struct clk_rk3562_inits {
1088 void (*inits)(struct device_node *np);
1089 };
1090
1091 static const struct clk_rk3562_inits clk_3562_cru_init = {
1092 .inits = rk3562_clk_init,
1093 };
1094
1095 static const struct of_device_id clk_rk3562_match_table[] = {
1096 {
1097 .compatible = "rockchip,rk3562-cru",
1098 .data = &clk_3562_cru_init,
1099 },
1100 { }
1101 };
1102 MODULE_DEVICE_TABLE(of, clk_rk3562_match_table);
1103
clk_rk3562_probe(struct platform_device * pdev)1104 static int clk_rk3562_probe(struct platform_device *pdev)
1105 {
1106 struct device_node *np = pdev->dev.of_node;
1107 const struct of_device_id *match;
1108 const struct clk_rk3562_inits *init_data;
1109
1110 match = of_match_device(clk_rk3562_match_table, &pdev->dev);
1111 if (!match || !match->data)
1112 return -EINVAL;
1113
1114 init_data = match->data;
1115 if (init_data->inits)
1116 init_data->inits(np);
1117
1118 return 0;
1119 }
1120
1121 static struct platform_driver clk_rk3562_driver = {
1122 .probe = clk_rk3562_probe,
1123 .driver = {
1124 .name = "clk-rk3562",
1125 .of_match_table = clk_rk3562_match_table,
1126 .suppress_bind_attrs = true,
1127 },
1128 };
1129 module_platform_driver(clk_rk3562_driver);
1130
1131 MODULE_DESCRIPTION("Rockchip RK3562 Clock Driver");
1132 MODULE_LICENSE("GPL");
1133 MODULE_ALIAS("platform:clk-rk3562");
1134 #endif /* MODULE */
1135