1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/regmap.h>
14 #include <linux/syscore_ops.h>
15 #include <dt-bindings/clock/rv1106-cru.h>
16 #include "clk.h"
17
18 #define CRU_PVTPLL0_CON0_L 0x11000
19 #define CRU_PVTPLL0_CON0_H 0x11004
20 #define CRU_PVTPLL0_CON1_L 0x11008
21 #define CRU_PVTPLL0_CON1_H 0x1100c
22 #define CRU_PVTPLL0_CON2_L 0x11010
23 #define CRU_PVTPLL0_CON2_H 0x11014
24 #define CRU_PVTPLL0_CON3_L 0x11018
25 #define CRU_PVTPLL0_CON3_H 0x1101c
26 #define CRU_PVTPLL0_OSC_CNT 0x11020
27 #define CRU_PVTPLL0_OSC_CNT_AVG 0x11024
28
29 #define CRU_PVTPLL1_CON0_L 0x11030
30 #define CRU_PVTPLL1_CON0_H 0x11034
31 #define CRU_PVTPLL1_CON1_L 0x11038
32 #define CRU_PVTPLL1_CON1_H 0x1103c
33 #define CRU_PVTPLL1_CON2_L 0x11040
34 #define CRU_PVTPLL1_CON2_H 0x11044
35 #define CRU_PVTPLL1_CON3_L 0x11048
36 #define CRU_PVTPLL1_CON3_H 0x1104c
37 #define CRU_PVTPLL1_OSC_CNT 0x11050
38 #define CRU_PVTPLL1_OSC_CNT_AVG 0x11054
39
40 #define RV1106_GRF_SOC_STATUS0 0x10
41 #define CPU_PVTPLL_CON0_L 0x40000
42 #define CPU_PVTPLL_CON0_H 0x40004
43 #define CPU_PVTPLL_CON1 0x40008
44 #define CPU_PVTPLL_CON2 0x4000c
45 #define CPU_PVTPLL_CON3 0x40010
46 #define CPU_PVTPLL_OSC_CNT 0x40018
47 #define CPU_PVTPLL_OSC_CNT_AVG 0x4001c
48
49 #define PVTPLL_RING_SEL_MASK 0x7
50 #define PVTPLL_RING_SEL_SHIFT 8
51 #define PVTPLL_EN_MASK 0x3
52 #define PVTPLL_EN_SHIFT 0
53 #define PVTPLL_LENGTH_SEL_MASK 0x7f
54 #define PVTPLL_LENGTH_SEL_SHIFT 0
55
56 #define CPU_CLK_PATH_BASE (0x18300)
57 #define CPU_PVTPLL_PATH_CORE ((1 << 12) | (1 << 28))
58
59 #define RV1106_FRAC_MAX_PRATE 1200000000
60
61 enum rv1106_plls {
62 apll, dpll, cpll, gpll,
63 };
64
65 static struct rockchip_pll_rate_table rv1106_pll_rates[] = {
66 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
67 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
70 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
71 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
72 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
73 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
74 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
75 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
76 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
77 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
78 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
79 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
80 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
81 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
82 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
83 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
84 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
85 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
86 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
87 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
88 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
89 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
90 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
91 RK3036_PLL_RATE(993484800, 1, 124, 3, 1, 0, 3113851),
92 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
93 RK3036_PLL_RATE(983040000, 1, 81, 2, 1, 0, 15435038),
94 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
95 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
96 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
97 RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
98 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
99 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
100 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
101 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
102 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
103 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
104 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
105 RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
106 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
107 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
108 RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
109 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
110 RK3036_PLL_RATE(496742400, 1, 124, 6, 1, 0, 3113851),
111 RK3036_PLL_RATE(491520000, 1, 40, 2, 1, 0, 16106127),
112 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
113 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
114 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
115 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
116 { /* sentinel */ },
117 };
118
119 #define RV1106_DIV_ACLK_CORE_MASK 0x1f
120 #define RV1106_DIV_ACLK_CORE_SHIFT 7
121 #define RV1106_DIV_PCLK_DBG_MASK 0x1f
122 #define RV1106_DIV_PCLK_DBG_SHIFT 0
123 #define RV1106_CORE_SEL_MASK 0x3
124 #define RV1106_CORE_SEL_SHIFT 5
125 #define RV1106_ALT_DIV_MASK 0x1f
126 #define RV1106_ALT_DIV_SHIFT 0
127
128 #define RV1106_CLKSEL0(_aclk_core) \
129 { \
130 .reg = RV1106_CORECLKSEL_CON(0), \
131 .val = HIWORD_UPDATE(_aclk_core, RV1106_DIV_ACLK_CORE_MASK, \
132 RV1106_DIV_ACLK_CORE_SHIFT), \
133 }
134
135 #define RV1106_CLKSEL1(_pclk_dbg) \
136 { \
137 .reg = RV1106_CORECLKSEL_CON(1), \
138 .val = HIWORD_UPDATE(_pclk_dbg, RV1106_DIV_PCLK_DBG_MASK, \
139 RV1106_DIV_PCLK_DBG_SHIFT), \
140 }
141
142 #define RV1106_CLKSEL2(_is_pvtpll) \
143 { \
144 .reg = RV1106_CORECLKSEL_CON(0), \
145 .val = HIWORD_UPDATE(_is_pvtpll, RV1106_CORE_SEL_MASK, \
146 RV1106_CORE_SEL_SHIFT), \
147 }
148
149 #define RV1106_CLKSEL3(_alt_div) \
150 { \
151 .reg = RV1106_CORECLKSEL_CON(0), \
152 .val = HIWORD_UPDATE(_alt_div, RV1106_ALT_DIV_MASK, \
153 RV1106_ALT_DIV_SHIFT), \
154 }
155
156 #define RV1106_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg, _is_pvtpll) \
157 { \
158 .prate = _prate, \
159 .divs = { \
160 RV1106_CLKSEL0(_aclk_core), \
161 RV1106_CLKSEL1(_pclk_dbg), \
162 }, \
163 .pre_muxs = { \
164 RV1106_CLKSEL3(1), \
165 RV1106_CLKSEL2(2), \
166 }, \
167 .post_muxs = { \
168 RV1106_CLKSEL2(_is_pvtpll), \
169 RV1106_CLKSEL3(0), \
170 }, \
171 }
172
173 static struct rockchip_cpuclk_rate_table rv1106_cpuclk_rates[] __initdata = {
174 RV1106_CPUCLK_RATE(1608000000, 3, 7, 1),
175 RV1106_CPUCLK_RATE(1584000000, 3, 7, 1),
176 RV1106_CPUCLK_RATE(1560000000, 3, 7, 1),
177 RV1106_CPUCLK_RATE(1536000000, 3, 7, 1),
178 RV1106_CPUCLK_RATE(1512000000, 3, 7, 1),
179 RV1106_CPUCLK_RATE(1488000000, 2, 5, 1),
180 RV1106_CPUCLK_RATE(1464000000, 2, 5, 1),
181 RV1106_CPUCLK_RATE(1440000000, 2, 5, 1),
182 RV1106_CPUCLK_RATE(1416000000, 2, 5, 1),
183 RV1106_CPUCLK_RATE(1392000000, 2, 5, 1),
184 RV1106_CPUCLK_RATE(1368000000, 2, 5, 1),
185 RV1106_CPUCLK_RATE(1344000000, 2, 5, 1),
186 RV1106_CPUCLK_RATE(1320000000, 2, 5, 1),
187 RV1106_CPUCLK_RATE(1296000000, 2, 5, 1),
188 RV1106_CPUCLK_RATE(1272000000, 2, 5, 1),
189 RV1106_CPUCLK_RATE(1248000000, 2, 5, 1),
190 RV1106_CPUCLK_RATE(1224000000, 2, 5, 1),
191 RV1106_CPUCLK_RATE(1200000000, 2, 5, 1),
192 RV1106_CPUCLK_RATE(1104000000, 2, 5, 1),
193 RV1106_CPUCLK_RATE(1096000000, 2, 5, 1),
194 RV1106_CPUCLK_RATE(1008000000, 1, 5, 1),
195 RV1106_CPUCLK_RATE(912000000, 1, 5, 1),
196 RV1106_CPUCLK_RATE(816000000, 1, 3, 1),
197 RV1106_CPUCLK_RATE(696000000, 1, 3, 0),
198 RV1106_CPUCLK_RATE(600000000, 1, 3, 0),
199 RV1106_CPUCLK_RATE(408000000, 1, 1, 0),
200 RV1106_CPUCLK_RATE(312000000, 1, 1, 0),
201 RV1106_CPUCLK_RATE(216000000, 1, 1, 0),
202 RV1106_CPUCLK_RATE(96000000, 1, 1, 0),
203 };
204
205 static const struct rockchip_cpuclk_reg_data rv1106_cpuclk_data = {
206 .core_reg[0] = RV1106_CORECLKSEL_CON(0),
207 .div_core_shift[0] = 0,
208 .div_core_mask[0] = 0x1f,
209 .num_cores = 1,
210 .mux_core_alt = 2,
211 .mux_core_main = 2,
212 .mux_core_shift = 5,
213 .mux_core_mask = 0x3,
214 };
215
216 PNAME(mux_pll_p) = { "xin24m" };
217 PNAME(mux_24m_32k_p) = { "xin24m", "clk_rtc_32k" };
218 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
219 PNAME(mux_gpll_24m_p) = { "gpll", "xin24m" };
220 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
221 PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
222 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
223 PNAME(mux_400m_300m_pvtpll0_pvtpll1_p) = { "clk_400m_src", "clk_300m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
224 PNAME(mux_500m_300m_pvtpll0_pvtpll1_p) = { "clk_500m_src", "clk_300m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
225 PNAME(mux_339m_200m_pvtpll0_pvtpll1_p) = { "clk_339m_src", "clk_200m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
226 PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
227 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
228 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
229 PNAME(mux_500m_300m_200m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_200m_src", "xin24m" };
230 PNAME(mux_50m_24m_p) = { "clk_50m_src", "xin24m" };
231 PNAME(mux_400m_24m_p) = { "clk_400m_src", "xin24m" };
232 PNAME(clk_rtc32k_pmu_p) = { "clk_rtc32k_frac", "xin32k", "clk_pvtm_32k" };
233 PNAME(mux_200m_100m_24m_32k_p) = { "clk_200m_src", "clk_100m_src", "xin24m", "clk_rtc_32k" };
234 PNAME(mux_100m_pmu_24m_p) = { "clk_100m_pmu", "xin24m" };
235 PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_pmu", "xin24m" };
236 PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", "clk_100m_pmu", "xin24m" };
237 PNAME(mux_dpll_300m_p) = { "dpll", "clk_300m_src" };
238 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
239 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
240 PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin_osc0_half" };
241 PNAME(clk_ref_mipi0_p) = { "clk_ref_mipi0_src", "clk_ref_mipi0_frac", "xin24m" };
242 PNAME(clk_ref_mipi1_p) = { "clk_ref_mipi1_src", "clk_ref_mipi1_frac", "xin24m" };
243 PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
244 PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
245 PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
246 PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
247 PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
248 PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
249 PNAME(clk_vicap_m0_p) = { "clk_vicap_m0_src", "clk_vicap_m0_frac", "xin24m" };
250 PNAME(clk_vicap_m1_p) = { "clk_vicap_m1_src", "clk_vicap_m1_frac", "xin24m" };
251
252 static struct rockchip_pll_clock rv1106_pll_clks[] __initdata = {
253 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
254 CLK_IGNORE_UNUSED, RV1106_PLL_CON(0),
255 RV1106_MODE_CON, 0, 10, 0, rv1106_pll_rates),
256 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
257 0, RV1106_PLL_CON(8),
258 RV1106_MODE_CON, 2, 10, 0, rv1106_pll_rates),
259 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
260 CLK_IGNORE_UNUSED, RV1106_PLL_CON(16),
261 RV1106_SUBDDRMODE_CON, 0, 10, 0, NULL),
262 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
263 0, RV1106_PLL_CON(24),
264 RV1106_MODE_CON, 4, 10, 0, rv1106_pll_rates),
265 };
266
267 #define MFLAGS CLK_MUX_HIWORD_MASK
268 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
269 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
270
271 static struct rockchip_clk_branch rv1106_rtc32k_pmu_fracmux __initdata =
272 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
273 RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS);
274
275 static struct rockchip_clk_branch rv1106_i2s0_8ch_tx_fracmux __initdata =
276 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
277 RV1106_CLKSEL_CON(19), 0, 2, MFLAGS);
278
279 static struct rockchip_clk_branch rv1106_i2s0_8ch_rx_fracmux __initdata =
280 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
281 RV1106_CLKSEL_CON(21), 0, 2, MFLAGS);
282
283 static struct rockchip_clk_branch rv1106_clk_ref_mipi0_fracmux __initdata =
284 MUX(CLK_REF_MIPI0, "clk_ref_mipi0", clk_ref_mipi0_p, CLK_SET_RATE_PARENT,
285 RV1106_CLKSEL_CON(27), 0, 2, MFLAGS);
286
287 static struct rockchip_clk_branch rv1106_clk_ref_mipi1_fracmux __initdata =
288 MUX(CLK_REF_MIPI1, "clk_ref_mipi1", clk_ref_mipi1_p, CLK_SET_RATE_PARENT,
289 RV1106_CLKSEL_CON(29), 0, 2, MFLAGS);
290
291 static struct rockchip_clk_branch rv1106_clk_uart0_fracmux __initdata =
292 MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT,
293 RV1106_CLKSEL_CON(7), 0, 2, MFLAGS);
294
295 static struct rockchip_clk_branch rv1106_clk_uart1_fracmux __initdata =
296 MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
297 RV1106_CLKSEL_CON(9), 0, 2, MFLAGS);
298
299 static struct rockchip_clk_branch rv1106_clk_uart2_fracmux __initdata =
300 MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
301 RV1106_CLKSEL_CON(11), 0, 2, MFLAGS);
302
303 static struct rockchip_clk_branch rv1106_clk_uart3_fracmux __initdata =
304 MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
305 RV1106_CLKSEL_CON(13), 0, 2, MFLAGS);
306
307 static struct rockchip_clk_branch rv1106_clk_uart4_fracmux __initdata =
308 MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
309 RV1106_CLKSEL_CON(15), 0, 2, MFLAGS);
310
311 static struct rockchip_clk_branch rv1106_clk_uart5_fracmux __initdata =
312 MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
313 RV1106_CLKSEL_CON(17), 0, 2, MFLAGS);
314
315 static struct rockchip_clk_branch rv1106_clk_vicap_m0_fracmux __initdata =
316 MUX(CLK_VICAP_M0, "clk_vicap_m0", clk_vicap_m0_p, CLK_SET_RATE_PARENT,
317 RV1106_CLKSEL_CON(31), 0, 2, MFLAGS);
318
319 static struct rockchip_clk_branch rv1106_clk_vicap_m1_fracmux __initdata =
320 MUX(CLK_VICAP_M1, "clk_vicap_m1", clk_vicap_m1_p, CLK_SET_RATE_PARENT,
321 RV1106_CLKSEL_CON(33), 0, 2, MFLAGS);
322
323 static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
324
325 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
326
327 /* PD_CORE */
328 GATE(CLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
329 RV1106_CORECLKGATE_CON(0), 14, GFLAGS),
330 GATE(CLK_CORE_MCU_RTC, "clk_core_mcu_rtc", "xin24m", 0,
331 RV1106_CORECLKGATE_CON(1), 6, GFLAGS),
332 COMPOSITE(HCLK_CPU, "hclk_cpu", mux_gpll_24m_p, CLK_IS_CRITICAL,
333 RV1106_CORECLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
334 RV1106_CORECLKGATE_CON(0), 12, GFLAGS),
335 COMPOSITE(CLK_CORE_MCU, "clk_core_mcu", mux_gpll_24m_p, 0,
336 RV1106_CORECLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
337 RV1106_CORECLKGATE_CON(1), 1, GFLAGS),
338 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
339 RV1106_CORECLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
340 RV1106_CORECLKGATE_CON(0), 6, GFLAGS),
341 GATE(0, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
342 RV1106_CORECLKGATE_CON(0), 10, GFLAGS),
343 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_cpu_root", 0,
344 RV1106_CORECLKGATE_CON(1), 8, GFLAGS),
345
346 /* PD _TOP */
347 COMPOSITE(CLK_50M_SRC, "clk_50m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
348 RV1106_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
349 RV1106_CLKGATE_CON(0), 1, GFLAGS),
350 COMPOSITE(CLK_100M_SRC, "clk_100m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
351 RV1106_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
352 RV1106_CLKGATE_CON(0), 2, GFLAGS),
353 COMPOSITE(CLK_150M_SRC, "clk_150m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
354 RV1106_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
355 RV1106_CLKGATE_CON(0), 3, GFLAGS),
356 COMPOSITE(CLK_200M_SRC, "clk_200m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
357 RV1106_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
358 RV1106_CLKGATE_CON(0), 4, GFLAGS),
359 COMPOSITE(CLK_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
360 RV1106_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
361 RV1106_CLKGATE_CON(0), 5, GFLAGS),
362 COMPOSITE(CLK_300M_SRC, "clk_300m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
363 RV1106_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
364 RV1106_CLKGATE_CON(0), 6, GFLAGS),
365 COMPOSITE_HALFDIV(CLK_339M_SRC, "clk_339m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
366 RV1106_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
367 RV1106_CLKGATE_CON(0), 7, GFLAGS),
368 COMPOSITE(CLK_400M_SRC, "clk_400m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
369 RV1106_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
370 RV1106_CLKGATE_CON(0), 8, GFLAGS),
371 COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
372 RV1106_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
373 RV1106_CLKGATE_CON(0), 9, GFLAGS),
374 COMPOSITE(CLK_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
375 RV1106_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
376 RV1106_CLKGATE_CON(0), 10, GFLAGS),
377
378 COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
379 RV1106_CLKSEL_CON(24), 5, 2, MFLAGS,
380 RV1106_CLKGATE_CON(2), 9, GFLAGS),
381
382 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_gpll_cpll_p, 0,
383 RV1106_CLKSEL_CON(17), 7, 1, MFLAGS, 2, 5, DFLAGS,
384 RV1106_CLKGATE_CON(1), 13, GFLAGS),
385 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
386 RV1106_CLKSEL_CON(18), 0,
387 RV1106_CLKGATE_CON(1), 14, GFLAGS,
388 &rv1106_i2s0_8ch_tx_fracmux),
389 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
390 RV1106_CLKGATE_CON(1), 15, GFLAGS),
391 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_gpll_cpll_p, 0,
392 RV1106_CLKSEL_CON(19), 7, 1, MFLAGS, 2, 5, DFLAGS,
393 RV1106_CLKGATE_CON(2), 0, GFLAGS),
394 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
395 RV1106_CLKSEL_CON(20), 0,
396 RV1106_CLKGATE_CON(2), 1, GFLAGS,
397 &rv1106_i2s0_8ch_rx_fracmux),
398 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
399 RV1106_CLKGATE_CON(2), 2, GFLAGS),
400 MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
401 RV1106_CLKSEL_CON(21), 2, 2, MFLAGS),
402 COMPOSITE(CLK_REF_MIPI0_SRC, "clk_ref_mipi0_src", mux_gpll_cpll_p, 0,
403 RV1106_CLKSEL_CON(25), 7, 1, MFLAGS, 2, 5, DFLAGS,
404 RV1106_CLKGATE_CON(3), 4, GFLAGS),
405 COMPOSITE_FRACMUX(CLK_REF_MIPI0_FRAC, "clk_ref_mipi0_frac", "clk_ref_mipi0_src", CLK_SET_RATE_PARENT,
406 RV1106_CLKSEL_CON(26), 0,
407 RV1106_CLKGATE_CON(3), 5, GFLAGS,
408 &rv1106_clk_ref_mipi0_fracmux),
409 GATE(MCLK_REF_MIPI0, "mclk_ref_mipi0", "clk_ref_mipi0", 0,
410 RV1106_CLKGATE_CON(3), 6, GFLAGS),
411 COMPOSITE(CLK_REF_MIPI1_SRC, "clk_ref_mipi1_src", mux_gpll_cpll_p, 0,
412 RV1106_CLKSEL_CON(27), 7, 1, MFLAGS, 2, 5, DFLAGS,
413 RV1106_CLKGATE_CON(3), 7, GFLAGS),
414 COMPOSITE_FRACMUX(CLK_REF_MIPI1_FRAC, "clk_ref_mipi1_frac", "clk_ref_mipi1_src", CLK_SET_RATE_PARENT,
415 RV1106_CLKSEL_CON(28), 0,
416 RV1106_CLKGATE_CON(3), 8, GFLAGS,
417 &rv1106_clk_ref_mipi1_fracmux),
418 GATE(MCLK_REF_MIPI1, "mclk_ref_mipi1", "clk_ref_mipi1", 0,
419 RV1106_CLKGATE_CON(3), 9, GFLAGS),
420 COMPOSITE(CLK_UART0_SRC, "clk_uart0_src", mux_gpll_cpll_p, 0,
421 RV1106_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
422 RV1106_CLKGATE_CON(0), 11, GFLAGS),
423 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
424 RV1106_CLKSEL_CON(6), CLK_FRAC_DIVIDER_NO_LIMIT,
425 RV1106_CLKGATE_CON(0), 12, GFLAGS,
426 &rv1106_clk_uart0_fracmux),
427 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
428 RV1106_CLKGATE_CON(0), 13, GFLAGS),
429 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", mux_gpll_cpll_p, 0,
430 RV1106_CLKSEL_CON(7), 7, 1, MFLAGS, 2, 5, DFLAGS,
431 RV1106_CLKGATE_CON(0), 14, GFLAGS),
432 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
433 RV1106_CLKSEL_CON(8), CLK_FRAC_DIVIDER_NO_LIMIT,
434 RV1106_CLKGATE_CON(0), 15, GFLAGS,
435 &rv1106_clk_uart1_fracmux),
436 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
437 RV1106_CLKGATE_CON(1), 0, GFLAGS),
438 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", mux_gpll_cpll_p, 0,
439 RV1106_CLKSEL_CON(9), 7, 1, MFLAGS, 2, 5, DFLAGS,
440 RV1106_CLKGATE_CON(1), 1, GFLAGS),
441 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
442 RV1106_CLKSEL_CON(10), CLK_FRAC_DIVIDER_NO_LIMIT,
443 RV1106_CLKGATE_CON(1), 2, GFLAGS,
444 &rv1106_clk_uart2_fracmux),
445 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
446 RV1106_CLKGATE_CON(1), 3, GFLAGS),
447 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", mux_gpll_cpll_p, 0,
448 RV1106_CLKSEL_CON(11), 7, 1, MFLAGS, 2, 5, DFLAGS,
449 RV1106_CLKGATE_CON(1), 4, GFLAGS),
450 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
451 RV1106_CLKSEL_CON(12), CLK_FRAC_DIVIDER_NO_LIMIT,
452 RV1106_CLKGATE_CON(1), 5, GFLAGS,
453 &rv1106_clk_uart3_fracmux),
454 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
455 RV1106_CLKGATE_CON(1), 6, GFLAGS),
456 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", mux_gpll_cpll_p, 0,
457 RV1106_CLKSEL_CON(13), 7, 1, MFLAGS, 2, 5, DFLAGS,
458 RV1106_CLKGATE_CON(1), 7, GFLAGS),
459 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
460 RV1106_CLKSEL_CON(14), CLK_FRAC_DIVIDER_NO_LIMIT,
461 RV1106_CLKGATE_CON(1), 8, GFLAGS,
462 &rv1106_clk_uart4_fracmux),
463 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
464 RV1106_CLKGATE_CON(1), 9, GFLAGS),
465 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", mux_gpll_cpll_p, 0,
466 RV1106_CLKSEL_CON(15), 7, 1, MFLAGS, 2, 5, DFLAGS,
467 RV1106_CLKGATE_CON(1), 10, GFLAGS),
468 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
469 RV1106_CLKSEL_CON(16), CLK_FRAC_DIVIDER_NO_LIMIT,
470 RV1106_CLKGATE_CON(1), 11, GFLAGS,
471 &rv1106_clk_uart5_fracmux),
472 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
473 RV1106_CLKGATE_CON(1), 12, GFLAGS),
474 COMPOSITE(CLK_VICAP_M0_SRC, "clk_vicap_m0_src", mux_gpll_cpll_p, 0,
475 RV1106_CLKSEL_CON(29), 7, 1, MFLAGS, 2, 5, DFLAGS,
476 RV1106_CLKGATE_CON(3), 10, GFLAGS),
477 COMPOSITE_FRACMUX(CLK_VICAP_M0_FRAC, "clk_vicap_m0_frac", "clk_vicap_m0_src", CLK_SET_RATE_PARENT,
478 RV1106_CLKSEL_CON(30), 0,
479 RV1106_CLKGATE_CON(3), 11, GFLAGS,
480 &rv1106_clk_vicap_m0_fracmux),
481 GATE(SCLK_VICAP_M0, "sclk_vicap_m0", "clk_vicap_m0", 0,
482 RV1106_CLKGATE_CON(3), 12, GFLAGS),
483 COMPOSITE(CLK_VICAP_M1_SRC, "clk_vicap_m1_src", mux_gpll_cpll_p, 0,
484 RV1106_CLKSEL_CON(31), 7, 1, MFLAGS, 2, 5, DFLAGS,
485 RV1106_CLKGATE_CON(3), 13, GFLAGS),
486 COMPOSITE_FRACMUX(CLK_VICAP_M1_FRAC, "clk_vicap_m1_frac", "clk_vicap_m1_src", 0,
487 RV1106_CLKSEL_CON(32), 0,
488 RV1106_CLKGATE_CON(3), 14, GFLAGS,
489 &rv1106_clk_vicap_m1_fracmux),
490 GATE(SCLK_VICAP_M1, "sclk_vicap_m1", "clk_vicap_m1", 0,
491 RV1106_CLKGATE_CON(3), 15, GFLAGS),
492 COMPOSITE(DCLK_VOP_SRC, "dclk_vop_src", mux_gpll_cpll_p, 0,
493 RV1106_CLKSEL_CON(23), 8, 1, MFLAGS, 3, 5, DFLAGS,
494 RV1106_CLKGATE_CON(2), 6, GFLAGS),
495
496 /* PD_DDR */
497 COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
498 RV1106_DDRCLKSEL_CON(0), 0, 2, MFLAGS,
499 RV1106_DDRCLKGATE_CON(0), 0, GFLAGS),
500 COMPOSITE_NODIV(ACLK_DDR_ROOT, "aclk_ddr_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
501 RV1106_DDRCLKSEL_CON(0), 8, 2, MFLAGS,
502 RV1106_DDRCLKGATE_CON(0), 12, GFLAGS),
503 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IGNORE_UNUSED,
504 RV1106_DDRCLKGATE_CON(1), 3, GFLAGS),
505 GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
506 RV1106_DDRCLKGATE_CON(1), 2, GFLAGS),
507 GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", 0,
508 RV1106_DDRCLKGATE_CON(0), 7, GFLAGS),
509 GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
510 RV1106_DDRCLKGATE_CON(0), 8, GFLAGS),
511 GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IGNORE_UNUSED,
512 RV1106_DDRCLKGATE_CON(0), 5, GFLAGS),
513 GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL,
514 RV1106_DDRCLKGATE_CON(0), 11, GFLAGS),
515 GATE(ACLK_SYS_SHRM, "aclk_sys_shrm", "aclk_ddr_root", CLK_IS_CRITICAL,
516 RV1106_DDRCLKGATE_CON(0), 13, GFLAGS),
517
518 /* PD_NPU */
519 COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
520 RV1106_NPUCLKSEL_CON(0), 0, 2, MFLAGS,
521 RV1106_NPUCLKGATE_CON(0), 0, GFLAGS),
522 COMPOSITE_NODIV(ACLK_NPU_ROOT, "aclk_npu_root", mux_500m_300m_pvtpll0_pvtpll1_p, CLK_IS_CRITICAL,
523 RV1106_NPUCLKSEL_CON(0), 2, 2, MFLAGS,
524 RV1106_NPUCLKGATE_CON(0), 1, GFLAGS),
525 COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
526 RV1106_NPUCLKSEL_CON(0), 4, 2, MFLAGS,
527 RV1106_NPUCLKGATE_CON(0), 2, GFLAGS),
528 GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_root", 0,
529 RV1106_NPUCLKGATE_CON(0), 9, GFLAGS),
530 GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_root", 0,
531 RV1106_NPUCLKGATE_CON(0), 10, GFLAGS),
532
533 /* PD_PERI */
534 COMPOSITE_NODIV(PCLK_PERI_ROOT, "pclk_peri_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
535 RV1106_PERICLKSEL_CON(1), 0, 2, MFLAGS,
536 RV1106_PERICLKGATE_CON(0), 0, GFLAGS),
537 COMPOSITE_NODIV(ACLK_PERI_ROOT, "aclk_peri_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
538 RV1106_PERICLKSEL_CON(1), 2, 2, MFLAGS,
539 RV1106_PERICLKGATE_CON(0), 1, GFLAGS),
540 COMPOSITE_NODIV(HCLK_PERI_ROOT, "hclk_peri_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
541 RV1106_PERICLKSEL_CON(1), 4, 2, MFLAGS,
542 RV1106_PERICLKGATE_CON(0), 2, GFLAGS),
543 COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
544 RV1106_PERICLKSEL_CON(9), 0, 2, MFLAGS,
545 RV1106_PERICLKGATE_CON(6), 8, GFLAGS),
546 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_peri_root", 0,
547 RV1106_PERICLKGATE_CON(6), 3, GFLAGS),
548 COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s0_8ch_tx", 0,
549 RV1106_PERICLKSEL_CON(8), 0, 8, DFLAGS,
550 RV1106_PERICLKGATE_CON(6), 4, GFLAGS),
551 COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_300m_200m_100m_24m_p, 0,
552 RV1106_PERICLKSEL_CON(6), 5, 2, MFLAGS,
553 RV1106_PERICLKGATE_CON(3), 11, GFLAGS),
554 COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_24m_p, 0,
555 RV1106_PERICLKSEL_CON(6), 7, 2, MFLAGS,
556 RV1106_PERICLKGATE_CON(3), 12, GFLAGS),
557 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus_root", 0,
558 RV1106_PERICLKGATE_CON(3), 13, GFLAGS),
559 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_peri_root", 0,
560 RV1106_PERICLKGATE_CON(3), 14, GFLAGS),
561 GATE(ACLK_DECOM, "aclk_decom", "aclk_peri_root", 0,
562 RV1106_PERICLKGATE_CON(5), 9, GFLAGS),
563 GATE(PCLK_DECOM, "pclk_decom", "pclk_peri_root", 0,
564 RV1106_PERICLKGATE_CON(5), 10, GFLAGS),
565 COMPOSITE_NODIV(DCLK_DECOM, "dclk_decom", mux_400m_200m_100m_24m_p, 0,
566 RV1106_PERICLKSEL_CON(7), 14, 2, MFLAGS,
567 RV1106_PERICLKGATE_CON(5), 11, GFLAGS),
568 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
569 RV1106_PERICLKGATE_CON(5), 8, GFLAGS),
570 GATE(PCLK_DSM, "pclk_dsm", "pclk_peri_root", 0,
571 RV1106_PERICLKGATE_CON(6), 2, GFLAGS),
572 GATE(MCLK_DSM, "mclk_dsm", "mclk_i2s0_8ch_tx", 0,
573 RV1106_PERICLKGATE_CON(6), 1, GFLAGS),
574 COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_400m_24m_p, 0,
575 RV1106_PERICLKSEL_CON(7), 6, 1, MFLAGS, 0, 6, DFLAGS,
576 RV1106_PERICLKGATE_CON(4), 12, GFLAGS),
577 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri_root", 0,
578 RV1106_PERICLKGATE_CON(4), 13, GFLAGS),
579 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri_root", 0,
580 RV1106_PERICLKGATE_CON(2), 0, GFLAGS),
581 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
582 RV1106_PERICLKGATE_CON(2), 1, GFLAGS),
583 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri_root", 0,
584 RV1106_PERICLKGATE_CON(1), 6, GFLAGS),
585 COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
586 RV1106_PERICLKSEL_CON(1), 8, 2, MFLAGS,
587 RV1106_PERICLKGATE_CON(1), 7, GFLAGS),
588 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri_root", 0,
589 RV1106_PERICLKGATE_CON(1), 10, GFLAGS),
590 COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0,
591 RV1106_PERICLKSEL_CON(1), 12, 2, MFLAGS,
592 RV1106_PERICLKGATE_CON(1), 11, GFLAGS),
593 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri_root", 0,
594 RV1106_PERICLKGATE_CON(1), 12, GFLAGS),
595 COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,
596 RV1106_PERICLKSEL_CON(1), 14, 2, MFLAGS,
597 RV1106_PERICLKGATE_CON(1), 13, GFLAGS),
598 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri_root", 0,
599 RV1106_PERICLKGATE_CON(1), 14, GFLAGS),
600 COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,
601 RV1106_PERICLKSEL_CON(2), 0, 2, MFLAGS,
602 RV1106_PERICLKGATE_CON(1), 15, GFLAGS),
603 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_peri_root", 0,
604 RV1106_PERICLKGATE_CON(6), 0, GFLAGS),
605 GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_peri_root", CLK_IGNORE_UNUSED,
606 RV1106_PERICLKGATE_CON(6), 7, GFLAGS),
607 GATE(HCLK_IVE, "hclk_ive", "hclk_peri_root", 0,
608 RV1106_PERICLKGATE_CON(6), 9, GFLAGS),
609 GATE(ACLK_IVE, "aclk_ive", "aclk_peri_root", 0,
610 RV1106_PERICLKGATE_CON(6), 10, GFLAGS),
611 GATE(PCLK_PWM0_PERI, "pclk_pwm0_peri", "pclk_peri_root", 0,
612 RV1106_PERICLKGATE_CON(7), 3, GFLAGS),
613 COMPOSITE_NODIV(CLK_PWM0_PERI, "clk_pwm0_peri", mux_100m_50m_24m_p, 0,
614 RV1106_PERICLKSEL_CON(11), 0, 2, MFLAGS,
615 RV1106_PERICLKGATE_CON(7), 4, GFLAGS),
616 GATE(CLK_CAPTURE_PWM0_PERI, "clk_capture_pwm0_peri", "xin24m", 0,
617 RV1106_PERICLKGATE_CON(7), 5, GFLAGS),
618 GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
619 RV1106_PERICLKGATE_CON(0), 3, GFLAGS),
620 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri_root", 0,
621 RV1106_PERICLKGATE_CON(4), 14, GFLAGS),
622 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_500m_300m_200m_24m_p, 0,
623 RV1106_PERICLKSEL_CON(7), 12, 2, MFLAGS, 7, 5, DFLAGS,
624 RV1106_PERICLKGATE_CON(5), 0, GFLAGS),
625 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri_root", 0,
626 RV1106_PERICLKGATE_CON(6), 11, GFLAGS),
627 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri_root", 0,
628 RV1106_PERICLKGATE_CON(6), 15, GFLAGS),
629 GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri_root", 0,
630 RV1106_PERICLKGATE_CON(3), 15, GFLAGS),
631 COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_24m_p, 0,
632 RV1106_PERICLKSEL_CON(6), 9, 2, MFLAGS,
633 RV1106_PERICLKGATE_CON(4), 0, GFLAGS),
634 GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
635 RV1106_PERICLKGATE_CON(4), 1, GFLAGS),
636 GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri_root", 0,
637 RV1106_PERICLKGATE_CON(4), 2, GFLAGS),
638 COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_24m_p, 0,
639 RV1106_PERICLKSEL_CON(6), 11, 2, MFLAGS,
640 RV1106_PERICLKGATE_CON(4), 3, GFLAGS),
641 GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
642 RV1106_PERICLKGATE_CON(4), 4, GFLAGS),
643 GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri_root", 0,
644 RV1106_PERICLKGATE_CON(0), 7, GFLAGS),
645 GATE(HCLK_SAI, "hclk_sai", "hclk_peri_root", 0,
646 RV1106_PERICLKGATE_CON(5), 13, GFLAGS),
647 GATE(MCLK_SAI, "mclk_sai", "mclk_i2s0_8ch_tx", 0,
648 RV1106_PERICLKGATE_CON(5), 14, GFLAGS),
649 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri_root", 0,
650 RV1106_PERICLKGATE_CON(3), 3, GFLAGS),
651 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
652 RV1106_PERICLKSEL_CON(6), 0, 3, DFLAGS,
653 RV1106_PERICLKGATE_CON(3), 4, GFLAGS),
654 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri_root", 0,
655 RV1106_PERICLKGATE_CON(3), 6, GFLAGS),
656 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
657 RV1106_PERICLKSEL_CON(6), 3, 2, MFLAGS,
658 RV1106_PERICLKGATE_CON(3), 7, GFLAGS),
659 GATE(PCLK_STIMER, "pclk_stimer", "pclk_peri_root", 0,
660 RV1106_PERICLKGATE_CON(0), 15, GFLAGS),
661 GATE(CLK_STIMER0, "clk_stimer0", "clk_timer_root", 0,
662 RV1106_PERICLKGATE_CON(1), 0, GFLAGS),
663 GATE(CLK_STIMER1, "clk_stimer1", "clk_timer_root", 0,
664 RV1106_PERICLKGATE_CON(1), 1, GFLAGS),
665 GATE(PCLK_TIMER, "pclk_timer", "pclk_peri_root", 0,
666 RV1106_PERICLKGATE_CON(0), 8, GFLAGS),
667 GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
668 RV1106_PERICLKGATE_CON(0), 9, GFLAGS),
669 GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
670 RV1106_PERICLKGATE_CON(0), 10, GFLAGS),
671 GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
672 RV1106_PERICLKGATE_CON(0), 11, GFLAGS),
673 GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
674 RV1106_PERICLKGATE_CON(0), 12, GFLAGS),
675 GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
676 RV1106_PERICLKGATE_CON(0), 13, GFLAGS),
677 GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
678 RV1106_PERICLKGATE_CON(0), 14, GFLAGS),
679 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_peri_root", 0,
680 RV1106_PERICLKGATE_CON(3), 9, GFLAGS),
681 GATE(HCLK_TRNG_S, "hclk_trng_s", "hclk_peri_root", 0,
682 RV1106_PERICLKGATE_CON(3), 10, GFLAGS),
683 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri_root", 0,
684 RV1106_PERICLKGATE_CON(2), 3, GFLAGS),
685 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri_root", 0,
686 RV1106_PERICLKGATE_CON(2), 7, GFLAGS),
687 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri_root", 0,
688 RV1106_PERICLKGATE_CON(2), 11, GFLAGS),
689 GATE(PCLK_UART5, "pclk_uart5", "pclk_peri_root", 0,
690 RV1106_PERICLKGATE_CON(2), 15, GFLAGS),
691 GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_bus_root", 0,
692 RV1106_PERICLKGATE_CON(4), 7, GFLAGS),
693 GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
694 RV1106_PERICLKGATE_CON(4), 8, GFLAGS),
695 GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_peri_root", 0,
696 RV1106_PERICLKGATE_CON(5), 1, GFLAGS),
697 GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
698 RV1106_PERICLKGATE_CON(5), 2, GFLAGS),
699 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_peri_root", 0,
700 RV1106_PERICLKGATE_CON(1), 2, GFLAGS),
701 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
702 RV1106_PERICLKGATE_CON(1), 3, GFLAGS),
703 GATE(PCLK_WDT_S, "pclk_wdt_s", "pclk_peri_root", 0,
704 RV1106_PERICLKGATE_CON(1), 4, GFLAGS),
705 GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
706 RV1106_PERICLKGATE_CON(1), 5, GFLAGS),
707
708 /* PD_PMU */
709 COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
710 RV1106_PMUCLKSEL_CON(6), 0,
711 RV1106_PMUCLKGATE_CON(1), 14, GFLAGS,
712 &rv1106_rtc32k_pmu_fracmux),
713 DIV(CLK_100M_PMU, "clk_100m_pmu", "clk_200m_src", 0,
714 RV1106_PMUCLKSEL_CON(0), 0, 3, DFLAGS),
715 COMPOSITE_NODIV(PCLK_PMU_ROOT, "pclk_pmu_root", mux_100m_pmu_24m_p, CLK_IS_CRITICAL,
716 RV1106_PMUCLKSEL_CON(0), 3, 1, MFLAGS,
717 RV1106_PMUCLKGATE_CON(0), 1, GFLAGS),
718 COMPOSITE_NODIV(HCLK_PMU_ROOT, "hclk_pmu_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
719 RV1106_PMUCLKSEL_CON(0), 4, 2, MFLAGS,
720 RV1106_PMUCLKGATE_CON(0), 2, GFLAGS),
721 GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL,
722 RV1106_PMUCLKGATE_CON(1), 0, GFLAGS),
723 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
724 RV1106_PMUCLKGATE_CON(1), 1, GFLAGS),
725 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu", 0,
726 RV1106_PMUCLKGATE_CON(1), 15, GFLAGS),
727 GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "pclk_pmu_root", 0,
728 RV1106_PMUCLKGATE_CON(1), 2, GFLAGS),
729 COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", mux_24m_32k_p, 0,
730 RV1106_PMUCLKSEL_CON(0), 15, 1, MFLAGS,
731 RV1106_PMUCLKGATE_CON(1), 3, GFLAGS),
732 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pmu_root", 0,
733 RV1106_PMUCLKGATE_CON(0), 3, GFLAGS),
734 COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_24m_32k_p, 0,
735 RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS,
736 RV1106_PMUCLKGATE_CON(0), 4, GFLAGS),
737 GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
738 RV1106_PMUCLKGATE_CON(2), 10, GFLAGS),
739 GATE(CLK_PMU_MCU, "clk_pmu_mcu", "hclk_pmu_root", 0,
740 RV1106_PMUCLKGATE_CON(0), 9, GFLAGS),
741 GATE(CLK_PMU_MCU_RTC, "clk_pmu_mcu_rtc", "xin24m", 0,
742 RV1106_PMUCLKGATE_CON(0), 13, GFLAGS),
743 COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
744 RV1106_PMUCLKSEL_CON(1), 0, 5, DFLAGS,
745 RV1106_PMUCLKGATE_CON(1), 4, GFLAGS),
746 GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
747 RV1106_PMUCLKGATE_CON(1), 5, GFLAGS),
748 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
749 RV1106_PMUCLKGATE_CON(2), 13, GFLAGS),
750 GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IGNORE_UNUSED,
751 RV1106_PMUCLKGATE_CON(0), 8, GFLAGS),
752 GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
753 RV1106_PMUCLKGATE_CON(2), 8, GFLAGS),
754 COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0,
755 RV1106_PMUCLKSEL_CON(7), 2, 1, MFLAGS,
756 RV1106_PMUCLKGATE_CON(2), 9, GFLAGS),
757
758 /* PD_SUBDDR */
759 COMPOSITE(CLK_CORE_DDRC_SRC, "clk_core_ddrc_src", mux_dpll_300m_p, CLK_IGNORE_UNUSED,
760 RV1106_SUBDDRCLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
761 RV1106_SUBDDRCLKGATE_CON(0), 2, GFLAGS),
762 GATE(CLK_DFICTRL, "clk_dfictrl", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
763 RV1106_SUBDDRCLKGATE_CON(0), 5, GFLAGS),
764 GATE(CLK_DDRMON, "clk_ddrmon", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
765 RV1106_SUBDDRCLKGATE_CON(0), 4, GFLAGS),
766 GATE(CLK_DDR_PHY, "clk_ddr_phy", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
767 RV1106_SUBDDRCLKGATE_CON(0), 6, GFLAGS),
768 GATE(ACLK_DDRC, "aclk_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
769 RV1106_SUBDDRCLKGATE_CON(0), 1, GFLAGS),
770 GATE(CLK_CORE_DDRC, "clk_core_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
771 RV1106_SUBDDRCLKGATE_CON(0), 3, GFLAGS),
772
773
774 /* PD_VEPU */
775 COMPOSITE_NODIV(HCLK_VEPU_ROOT, "hclk_vepu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
776 RV1106_VEPUCLKSEL_CON(0), 0, 2, MFLAGS,
777 RV1106_VEPUCLKGATE_CON(0), 0, GFLAGS),
778 COMPOSITE_NODIV(ACLK_VEPU_COM_ROOT, "aclk_vepu_com_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
779 RV1106_VEPUCLKSEL_CON(0), 2, 2, MFLAGS,
780 RV1106_VEPUCLKGATE_CON(0), 1, GFLAGS),
781 COMPOSITE_NODIV(ACLK_VEPU_ROOT, "aclk_vepu_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
782 RV1106_VEPUCLKSEL_CON(0), 4, 2, MFLAGS,
783 RV1106_VEPUCLKGATE_CON(0), 2, GFLAGS),
784 COMPOSITE_NODIV(PCLK_VEPU_ROOT, "pclk_vepu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
785 RV1106_VEPUCLKSEL_CON(0), 6, 2, MFLAGS,
786 RV1106_VEPUCLKGATE_CON(0), 3, GFLAGS),
787 GATE(PCLK_SPI0, "pclk_spi0", "pclk_vepu_root", 0,
788 RV1106_VEPUCLKGATE_CON(1), 2, GFLAGS),
789 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
790 RV1106_VEPUCLKSEL_CON(0), 12, 2, MFLAGS,
791 RV1106_VEPUCLKGATE_CON(1), 3, GFLAGS),
792 GATE(CLK_UART_DETN_FLT, "clk_uart_detn_flt", "xin24m", 0,
793 RV1106_VEPUCLKGATE_CON(1), 8, GFLAGS),
794 GATE(HCLK_VEPU, "hclk_vepu", "hclk_vepu_root", 0,
795 RV1106_VEPUCLKGATE_CON(0), 8, GFLAGS),
796 GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_root", 0,
797 RV1106_VEPUCLKGATE_CON(0), 9, GFLAGS),
798 COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", mux_400m_300m_pvtpll0_pvtpll1_p, 0,
799 RV1106_VEPUCLKSEL_CON(0), 8, 2, MFLAGS,
800 RV1106_VEPUCLKGATE_CON(0), 10, GFLAGS),
801 COMPOSITE_NODIV(CLK_CORE_VEPU_DVBM, "clk_core_vepu_dvbm", mux_200m_100m_50m_24m_p, 0,
802 RV1106_VEPUCLKSEL_CON(0), 10, 2, MFLAGS,
803 RV1106_VEPUCLKGATE_CON(0), 13, GFLAGS),
804 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vepu_root", 0,
805 RV1106_VEPUCLKGATE_CON(0), 15, GFLAGS),
806 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
807 RV1106_VEPUCLKGATE_CON(1), 0, GFLAGS),
808 GATE(HCLK_VEPU_PP, "hclk_vepu_pp", "hclk_vepu_root", 0,
809 RV1106_VEPUCLKGATE_CON(0), 11, GFLAGS),
810 GATE(ACLK_VEPU_PP, "aclk_vepu_pp", "aclk_vepu_root", 0,
811 RV1106_VEPUCLKGATE_CON(0), 12, GFLAGS),
812
813 /* PD_VI */
814 COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
815 RV1106_VICLKSEL_CON(0), 0, 2, MFLAGS,
816 RV1106_VICLKGATE_CON(0), 0, GFLAGS),
817 COMPOSITE_NODIV(ACLK_VI_ROOT, "aclk_vi_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
818 RV1106_VICLKSEL_CON(0), 2, 2, MFLAGS,
819 RV1106_VICLKGATE_CON(0), 1, GFLAGS),
820 COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
821 RV1106_VICLKSEL_CON(0), 4, 2, MFLAGS,
822 RV1106_VICLKGATE_CON(0), 2, GFLAGS),
823 COMPOSITE_NODIV(PCLK_VI_RTC_ROOT, "pclk_vi_rtc_root", mux_50m_24m_p, 0,
824 RV1106_VICLKSEL_CON(0), 6, 1, MFLAGS,
825 RV1106_VICLKGATE_CON(0), 3, GFLAGS),
826
827 GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi_root", 0,
828 RV1106_VICLKGATE_CON(1), 3, GFLAGS),
829 GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi_root", 0,
830 RV1106_VICLKGATE_CON(1), 5, GFLAGS),
831 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vi_root", 0,
832 RV1106_VICLKGATE_CON(1), 15, GFLAGS),
833 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
834 RV1106_VICLKGATE_CON(2), 0, GFLAGS),
835 GATE(HCLK_ISP3P2, "hclk_isp3p2", "hclk_vi_root", 0,
836 RV1106_VICLKGATE_CON(0), 7, GFLAGS),
837 GATE(ACLK_ISP3P2, "aclk_isp3p2", "aclk_vi_root", 0,
838 RV1106_VICLKGATE_CON(0), 8, GFLAGS),
839 COMPOSITE_NODIV(CLK_CORE_ISP3P2, "clk_core_isp3p2", mux_339m_200m_pvtpll0_pvtpll1_p, 0,
840 RV1106_VICLKSEL_CON(0), 7, 2, MFLAGS,
841 RV1106_VICLKGATE_CON(0), 9, GFLAGS),
842 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_vi_root", 0,
843 RV1106_VICLKGATE_CON(1), 14, GFLAGS),
844 COMPOSITE(CCLK_SRC_SDMMC, "cclk_src_sdmmc", mux_400m_24m_p, 0,
845 RV1106_VICLKSEL_CON(1), 14, 1, MFLAGS, 8, 6, DFLAGS,
846 RV1106_VICLKGATE_CON(1), 11, GFLAGS),
847 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_vi_root", 0,
848 RV1106_VICLKGATE_CON(1), 12, GFLAGS),
849 GATE(CLK_SDMMC_DETN_FLT, "clk_sdmmc_detn_flt", "xin24m", 0,
850 RV1106_VICLKGATE_CON(1), 13, GFLAGS),
851 GATE(PCLK_VI_RTC_TEST, "pclk_vi_rtc_test", "pclk_vi_rtc_root", 0,
852 RV1106_VICLKGATE_CON(2), 5, GFLAGS),
853 GATE(PCLK_VI_RTC_PHY, "pclk_vi_rtc_phy", "pclk_vi_rtc_root", 0,
854 RV1106_VICLKGATE_CON(2), 6, GFLAGS),
855 COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", mux_339m_200m_100m_24m_p, 0,
856 RV1106_VICLKSEL_CON(0), 9, 2, MFLAGS,
857 RV1106_VICLKGATE_CON(0), 10, GFLAGS),
858 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
859 RV1106_VICLKGATE_CON(0), 12, GFLAGS),
860 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
861 RV1106_VICLKGATE_CON(0), 13, GFLAGS),
862
863 /* PD_VO */
864 COMPOSITE_NODIV(ACLK_MAC_ROOT, "aclk_mac_root", mux_300m_200m_100m_24m_p, 0,
865 RV1106_VOCLKSEL_CON(1), 12, 2, MFLAGS,
866 RV1106_VOCLKGATE_CON(1), 4, GFLAGS),
867 COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
868 RV1106_VOCLKSEL_CON(0), 0, 2, MFLAGS,
869 RV1106_VOCLKGATE_CON(0), 0, GFLAGS),
870 COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
871 RV1106_VOCLKSEL_CON(0), 2, 2, MFLAGS,
872 RV1106_VOCLKGATE_CON(0), 1, GFLAGS),
873 COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
874 RV1106_VOCLKSEL_CON(0), 4, 2, MFLAGS,
875 RV1106_VOCLKGATE_CON(0), 2, GFLAGS),
876 COMPOSITE_NODIV(ACLK_VOP_ROOT, "aclk_vop_root", mux_300m_200m_100m_24m_p, 0,
877 RV1106_VOCLKSEL_CON(1), 10, 2, MFLAGS,
878 RV1106_VOCLKGATE_CON(0), 11, GFLAGS),
879
880 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
881 RV1106_VOCLKGATE_CON(3), 0, GFLAGS),
882 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
883 RV1106_VOCLKGATE_CON(3), 1, GFLAGS),
884 GATE(ACLK_MAC, "aclk_mac", "aclk_mac_root", 0,
885 RV1106_VOCLKGATE_CON(1), 8, GFLAGS),
886 GATE(PCLK_MAC, "pclk_mac", "pclk_vo_root", 0,
887 RV1106_VOCLKGATE_CON(1), 9, GFLAGS),
888 FACTOR(CLK_GMAC0_50M_O, "clk_gmac0_50m_o", "clk_50m_src", 0, 1, 1),
889 FACTOR(CLK_GMAC0_REF_50M, "clk_gmac0_ref_50m", "clk_gmac0_50m_o", 0, 1, 1),
890 DIV(CLK_GMAC0_TX_50M_O, "clk_gmac0_tx_50m_o", "clk_gmac0_50m_o", 0,
891 RV1106_VOCLKSEL_CON(2), 1, 6, DFLAGS),
892 GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
893 RV1106_VOCLKGATE_CON(2), 13, GFLAGS),
894 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
895 RV1106_VOCLKGATE_CON(2), 11, GFLAGS),
896 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
897 RV1106_VOCLKGATE_CON(2), 3, GFLAGS),
898 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
899 RV1106_VOCLKGATE_CON(2), 5, GFLAGS),
900 COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
901 RV1106_VOCLKSEL_CON(3), 10, 3, DFLAGS,
902 RV1106_VOCLKGATE_CON(2), 6, GFLAGS),
903 GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_vo_root", 0,
904 RV1106_VOCLKGATE_CON(2), 7, GFLAGS),
905 GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", 0,
906 RV1106_VOCLKGATE_CON(2), 9, GFLAGS),
907 COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", 0,
908 RV1106_VOCLKSEL_CON(3), 13, 3, DFLAGS,
909 RV1106_VOCLKGATE_CON(2), 10, GFLAGS),
910 GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_vo_root", 0,
911 RV1106_VOCLKGATE_CON(2), 14, GFLAGS),
912 GATE(CLK_PMC_OTP, "clk_pmc_otp", "clk_sbpi_otpc_s", 0,
913 RV1106_VOCLKGATE_CON(2), 15, GFLAGS),
914 GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
915 RV1106_VOCLKGATE_CON(0), 7, GFLAGS),
916 GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
917 RV1106_VOCLKGATE_CON(0), 8, GFLAGS),
918 COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_400m_200m_100m_24m_p, 0,
919 RV1106_VOCLKSEL_CON(1), 8, 2, MFLAGS,
920 RV1106_VOCLKGATE_CON(0), 9, GFLAGS),
921 COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", mux_400m_24m_p, 0,
922 RV1106_VOCLKSEL_CON(2), 13, 1, MFLAGS, 7, 6, DFLAGS,
923 RV1106_VOCLKGATE_CON(1), 14, GFLAGS),
924 GATE(HCLK_SDIO, "hclk_sdio", "hclk_vo_root", 0,
925 RV1106_VOCLKGATE_CON(1), 15, GFLAGS),
926 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vo_root", 0,
927 RV1106_VOCLKGATE_CON(2), 0, GFLAGS),
928 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
929 RV1106_VOCLKSEL_CON(3), 0, 5, DFLAGS,
930 RV1106_VOCLKGATE_CON(2), 1, GFLAGS),
931 COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
932 RV1106_VOCLKSEL_CON(3), 5, 5, DFLAGS,
933 RV1106_VOCLKGATE_CON(2), 2, GFLAGS),
934 GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
935 RV1106_VOCLKGATE_CON(0), 13, GFLAGS),
936 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_src", 0,
937 RV1106_VOCLKGATE_CON(0), 14, GFLAGS),
938 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
939 RV1106_VOCLKGATE_CON(0), 15, GFLAGS),
940
941 /* IO CLK */
942 GATE(RX0PCLK_VICAP, "rx0pclk_vicap", "rx0pclk_vicap_io", 0,
943 RV1106_VICLKGATE_CON(1), 0, GFLAGS),
944 GATE(RX1PCLK_VICAP, "rx1pclk_vicap", "rx1pclk_vicap_io", 0,
945 RV1106_VICLKGATE_CON(1), 1, GFLAGS),
946 GATE(ISP0CLK_VICAP, "isp0clk_vicap", "isp0clk_vicap_io", 0,
947 RV1106_VICLKGATE_CON(1), 2, GFLAGS),
948 GATE(I0CLK_VICAP, "i0clk_vicap", "i0clk_vicap_io", 0,
949 RV1106_VICLKGATE_CON(0), 14, GFLAGS),
950 GATE(I1CLK_VICAP, "i1clk_vicap", "i1clk_vicap_io", 0,
951 RV1106_VICLKGATE_CON(0), 15, GFLAGS),
952 GATE(PCLK_VICAP, "pclk_vicap", "pclk_vicap_io", 0,
953 RV1106_VICLKGATE_CON(0), 11, GFLAGS),
954 GATE(CLK_RXBYTECLKHS_0, "clk_rxbyteclkhs_0", "clk_rxbyteclkhs_0_io", 0,
955 RV1106_VICLKGATE_CON(1), 4, GFLAGS),
956 GATE(CLK_RXBYTECLKHS_1, "clk_rxbyteclkhs_1", "clk_rxbyteclkhs_1_io", 0,
957 RV1106_VICLKGATE_CON(1), 6, GFLAGS),
958
959 GATE(PCLK_VICAP_VEPU, "pclk_vicap_vepu", "pclk_vicap_vepu_io", 0,
960 RV1106_VEPUCLKGATE_CON(0), 14, GFLAGS),
961 GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0,
962 RV1106_VEPUCLKGATE_CON(1), 4, GFLAGS),
963
964 GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
965 RV1106_PERICLKGATE_CON(4), 9, GFLAGS),
966
967 };
968
969 static struct rockchip_clk_branch rv1106_grf_clk_branches[] __initdata = {
970 MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_src_emmc", RV1106_EMMC_CON0, 1),
971 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_src_emmc", RV1106_EMMC_CON1, 1),
972 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc", RV1106_SDMMC_CON0, 1),
973 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc", RV1106_SDMMC_CON1, 1),
974 MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RV1106_SDIO_CON0, 1),
975 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RV1106_SDIO_CON1, 1),
976 };
977
978 static void __iomem *rv1106_cru_base;
979 static struct rockchip_clk_provider *grf_ctx, *cru_ctx;
980
rv1106_dump_cru(void)981 void rv1106_dump_cru(void)
982 {
983 if (rv1106_cru_base) {
984 pr_warn("CRU:\n");
985 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
986 32, 4, rv1106_cru_base,
987 0x588, false);
988 }
989 }
990 EXPORT_SYMBOL_GPL(rv1106_dump_cru);
991
_cru_pvtpll_calibrate(int count_offset,int length_offset,int target_rate)992 static void _cru_pvtpll_calibrate(int count_offset, int length_offset, int target_rate)
993 {
994 unsigned int rate0, rate1, delta, length_ori, length, step, val, i = 0;
995
996 rate0 = readl_relaxed(rv1106_cru_base + count_offset);
997 if (rate0 < target_rate)
998 return;
999 /* delta < (3.125% * target_rate) */
1000 if ((rate0 - target_rate) < (target_rate >> 5))
1001 return;
1002
1003 length_ori = readl_relaxed(rv1106_cru_base + length_offset) & PVTPLL_LENGTH_SEL_MASK;
1004 length = length_ori;
1005 length++;
1006 val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
1007 writel_relaxed(val, rv1106_cru_base + length_offset);
1008 usleep_range(2000, 2100);
1009 rate1 = readl_relaxed(rv1106_cru_base + count_offset);
1010 if ((rate1 < target_rate) || (rate1 >= rate0))
1011 return;
1012 if (abs(rate1 - target_rate) < (target_rate >> 5))
1013 return;
1014
1015 step = rate0 - rate1;
1016 delta = rate1 - target_rate;
1017 length += delta / step;
1018 val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
1019 writel_relaxed(val, rv1106_cru_base + length_offset);
1020 usleep_range(2000, 2100);
1021 rate0 = readl_relaxed(rv1106_cru_base + count_offset);
1022
1023 while (abs(rate0 - target_rate) >= (target_rate >> 5)) {
1024 if (i++ > 20)
1025 break;
1026 if (rate0 > target_rate)
1027 length++;
1028 else
1029 length--;
1030 if (length <= length_ori)
1031 break;
1032 val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
1033 writel_relaxed(val, rv1106_cru_base + length_offset);
1034 usleep_range(2000, 2100);
1035 rate0 = readl_relaxed(rv1106_cru_base + count_offset);
1036 }
1037 }
1038
_grf_pvtpll_calibrate(int count_offset,int length_offset,int target_rate)1039 static void _grf_pvtpll_calibrate(int count_offset, int length_offset, int target_rate)
1040 {
1041 unsigned int rate0, rate1, delta, length_ori, length, step, val, i = 0;
1042
1043 regmap_read(cru_ctx->grf, count_offset, &rate0);
1044 if (rate0 < target_rate)
1045 return;
1046 /* delta < (3.125% * target_rate) */
1047 if ((rate0 - target_rate) < (target_rate >> 5))
1048 return;
1049
1050 regmap_read(cru_ctx->grf, length_offset, &length_ori);
1051 length = length_ori;
1052 length_ori = length;
1053 length &= PVTPLL_LENGTH_SEL_MASK;
1054 length++;
1055 val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
1056 regmap_write(cru_ctx->grf, length_offset, val);
1057 usleep_range(2000, 2100);
1058 regmap_read(cru_ctx->grf, count_offset, &rate1);
1059 if ((rate1 < target_rate) || (rate1 >= rate0))
1060 return;
1061 if (abs(rate1 - target_rate) < (target_rate >> 5))
1062 return;
1063
1064 step = rate0 - rate1;
1065 delta = rate1 - target_rate;
1066 length += delta / step;
1067 val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
1068 regmap_write(cru_ctx->grf, length_offset, val);
1069 usleep_range(2000, 2100);
1070 regmap_read(cru_ctx->grf, count_offset, &rate0);
1071
1072 while (abs(rate0 - target_rate) >= (target_rate >> 5)) {
1073 if (i++ > 20)
1074 break;
1075 if (rate0 > target_rate)
1076 length++;
1077 else
1078 length--;
1079 if (length <= length_ori)
1080 break;
1081 val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
1082 regmap_write(cru_ctx->grf, length_offset, val);
1083 usleep_range(2000, 2100);
1084 regmap_read(cru_ctx->grf, count_offset, &rate0);
1085 }
1086 }
1087
rockchip_rv1106_pvtpll_calibrate(struct work_struct * w)1088 static void rockchip_rv1106_pvtpll_calibrate(struct work_struct *w)
1089 {
1090 struct clk *clk;
1091 unsigned long rate;
1092
1093 clk = __clk_lookup("clk_pvtpll_0");
1094 if (clk) {
1095 rate = clk_get_rate(clk);
1096 _cru_pvtpll_calibrate(CRU_PVTPLL0_OSC_CNT_AVG,
1097 CRU_PVTPLL0_CON0_H, rate / 1000000);
1098 }
1099
1100 clk = __clk_lookup("clk_pvtpll_1");
1101 if (clk) {
1102 rate = clk_get_rate(clk);
1103 _cru_pvtpll_calibrate(CRU_PVTPLL1_OSC_CNT_AVG,
1104 CRU_PVTPLL1_CON0_H, rate / 1000000);
1105 }
1106
1107 clk = __clk_lookup("cpu_pvtpll");
1108 if (clk) {
1109 rate = clk_get_rate(clk);
1110 _grf_pvtpll_calibrate(CPU_PVTPLL_OSC_CNT_AVG,
1111 CPU_PVTPLL_CON0_H, rate / 1000000);
1112 }
1113 }
1114 static DECLARE_DEFERRABLE_WORK(pvtpll_calibrate_work, rockchip_rv1106_pvtpll_calibrate);
1115
rockchip_rv1106_pvtpll_init(struct rockchip_clk_provider * ctx)1116 static void rockchip_rv1106_pvtpll_init(struct rockchip_clk_provider *ctx)
1117 {
1118 /* set pvtpll ref clk mux */
1119 writel_relaxed(CPU_PVTPLL_PATH_CORE, ctx->reg_base + CPU_CLK_PATH_BASE);
1120
1121 regmap_write(ctx->grf, CPU_PVTPLL_CON0_H, HIWORD_UPDATE(0x7, PVTPLL_LENGTH_SEL_MASK,
1122 PVTPLL_LENGTH_SEL_SHIFT));
1123 regmap_write(ctx->grf, CPU_PVTPLL_CON0_L, HIWORD_UPDATE(0x1, PVTPLL_RING_SEL_MASK,
1124 PVTPLL_RING_SEL_SHIFT));
1125 regmap_write(ctx->grf, CPU_PVTPLL_CON0_L, HIWORD_UPDATE(0x3, PVTPLL_EN_MASK,
1126 PVTPLL_EN_SHIFT));
1127
1128 writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL0_CON0_H);
1129 writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL0_CON1_L);
1130 writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL0_CON2_H);
1131 writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL0_CON0_L);
1132
1133 writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL1_CON0_H);
1134 writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL1_CON1_L);
1135 writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL1_CON2_H);
1136 writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL1_CON0_L);
1137
1138 schedule_delayed_work(&pvtpll_calibrate_work, msecs_to_jiffies(3000));
1139 }
1140
rv1106_clk_panic(struct notifier_block * this,unsigned long ev,void * ptr)1141 static int rv1106_clk_panic(struct notifier_block *this,
1142 unsigned long ev, void *ptr)
1143 {
1144 rv1106_dump_cru();
1145 return NOTIFY_DONE;
1146 }
1147
1148 static struct notifier_block rv1106_clk_panic_block = {
1149 .notifier_call = rv1106_clk_panic,
1150 };
1151
rv1106_clk_init(struct device_node * np)1152 static void __init rv1106_clk_init(struct device_node *np)
1153 {
1154 struct rockchip_clk_provider *ctx;
1155 void __iomem *reg_base;
1156 struct clk **cru_clks;
1157
1158 reg_base = of_iomap(np, 0);
1159 if (!reg_base) {
1160 pr_err("%s: could not map cru region\n", __func__);
1161 return;
1162 }
1163
1164 rv1106_cru_base = reg_base;
1165
1166 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1167 if (IS_ERR(ctx)) {
1168 pr_err("%s: rockchip clk init failed\n", __func__);
1169 iounmap(reg_base);
1170 return;
1171 }
1172 cru_ctx = ctx;
1173
1174 rockchip_rv1106_pvtpll_init(ctx);
1175
1176 cru_clks = ctx->clk_data.clks;
1177
1178 rockchip_clk_register_plls(ctx, rv1106_pll_clks,
1179 ARRAY_SIZE(rv1106_pll_clks),
1180 RV1106_GRF_SOC_STATUS0);
1181
1182 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1183 3, cru_clks[PLL_APLL], cru_clks[PLL_GPLL],
1184 &rv1106_cpuclk_data, rv1106_cpuclk_rates,
1185 ARRAY_SIZE(rv1106_cpuclk_rates));
1186
1187 rockchip_clk_register_branches(ctx, rv1106_clk_branches,
1188 ARRAY_SIZE(rv1106_clk_branches));
1189
1190 rockchip_clk_register_branches(grf_ctx, rv1106_grf_clk_branches,
1191 ARRAY_SIZE(rv1106_grf_clk_branches));
1192
1193 rockchip_register_softrst(np, 31745, reg_base + RV1106_PMUSOFTRST_CON(0),
1194 ROCKCHIP_SOFTRST_HIWORD_MASK);
1195
1196 rockchip_register_restart_notifier(ctx, RV1106_GLB_SRST_FST, NULL);
1197
1198 rockchip_clk_of_add_provider(np, ctx);
1199
1200 atomic_notifier_chain_register(&panic_notifier_list,
1201 &rv1106_clk_panic_block);
1202 }
1203
1204 CLK_OF_DECLARE(rv1106_cru, "rockchip,rv1106-cru", rv1106_clk_init);
1205
rv1106_grf_clk_init(struct device_node * np)1206 static void __init rv1106_grf_clk_init(struct device_node *np)
1207 {
1208 struct rockchip_clk_provider *ctx;
1209 void __iomem *reg_base;
1210
1211 reg_base = of_iomap(of_get_parent(np), 0);
1212 if (!reg_base) {
1213 pr_err("%s: could not map cru grf region\n", __func__);
1214 return;
1215 }
1216
1217 ctx = rockchip_clk_init(np, reg_base, CLK_NR_GRF_CLKS);
1218 if (IS_ERR(ctx)) {
1219 pr_err("%s: rockchip grf clk init failed\n", __func__);
1220 return;
1221 }
1222 grf_ctx = ctx;
1223
1224 rockchip_clk_of_add_provider(np, ctx);
1225 }
1226 CLK_OF_DECLARE(rv1106_grf_cru, "rockchip,rv1106-grf-cru", rv1106_grf_clk_init);
1227
1228 #ifdef MODULE
1229 struct clk_rv1106_inits {
1230 void (*inits)(struct device_node *np);
1231 };
1232
1233 static const struct clk_rv1106_inits clk_rv1106_init = {
1234 .inits = rv1106_clk_init,
1235 };
1236
1237 static const struct clk_rv1106_inits clk_rv1106_grf_init = {
1238 .inits = rv1106_grf_clk_init,
1239 };
1240
1241 static const struct of_device_id clk_rv1106_match_table[] = {
1242 {
1243 .compatible = "rockchip,rv1106-cru",
1244 .data = &clk_rv1106_init,
1245 }, {
1246 .compatible = "rockchip,rv1106-grf-cru",
1247 .data = &clk_rv1106_grf_init,
1248 },
1249 { }
1250 };
1251 MODULE_DEVICE_TABLE(of, clk_rv1106_match_table);
1252
clk_rv1106_probe(struct platform_device * pdev)1253 static int __init clk_rv1106_probe(struct platform_device *pdev)
1254 {
1255 struct device_node *np = pdev->dev.of_node;
1256 const struct of_device_id *match;
1257 const struct clk_rv1106_inits *init_data;
1258
1259 match = of_match_device(clk_rv1106_match_table, &pdev->dev);
1260 if (!match || !match->data)
1261 return -EINVAL;
1262
1263 init_data = match->data;
1264 if (init_data->inits)
1265 init_data->inits(np);
1266
1267 return 0;
1268 }
1269
1270 static struct platform_driver clk_rv1106_driver = {
1271 .driver = {
1272 .name = "clk-rv1106",
1273 .of_match_table = clk_rv1106_match_table,
1274 },
1275 };
1276 builtin_platform_driver_probe(clk_rv1106_driver, clk_rv1106_probe);
1277
1278 MODULE_DESCRIPTION("Rockchip RV1106 Clock Driver");
1279 MODULE_LICENSE("GPL");
1280 #endif /* MODULE */
1281