1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/of_address.h>
12 #include <linux/syscore_ops.h>
13 #include <dt-bindings/clock/rk3588-cru.h>
14 #include "clk.h"
15
16 #define RK3588_GRF_SOC_STATUS0 0x600
17 #define RK3588_PHYREF_ALT_GATE 0xc38
18 #define RK3588_FRAC_MAX_PRATE 1500000000
19 #define RK3588_DCLK_MAX_PRATE 594000000
20
21 enum rk3588_plls {
22 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll,
23 };
24
25 static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
26 /* _mhz, _p, _m, _s, _k */
27 RK3588_PLL_RATE(2520000000, 2, 210, 0, 0),
28 RK3588_PLL_RATE(2496000000, 2, 208, 0, 0),
29 RK3588_PLL_RATE(2472000000, 2, 206, 0, 0),
30 RK3588_PLL_RATE(2448000000, 2, 204, 0, 0),
31 RK3588_PLL_RATE(2424000000, 2, 202, 0, 0),
32 RK3588_PLL_RATE(2400000000, 2, 200, 0, 0),
33 RK3588_PLL_RATE(2376000000, 2, 198, 0, 0),
34 RK3588_PLL_RATE(2352000000, 2, 196, 0, 0),
35 RK3588_PLL_RATE(2328000000, 2, 194, 0, 0),
36 RK3588_PLL_RATE(2304000000, 2, 192, 0, 0),
37 RK3588_PLL_RATE(2280000000, 2, 190, 0, 0),
38 RK3588_PLL_RATE(2256000000, 2, 376, 1, 0),
39 RK3588_PLL_RATE(2232000000, 2, 372, 1, 0),
40 RK3588_PLL_RATE(2208000000, 2, 368, 1, 0),
41 RK3588_PLL_RATE(2184000000, 2, 364, 1, 0),
42 RK3588_PLL_RATE(2160000000, 2, 360, 1, 0),
43 RK3588_PLL_RATE(2136000000, 2, 356, 1, 0),
44 RK3588_PLL_RATE(2112000000, 2, 352, 1, 0),
45 RK3588_PLL_RATE(2088000000, 2, 348, 1, 0),
46 RK3588_PLL_RATE(2064000000, 2, 344, 1, 0),
47 RK3588_PLL_RATE(2040000000, 2, 340, 1, 0),
48 RK3588_PLL_RATE(2016000000, 2, 336, 1, 0),
49 RK3588_PLL_RATE(1992000000, 2, 332, 1, 0),
50 RK3588_PLL_RATE(1968000000, 2, 328, 1, 0),
51 RK3588_PLL_RATE(1944000000, 2, 324, 1, 0),
52 RK3588_PLL_RATE(1920000000, 2, 320, 1, 0),
53 RK3588_PLL_RATE(1896000000, 2, 316, 1, 0),
54 RK3588_PLL_RATE(1872000000, 2, 312, 1, 0),
55 RK3588_PLL_RATE(1848000000, 2, 308, 1, 0),
56 RK3588_PLL_RATE(1824000000, 2, 304, 1, 0),
57 RK3588_PLL_RATE(1800000000, 2, 300, 1, 0),
58 RK3588_PLL_RATE(1776000000, 2, 296, 1, 0),
59 RK3588_PLL_RATE(1752000000, 2, 292, 1, 0),
60 RK3588_PLL_RATE(1728000000, 2, 288, 1, 0),
61 RK3588_PLL_RATE(1704000000, 2, 284, 1, 0),
62 RK3588_PLL_RATE(1680000000, 2, 280, 1, 0),
63 RK3588_PLL_RATE(1656000000, 2, 276, 1, 0),
64 RK3588_PLL_RATE(1632000000, 2, 272, 1, 0),
65 RK3588_PLL_RATE(1608000000, 2, 268, 1, 0),
66 RK3588_PLL_RATE(1584000000, 2, 264, 1, 0),
67 RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),
68 RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
69 RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
70 RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
71 RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
72 RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),
73 RK3588_PLL_RATE(1416000000, 2, 236, 1, 0),
74 RK3588_PLL_RATE(1392000000, 2, 232, 1, 0),
75 RK3588_PLL_RATE(1320000000, 2, 220, 1, 0),
76 RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
77 RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
78 RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
79 RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
80 RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
81 RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
82 RK3588_PLL_RATE(955520000, 3, 477, 2, 49806),
83 RK3588_PLL_RATE(903168000, 6, 903, 2, 11009),
84 RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
85 RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
86 RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
87 RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
88 RK3588_PLL_RATE(785560000, 3, 392, 2, 51117),
89 RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
90 RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
91 RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
92 RK3588_PLL_RATE(408000000, 2, 272, 3, 0),
93 RK3588_PLL_RATE(312000000, 2, 208, 3, 0),
94 RK3588_PLL_RATE(216000000, 2, 288, 4, 0),
95 RK3588_PLL_RATE(96000000, 2, 256, 5, 0),
96 { /* sentinel */ },
97 };
98
99 #define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK 0x3
100 #define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT 13
101 #define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK 0x3
102 #define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT 5
103 #define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f
104 #define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1
105 #define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3
106 #define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12
107 #define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5
108 #define RK3588_CLK_DSU_SEL_DF_MASK 0x1
109 #define RK3588_CLK_DSU_SEL_DF_SHIFT 15
110 #define RK3588_CLK_DSU_DF_SRC_MASK 0x3
111 #define RK3588_CLK_DSU_DF_SRC_SHIFT 12
112 #define RK3588_CLK_DSU_DF_DIV_MASK 0x1f
113 #define RK3588_CLK_DSU_DF_DIV_SHIFT 7
114 #define RK3588_ACLKM_DSU_DIV_MASK 0x1f
115 #define RK3588_ACLKM_DSU_DIV_SHIFT 1
116 #define RK3588_ACLKS_DSU_DIV_MASK 0x1f
117 #define RK3588_ACLKS_DSU_DIV_SHIFT 6
118 #define RK3588_ACLKMP_DSU_DIV_MASK 0x1f
119 #define RK3588_ACLKMP_DSU_DIV_SHIFT 11
120 #define RK3588_PERIPH_DSU_DIV_MASK 0x1f
121 #define RK3588_PERIPH_DSU_DIV_SHIFT 0
122 #define RK3588_ATCLK_DSU_DIV_MASK 0x1f
123 #define RK3588_ATCLK_DSU_DIV_SHIFT 0
124 #define RK3588_GICCLK_DSU_DIV_MASK 0x1f
125 #define RK3588_GICCLK_DSU_DIV_SHIFT 5
126
127 #define RK3588_CORE_B0_SEL(_apllcore) \
128 { \
129 .reg = RK3588_BIGCORE0_CLKSEL_CON(0), \
130 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
131 RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \
132 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
133 RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \
134 }
135
136 #define RK3588_CORE_B1_SEL(_apllcore) \
137 { \
138 .reg = RK3588_BIGCORE0_CLKSEL_CON(1), \
139 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
140 RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \
141 }
142
143 #define RK3588_CORE_B2_SEL(_apllcore) \
144 { \
145 .reg = RK3588_BIGCORE1_CLKSEL_CON(0), \
146 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
147 RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \
148 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
149 RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \
150 }
151
152 #define RK3588_CORE_B3_SEL(_apllcore) \
153 { \
154 .reg = RK3588_BIGCORE1_CLKSEL_CON(1), \
155 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
156 RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \
157 }
158
159 #define RK3588_CORE_L_SEL0(_offs, _apllcore) \
160 { \
161 .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \
162 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
163 RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \
164 HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
165 RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \
166 }
167
168 #define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \
169 { \
170 .reg = RK3588_DSU_CLKSEL_CON(0), \
171 .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \
172 RK3588_CLK_DSU_DF_SRC_SHIFT) | \
173 HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \
174 RK3588_CLK_DSU_DF_DIV_SHIFT), \
175 }
176
177 #define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \
178 { \
179 .reg = RK3588_DSU_CLKSEL_CON(1), \
180 .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \
181 RK3588_ACLKM_DSU_DIV_SHIFT) | \
182 HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \
183 RK3588_ACLKMP_DSU_DIV_SHIFT) | \
184 HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \
185 RK3588_ACLKS_DSU_DIV_SHIFT), \
186 }
187
188 #define RK3588_CORE_L_SEL3(_periph) \
189 { \
190 .reg = RK3588_DSU_CLKSEL_CON(2), \
191 .val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \
192 RK3588_PERIPH_DSU_DIV_SHIFT), \
193 }
194
195 #define RK3588_CORE_L_SEL4(_gicclk, _atclk) \
196 { \
197 .reg = RK3588_DSU_CLKSEL_CON(3), \
198 .val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \
199 RK3588_GICCLK_DSU_DIV_SHIFT) | \
200 HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \
201 RK3588_ATCLK_DSU_DIV_SHIFT), \
202 }
203
204 #define RK3588_CPUB01CLK_RATE(_prate, _apllcore) \
205 { \
206 .prate = _prate##U, \
207 .pre_muxs = { \
208 RK3588_CORE_B0_SEL(0), \
209 RK3588_CORE_B1_SEL(0), \
210 }, \
211 .post_muxs = { \
212 RK3588_CORE_B0_SEL(_apllcore), \
213 RK3588_CORE_B1_SEL(_apllcore), \
214 }, \
215 }
216
217 #define RK3588_CPUB23CLK_RATE(_prate, _apllcore) \
218 { \
219 .prate = _prate##U, \
220 .pre_muxs = { \
221 RK3588_CORE_B2_SEL(0), \
222 RK3588_CORE_B3_SEL(0), \
223 }, \
224 .post_muxs = { \
225 RK3588_CORE_B2_SEL(_apllcore), \
226 RK3588_CORE_B3_SEL(_apllcore), \
227 }, \
228 }
229
230 #define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \
231 { \
232 .prate = _prate##U, \
233 .pre_muxs = { \
234 RK3588_CORE_L_SEL0(0, 0), \
235 RK3588_CORE_L_SEL0(1, 0), \
236 RK3588_CORE_L_SEL1(3, 2), \
237 RK3588_CORE_L_SEL2(2, 3, 3), \
238 RK3588_CORE_L_SEL3(4), \
239 RK3588_CORE_L_SEL4(4, 4), \
240 }, \
241 .post_muxs = { \
242 RK3588_CORE_L_SEL0(0, _apllcore), \
243 RK3588_CORE_L_SEL0(1, _apllcore), \
244 RK3588_CORE_L_SEL1(_seldsu, _divdsu), \
245 }, \
246 }
247
248 static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = {
249 RK3588_CPUB01CLK_RATE(2496000000, 1),
250 RK3588_CPUB01CLK_RATE(2400000000, 1),
251 RK3588_CPUB01CLK_RATE(2304000000, 1),
252 RK3588_CPUB01CLK_RATE(2208000000, 1),
253 RK3588_CPUB01CLK_RATE(2184000000, 1),
254 RK3588_CPUB01CLK_RATE(2088000000, 1),
255 RK3588_CPUB01CLK_RATE(2040000000, 1),
256 RK3588_CPUB01CLK_RATE(2016000000, 1),
257 RK3588_CPUB01CLK_RATE(1992000000, 1),
258 RK3588_CPUB01CLK_RATE(1896000000, 1),
259 RK3588_CPUB01CLK_RATE(1800000000, 1),
260 RK3588_CPUB01CLK_RATE(1704000000, 0),
261 RK3588_CPUB01CLK_RATE(1608000000, 0),
262 RK3588_CPUB01CLK_RATE(1584000000, 0),
263 RK3588_CPUB01CLK_RATE(1560000000, 0),
264 RK3588_CPUB01CLK_RATE(1536000000, 0),
265 RK3588_CPUB01CLK_RATE(1512000000, 0),
266 RK3588_CPUB01CLK_RATE(1488000000, 0),
267 RK3588_CPUB01CLK_RATE(1464000000, 0),
268 RK3588_CPUB01CLK_RATE(1440000000, 0),
269 RK3588_CPUB01CLK_RATE(1416000000, 0),
270 RK3588_CPUB01CLK_RATE(1392000000, 0),
271 RK3588_CPUB01CLK_RATE(1368000000, 0),
272 RK3588_CPUB01CLK_RATE(1344000000, 0),
273 RK3588_CPUB01CLK_RATE(1320000000, 0),
274 RK3588_CPUB01CLK_RATE(1296000000, 0),
275 RK3588_CPUB01CLK_RATE(1272000000, 0),
276 RK3588_CPUB01CLK_RATE(1248000000, 0),
277 RK3588_CPUB01CLK_RATE(1224000000, 0),
278 RK3588_CPUB01CLK_RATE(1200000000, 0),
279 RK3588_CPUB01CLK_RATE(1104000000, 0),
280 RK3588_CPUB01CLK_RATE(1008000000, 0),
281 RK3588_CPUB01CLK_RATE(912000000, 0),
282 RK3588_CPUB01CLK_RATE(816000000, 0),
283 RK3588_CPUB01CLK_RATE(696000000, 0),
284 RK3588_CPUB01CLK_RATE(600000000, 0),
285 RK3588_CPUB01CLK_RATE(408000000, 0),
286 RK3588_CPUB01CLK_RATE(312000000, 0),
287 RK3588_CPUB01CLK_RATE(216000000, 0),
288 RK3588_CPUB01CLK_RATE(96000000, 0),
289 };
290
291 static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = {
292 .core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0),
293 .div_core_shift[0] = 8,
294 .div_core_mask[0] = 0x1f,
295 .core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1),
296 .div_core_shift[1] = 0,
297 .div_core_mask[1] = 0x1f,
298 .num_cores = 2,
299 .mux_core_alt = 1,
300 .mux_core_main = 2,
301 .mux_core_shift = 6,
302 .mux_core_mask = 0x3,
303 };
304
305 static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = {
306 RK3588_CPUB23CLK_RATE(2496000000, 1),
307 RK3588_CPUB23CLK_RATE(2400000000, 1),
308 RK3588_CPUB23CLK_RATE(2304000000, 1),
309 RK3588_CPUB23CLK_RATE(2208000000, 1),
310 RK3588_CPUB23CLK_RATE(2184000000, 1),
311 RK3588_CPUB23CLK_RATE(2088000000, 1),
312 RK3588_CPUB23CLK_RATE(2040000000, 1),
313 RK3588_CPUB23CLK_RATE(2016000000, 1),
314 RK3588_CPUB23CLK_RATE(1992000000, 1),
315 RK3588_CPUB23CLK_RATE(1896000000, 1),
316 RK3588_CPUB23CLK_RATE(1800000000, 1),
317 RK3588_CPUB23CLK_RATE(1704000000, 0),
318 RK3588_CPUB23CLK_RATE(1608000000, 0),
319 RK3588_CPUB23CLK_RATE(1584000000, 0),
320 RK3588_CPUB23CLK_RATE(1560000000, 0),
321 RK3588_CPUB23CLK_RATE(1536000000, 0),
322 RK3588_CPUB23CLK_RATE(1512000000, 0),
323 RK3588_CPUB23CLK_RATE(1488000000, 0),
324 RK3588_CPUB23CLK_RATE(1464000000, 0),
325 RK3588_CPUB23CLK_RATE(1440000000, 0),
326 RK3588_CPUB23CLK_RATE(1416000000, 0),
327 RK3588_CPUB23CLK_RATE(1392000000, 0),
328 RK3588_CPUB23CLK_RATE(1368000000, 0),
329 RK3588_CPUB23CLK_RATE(1344000000, 0),
330 RK3588_CPUB23CLK_RATE(1320000000, 0),
331 RK3588_CPUB23CLK_RATE(1296000000, 0),
332 RK3588_CPUB23CLK_RATE(1272000000, 0),
333 RK3588_CPUB23CLK_RATE(1248000000, 0),
334 RK3588_CPUB23CLK_RATE(1224000000, 0),
335 RK3588_CPUB23CLK_RATE(1200000000, 0),
336 RK3588_CPUB23CLK_RATE(1104000000, 0),
337 RK3588_CPUB23CLK_RATE(1008000000, 0),
338 RK3588_CPUB23CLK_RATE(912000000, 0),
339 RK3588_CPUB23CLK_RATE(816000000, 0),
340 RK3588_CPUB23CLK_RATE(696000000, 0),
341 RK3588_CPUB23CLK_RATE(600000000, 0),
342 RK3588_CPUB23CLK_RATE(408000000, 0),
343 RK3588_CPUB23CLK_RATE(312000000, 0),
344 RK3588_CPUB23CLK_RATE(216000000, 0),
345 RK3588_CPUB23CLK_RATE(96000000, 0),
346 };
347
348 static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = {
349 .core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0),
350 .div_core_shift[0] = 8,
351 .div_core_mask[0] = 0x1f,
352 .core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1),
353 .div_core_shift[1] = 0,
354 .div_core_mask[1] = 0x1f,
355 .num_cores = 2,
356 .mux_core_alt = 1,
357 .mux_core_main = 2,
358 .mux_core_shift = 6,
359 .mux_core_mask = 0x3,
360 };
361
362 static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = {
363 RK3588_CPULCLK_RATE(2208000000, 1, 3, 1),
364 RK3588_CPULCLK_RATE(2184000000, 1, 3, 1),
365 RK3588_CPULCLK_RATE(2088000000, 1, 3, 1),
366 RK3588_CPULCLK_RATE(2040000000, 1, 3, 1),
367 RK3588_CPULCLK_RATE(2016000000, 1, 3, 1),
368 RK3588_CPULCLK_RATE(1992000000, 1, 3, 1),
369 RK3588_CPULCLK_RATE(1896000000, 1, 3, 1),
370 RK3588_CPULCLK_RATE(1800000000, 1, 3, 1),
371 RK3588_CPULCLK_RATE(1704000000, 0, 3, 1),
372 RK3588_CPULCLK_RATE(1608000000, 0, 3, 1),
373 RK3588_CPULCLK_RATE(1584000000, 0, 2, 1),
374 RK3588_CPULCLK_RATE(1560000000, 0, 2, 1),
375 RK3588_CPULCLK_RATE(1536000000, 0, 2, 1),
376 RK3588_CPULCLK_RATE(1512000000, 0, 2, 1),
377 RK3588_CPULCLK_RATE(1488000000, 0, 2, 1),
378 RK3588_CPULCLK_RATE(1464000000, 0, 2, 1),
379 RK3588_CPULCLK_RATE(1440000000, 0, 2, 1),
380 RK3588_CPULCLK_RATE(1416000000, 0, 2, 1),
381 RK3588_CPULCLK_RATE(1392000000, 0, 2, 1),
382 RK3588_CPULCLK_RATE(1368000000, 0, 2, 1),
383 RK3588_CPULCLK_RATE(1344000000, 0, 2, 1),
384 RK3588_CPULCLK_RATE(1320000000, 0, 2, 1),
385 RK3588_CPULCLK_RATE(1296000000, 0, 2, 1),
386 RK3588_CPULCLK_RATE(1272000000, 0, 2, 1),
387 RK3588_CPULCLK_RATE(1248000000, 0, 2, 1),
388 RK3588_CPULCLK_RATE(1224000000, 0, 2, 1),
389 RK3588_CPULCLK_RATE(1200000000, 0, 2, 1),
390 RK3588_CPULCLK_RATE(1104000000, 0, 2, 1),
391 RK3588_CPULCLK_RATE(1008000000, 0, 2, 1),
392 RK3588_CPULCLK_RATE(912000000, 0, 2, 1),
393 RK3588_CPULCLK_RATE(816000000, 0, 2, 1),
394 RK3588_CPULCLK_RATE(696000000, 0, 2, 1),
395 RK3588_CPULCLK_RATE(600000000, 0, 2, 1),
396 RK3588_CPULCLK_RATE(408000000, 0, 2, 1),
397 RK3588_CPULCLK_RATE(312000000, 0, 2, 1),
398 RK3588_CPULCLK_RATE(216000000, 0, 2, 1),
399 RK3588_CPULCLK_RATE(96000000, 0, 2, 1),
400 };
401
402 static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = {
403 .core_reg[0] = RK3588_DSU_CLKSEL_CON(6),
404 .div_core_shift[0] = 0,
405 .div_core_mask[0] = 0x1f,
406 .core_reg[1] = RK3588_DSU_CLKSEL_CON(6),
407 .div_core_shift[1] = 7,
408 .div_core_mask[1] = 0x1f,
409 .core_reg[2] = RK3588_DSU_CLKSEL_CON(7),
410 .div_core_shift[2] = 0,
411 .div_core_mask[2] = 0x1f,
412 .core_reg[3] = RK3588_DSU_CLKSEL_CON(7),
413 .div_core_shift[3] = 7,
414 .div_core_mask[3] = 0x1f,
415 .num_cores = 4,
416 .mux_core_reg = RK3588_DSU_CLKSEL_CON(5),
417 .mux_core_alt = 1,
418 .mux_core_main = 2,
419 .mux_core_shift = 14,
420 .mux_core_mask = 0x3,
421 };
422
423 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
424 PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" };
425 PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",};
426 PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",};
427 PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" };
428 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
429 PNAME(gpll_aupll_p) = { "gpll", "aupll" };
430 PNAME(gpll_lpll_p) = { "gpll", "lpll" };
431 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
432 PNAME(gpll_spll_p) = { "gpll", "spll" };
433 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"};
434 PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll"};
435 PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll"};
436 PNAME(gpll_cpll_npll_v0pll_p) = { "gpll", "cpll", "npll", "v0pll"};
437 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
438 PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" };
439 PNAME(gpll_cpll_aupll_npll_p) = { "gpll", "cpll", "aupll", "npll" };
440 PNAME(gpll_cpll_v0pll_aupll_p) = { "gpll", "cpll", "v0pll", "aupll" };
441 PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" };
442 PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" };
443 PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" };
444 PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" };
445 PNAME(gpll_cpll_npll_1000m_p) = { "gpll", "cpll", "npll", "clk_1000m_src" };
446 PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" };
447 PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" };
448 PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" };
449 PNAME(mux_200m_100m_p) = { "clk_200m_src", "clk_100m_src" };
450 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
451 PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" };
452 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" };
453 PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" };
454 PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
455 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
456 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
457 PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" };
458 PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" };
459 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
460 PNAME(mux_400m_200m_100m_24m_p) = {"clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
461 PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" };
462 PNAME(i2s2_2ch_mclkout_p) = { "mclk_i2s2_2ch", "xin12m" };
463 PNAME(clk_i2s3_2ch_p) = { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" };
464 PNAME(i2s3_2ch_mclkout_p) = { "mclk_i2s3_2ch", "xin12m" };
465 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" };
466 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" };
467 PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" };
468 PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" };
469 PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" };
470 PNAME(i2s1_8ch_mclkout_p) = { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" };
471 PNAME(clk_i2s4_8ch_tx_p) = { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" };
472 PNAME(clk_i2s5_8ch_tx_p) = { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" };
473 PNAME(clk_i2s6_8ch_tx_p) = { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" };
474 PNAME(clk_i2s6_8ch_rx_p) = { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" };
475 PNAME(i2s6_8ch_mclkout_p) = { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" };
476 PNAME(clk_i2s7_8ch_rx_p) = { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" };
477 PNAME(clk_i2s8_8ch_tx_p) = { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" };
478 PNAME(clk_i2s9_8ch_rx_p) = { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" };
479 PNAME(clk_i2s10_8ch_rx_p) = { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" };
480 PNAME(clk_spdif0_p) = { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" };
481 PNAME(clk_spdif1_p) = { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" };
482 PNAME(clk_spdif2_dp0_p) = { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" };
483 PNAME(clk_spdif3_p) = { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" };
484 PNAME(clk_spdif4_p) = { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" };
485 PNAME(clk_spdif5_dp1_p) = { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" };
486 PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
487 PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
488 PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
489 PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
490 PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
491 PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
492 PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
493 PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
494 PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
495 PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
496 PNAME(clk_gmac0_ptp_ref_p) = { "cpll", "clk_gmac0_ptpref_io" };
497 PNAME(clk_gmac1_ptp_ref_p) = { "cpll", "clk_gmac1_ptpref_io" };
498 PNAME(clk_hdmirx_aud_p) = { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" };
499 PNAME(aclk_hdcp1_root_p) = { "gpll", "cpll", "clk_hdmitrx_refsrc" };
500 PNAME(aclk_vop_sub_src_p) = { "aclk_vop_root", "aclk_vop_div2_src" };
501 PNAME(dclk_vop0_p) = { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
502 PNAME(dclk_vop1_p) = { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
503 PNAME(dclk_vop2_p) = { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
504 PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" };
505 PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" };
506 PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" };
507 PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
508 PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "32k", "clk_pmu1_100m_src" };
509 PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
510 PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" };
511 PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" };
512 PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" };
513 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
514 PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" };
515 PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" };
516 PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" };
517
518 #define MFLAGS CLK_MUX_HIWORD_MASK
519 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
520 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
521
522 static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata =
523 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
524 RK3588_CLKSEL_CON(26), 0, 2, MFLAGS);
525
526 static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata =
527 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
528 RK3588_CLKSEL_CON(28), 0, 2, MFLAGS);
529
530 static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata =
531 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
532 RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS);
533
534 static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata =
535 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
536 RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS);
537
538 static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata =
539 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
540 RK3588_CLKSEL_CON(30), 0, 2, MFLAGS);
541
542 static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata =
543 MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT,
544 RK3588_CLKSEL_CON(32), 0, 2, MFLAGS);
545
546 static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata =
547 MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT,
548 RK3588_CLKSEL_CON(120), 0, 2, MFLAGS);
549
550 static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata =
551 MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT,
552 RK3588_CLKSEL_CON(142), 0, 2, MFLAGS);
553
554 static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata =
555 MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT,
556 RK3588_CLKSEL_CON(146), 0, 2, MFLAGS);
557
558 static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata =
559 MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT,
560 RK3588_CLKSEL_CON(148), 0, 2, MFLAGS);
561
562 static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata =
563 MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT,
564 RK3588_CLKSEL_CON(131), 0, 2, MFLAGS);
565
566 static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata =
567 MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT,
568 RK3588_CLKSEL_CON(122), 0, 2, MFLAGS);
569
570 static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata =
571 MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT,
572 RK3588_CLKSEL_CON(155), 0, 2, MFLAGS);
573
574 static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata =
575 MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT,
576 RK3588_CLKSEL_CON(157), 0, 2, MFLAGS);
577
578 static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata =
579 MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT,
580 RK3588_CLKSEL_CON(34), 0, 2, MFLAGS);
581
582 static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata =
583 MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT,
584 RK3588_CLKSEL_CON(36), 0, 2, MFLAGS);
585
586 static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata =
587 MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT,
588 RK3588_CLKSEL_CON(124), 0, 2, MFLAGS);
589
590 static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata =
591 MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT,
592 RK3588_CLKSEL_CON(150), 0, 2, MFLAGS);
593
594 static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata =
595 MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT,
596 RK3588_CLKSEL_CON(152), 0, 2, MFLAGS);
597
598 static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata =
599 MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT,
600 RK3588_CLKSEL_CON(126), 0, 2, MFLAGS);
601
602 static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata =
603 MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT,
604 RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS);
605
606 static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata =
607 MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
608 RK3588_CLKSEL_CON(43), 0, 2, MFLAGS);
609
610 static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata =
611 MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
612 RK3588_CLKSEL_CON(45), 0, 2, MFLAGS);
613
614 static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata =
615 MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
616 RK3588_CLKSEL_CON(47), 0, 2, MFLAGS);
617
618 static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata =
619 MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
620 RK3588_CLKSEL_CON(49), 0, 2, MFLAGS);
621
622 static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata =
623 MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
624 RK3588_CLKSEL_CON(51), 0, 2, MFLAGS);
625
626 static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata =
627 MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT,
628 RK3588_CLKSEL_CON(53), 0, 2, MFLAGS);
629
630 static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata =
631 MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT,
632 RK3588_CLKSEL_CON(55), 0, 2, MFLAGS);
633
634 static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata =
635 MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT,
636 RK3588_CLKSEL_CON(57), 0, 2, MFLAGS);
637
638 static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata =
639 MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT,
640 RK3588_CLKSEL_CON(59), 0, 2, MFLAGS);
641
642 static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata =
643 MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT,
644 RK3588_CLKSEL_CON(140), 0, 1, MFLAGS);
645
646 static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = {
647 [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p,
648 CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0),
649 RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
650 [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p,
651 CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8),
652 RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
653 [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p,
654 CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16),
655 RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
656 [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p,
657 0, RK3588_PLL_CON(88),
658 RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates),
659 [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p,
660 0, RK3588_PLL_CON(96),
661 RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates),
662 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
663 CLK_IGNORE_UNUSED, RK3588_PLL_CON(104),
664 RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates),
665 [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,
666 CLK_IGNORE_UNUSED, RK3588_PLL_CON(112),
667 RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
668 [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p,
669 0, RK3588_PLL_CON(120),
670 RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
671 [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
672 CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128),
673 RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
674 };
675
676 static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
677 /*
678 * CRU Clock-Architecture
679 */
680 /* fixed */
681 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
682
683 /* top */
684 COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL,
685 RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
686 RK3588_CLKGATE_CON(0), 0, GFLAGS),
687 COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL,
688 RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
689 RK3588_CLKGATE_CON(0), 1, GFLAGS),
690 COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL,
691 RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
692 RK3588_CLKGATE_CON(0), 2, GFLAGS),
693 COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
694 RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
695 RK3588_CLKGATE_CON(0), 3, GFLAGS),
696 COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL,
697 RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
698 RK3588_CLKGATE_CON(0), 4, GFLAGS),
699 COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL,
700 RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
701 RK3588_CLKGATE_CON(0), 5, GFLAGS),
702 COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL,
703 RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
704 RK3588_CLKGATE_CON(0), 6, GFLAGS),
705 COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL,
706 RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
707 RK3588_CLKGATE_CON(0), 7, GFLAGS),
708 COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0,
709 RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
710 RK3588_CLKGATE_CON(0), 8, GFLAGS),
711 COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL,
712 RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
713 RK3588_CLKGATE_CON(0), 9, GFLAGS),
714 COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL,
715 RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
716 RK3588_CLKGATE_CON(0), 10, GFLAGS),
717 COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0,
718 RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS,
719 RK3588_CLKGATE_CON(0), 11, GFLAGS),
720 COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL,
721 RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS,
722 RK3588_CLKGATE_CON(0), 12, GFLAGS),
723 COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL,
724 RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS,
725 RK3588_CLKGATE_CON(0), 13, GFLAGS),
726 COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL,
727 RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS,
728 RK3588_CLKGATE_CON(0), 14, GFLAGS),
729 COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
730 RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS,
731 RK3588_CLKGATE_CON(0), 15, GFLAGS),
732 COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
733 RK3588_CLKSEL_CON(9), 0, 2, MFLAGS,
734 RK3588_CLKGATE_CON(1), 10, GFLAGS),
735 COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
736 RK3588_CLKSEL_CON(9), 2, 2, MFLAGS,
737 RK3588_CLKGATE_CON(1), 11, GFLAGS),
738 COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
739 RK3588_CLKSEL_CON(9), 4, 2, MFLAGS,
740 RK3588_CLKGATE_CON(1), 12, GFLAGS),
741 COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
742 RK3588_CLKSEL_CON(9), 6, 2, MFLAGS,
743 RK3588_CLKGATE_CON(1), 13, GFLAGS),
744 COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
745 RK3588_CLKSEL_CON(9), 8, 2, MFLAGS,
746 RK3588_CLKGATE_CON(1), 14, GFLAGS),
747 COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL,
748 RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS,
749 RK3588_CLKGATE_CON(1), 0, GFLAGS),
750 COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
751 RK3588_CLKSEL_CON(8), 7, 2, MFLAGS,
752 RK3588_CLKGATE_CON(1), 1, GFLAGS),
753 COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
754 RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS,
755 RK3588_CLKGATE_CON(1), 2, GFLAGS),
756 COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0,
757 RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS,
758 RK3588_CLKGATE_CON(5), 9, GFLAGS),
759 COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0,
760 RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS,
761 RK3588_CLKGATE_CON(5), 10, GFLAGS),
762 COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0,
763 RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
764 RK3588_CLKGATE_CON(5), 11, GFLAGS),
765 COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0,
766 RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS,
767 RK3588_CLKGATE_CON(5), 12, GFLAGS),
768 COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0,
769 RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS,
770 RK3588_CLKGATE_CON(5), 13, GFLAGS),
771 COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0,
772 RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS,
773 RK3588_CLKGATE_CON(5), 3, GFLAGS),
774 COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0,
775 RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS,
776 RK3588_CLKGATE_CON(5), 4, GFLAGS),
777 COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0,
778 RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS,
779 RK3588_CLKGATE_CON(5), 5, GFLAGS),
780 COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0,
781 RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS,
782 RK3588_CLKGATE_CON(5), 6, GFLAGS),
783 GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0,
784 RK3588_CLKGATE_CON(3), 14, GFLAGS),
785 GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0,
786 RK3588_CLKGATE_CON(4), 3, GFLAGS),
787 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0,
788 RK3588_CLKGATE_CON(1), 6, GFLAGS),
789 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0,
790 RK3588_CLKGATE_CON(1), 8, GFLAGS),
791 GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL,
792 RK3588_CLKGATE_CON(5), 0, GFLAGS),
793
794 /* bigcore0 */
795 COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
796 RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS,
797 RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS),
798 GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0,
799 RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS),
800 GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0,
801 RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS),
802 GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0,
803 RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS),
804
805 /* bigcore1 */
806 COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
807 RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS,
808 RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS),
809 GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0,
810 RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS),
811 GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0,
812 RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS),
813 GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0,
814 RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS),
815
816 /* dsu */
817 COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL,
818 RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS,
819 RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS),
820 COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL,
821 RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
822 RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS),
823 COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL,
824 RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
825 RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS),
826 COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL,
827 RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
828 RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS),
829 COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL,
830 RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
831 RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS),
832 COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL,
833 RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
834 RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS),
835 COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL,
836 RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
837 RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS),
838 COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL,
839 RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
840 RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS),
841 COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL,
842 RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
843 RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS),
844 COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
845 RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS,
846 RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS),
847 COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL,
848 RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS,
849 RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS),
850 COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
851 RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS,
852 RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS),
853 GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0,
854 RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS),
855 GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL,
856 RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS),
857 GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL,
858 RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS),
859 GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED,
860 RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS),
861 GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED,
862 RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS),
863 GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0,
864 RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS),
865 GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0,
866 RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS),
867
868 /* audio */
869 COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0,
870 RK3588_CLKSEL_CON(24), 0, 2, MFLAGS,
871 RK3588_CLKGATE_CON(7), 0, GFLAGS),
872 COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0,
873 RK3588_CLKSEL_CON(24), 2, 2, MFLAGS,
874 RK3588_CLKGATE_CON(7), 1, GFLAGS),
875 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0,
876 RK3588_CLKGATE_CON(7), 12, GFLAGS),
877 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0,
878 RK3588_CLKGATE_CON(7), 13, GFLAGS),
879 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0,
880 RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS,
881 RK3588_CLKGATE_CON(7), 14, GFLAGS),
882 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
883 RK3588_CLKSEL_CON(29), 0,
884 RK3588_CLKGATE_CON(7), 15, GFLAGS,
885 &rk3588_i2s2_2ch_fracmux),
886 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
887 RK3588_CLKGATE_CON(8), 0, GFLAGS),
888 MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT,
889 RK3588_CLKSEL_CON(30), 2, 1, MFLAGS),
890
891 COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0,
892 RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS,
893 RK3588_CLKGATE_CON(8), 1, GFLAGS),
894 COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src", CLK_SET_RATE_PARENT,
895 RK3588_CLKSEL_CON(31), 0,
896 RK3588_CLKGATE_CON(8), 2, GFLAGS,
897 &rk3588_i2s3_2ch_fracmux),
898 GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0,
899 RK3588_CLKGATE_CON(8), 3, GFLAGS),
900 GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0,
901 RK3588_CLKGATE_CON(8), 4, GFLAGS),
902 MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT,
903 RK3588_CLKSEL_CON(32), 2, 1, MFLAGS),
904 GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0,
905 RK3588_CLKGATE_CON(7), 11, GFLAGS),
906 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0,
907 RK3588_CLKGATE_CON(7), 4, GFLAGS),
908
909 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0,
910 RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS,
911 RK3588_CLKGATE_CON(7), 5, GFLAGS),
912 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
913 RK3588_CLKSEL_CON(25), 0,
914 RK3588_CLKGATE_CON(7), 6, GFLAGS,
915 &rk3588_i2s0_8ch_tx_fracmux),
916 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
917 RK3588_CLKGATE_CON(7), 7, GFLAGS),
918
919 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0,
920 RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS,
921 RK3588_CLKGATE_CON(7), 8, GFLAGS),
922 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
923 RK3588_CLKSEL_CON(27), 0,
924 RK3588_CLKGATE_CON(7), 9, GFLAGS,
925 &rk3588_i2s0_8ch_rx_fracmux),
926 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
927 RK3588_CLKGATE_CON(7), 10, GFLAGS),
928 MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
929 RK3588_CLKSEL_CON(28), 2, 2, MFLAGS),
930
931 GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0,
932 RK3588_CLKGATE_CON(9), 6, GFLAGS),
933 COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0,
934 RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS,
935 RK3588_CLKGATE_CON(9), 7, GFLAGS),
936
937 GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0,
938 RK3588_CLKGATE_CON(8), 14, GFLAGS),
939 COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0,
940 RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS,
941 RK3588_CLKGATE_CON(8), 15, GFLAGS),
942 COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src", CLK_SET_RATE_PARENT,
943 RK3588_CLKSEL_CON(33), 0,
944 RK3588_CLKGATE_CON(9), 0, GFLAGS,
945 &rk3588_spdif0_fracmux),
946 GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0,
947 RK3588_CLKGATE_CON(9), 1, GFLAGS),
948
949 GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0,
950 RK3588_CLKGATE_CON(9), 2, GFLAGS),
951 COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0,
952 RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS,
953 RK3588_CLKGATE_CON(9), 3, GFLAGS),
954 COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src", CLK_SET_RATE_PARENT,
955 RK3588_CLKSEL_CON(35), 0,
956 RK3588_CLKGATE_CON(9), 4, GFLAGS,
957 &rk3588_spdif1_fracmux),
958 GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0,
959 RK3588_CLKGATE_CON(9), 5, GFLAGS),
960
961 COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0,
962 RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS,
963 RK3588_CLKGATE_CON(68), 0, GFLAGS),
964 COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0,
965 RK3588_CLKSEL_CON(163), 7, 2, MFLAGS,
966 RK3588_CLKGATE_CON(68), 3, GFLAGS),
967
968 /* bus */
969 COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL,
970 RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
971 RK3588_CLKGATE_CON(10), 0, GFLAGS),
972
973 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0,
974 RK3588_CLKGATE_CON(16), 11, GFLAGS),
975 GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
976 RK3588_CLKGATE_CON(16), 12, GFLAGS),
977 GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
978 RK3588_CLKGATE_CON(16), 13, GFLAGS),
979 GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
980 RK3588_CLKGATE_CON(19), 3, GFLAGS),
981 GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
982 RK3588_CLKGATE_CON(19), 4, GFLAGS),
983 GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
984 RK3588_CLKGATE_CON(19), 5, GFLAGS),
985
986 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0,
987 RK3588_CLKGATE_CON(15), 3, GFLAGS),
988 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0,
989 RK3588_CLKSEL_CON(59), 12, 2, MFLAGS,
990 RK3588_CLKGATE_CON(15), 4, GFLAGS),
991 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
992 RK3588_CLKGATE_CON(15), 5, GFLAGS),
993 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0,
994 RK3588_CLKGATE_CON(15), 6, GFLAGS),
995 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0,
996 RK3588_CLKSEL_CON(59), 14, 2, MFLAGS,
997 RK3588_CLKGATE_CON(15), 7, GFLAGS),
998 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
999 RK3588_CLKGATE_CON(15), 8, GFLAGS),
1000 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0,
1001 RK3588_CLKGATE_CON(15), 9, GFLAGS),
1002 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0,
1003 RK3588_CLKSEL_CON(60), 0, 2, MFLAGS,
1004 RK3588_CLKGATE_CON(15), 10, GFLAGS),
1005 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
1006 RK3588_CLKGATE_CON(15), 11, GFLAGS),
1007
1008 GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0,
1009 RK3588_CLKGATE_CON(15), 12, GFLAGS),
1010 GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0,
1011 RK3588_CLKGATE_CON(15), 13, GFLAGS),
1012 COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0,
1013 RK3588_CLKSEL_CON(60), 2, 1, MFLAGS,
1014 RK3588_CLKGATE_CON(15), 14, GFLAGS),
1015 GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0,
1016 RK3588_CLKGATE_CON(15), 15, GFLAGS),
1017 GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0,
1018 RK3588_CLKGATE_CON(16), 0, GFLAGS),
1019 GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0,
1020 RK3588_CLKGATE_CON(16), 1, GFLAGS),
1021 GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0,
1022 RK3588_CLKGATE_CON(16), 2, GFLAGS),
1023 GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0,
1024 RK3588_CLKGATE_CON(16), 3, GFLAGS),
1025 GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0,
1026 RK3588_CLKGATE_CON(16), 4, GFLAGS),
1027 GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0,
1028 RK3588_CLKGATE_CON(16), 5, GFLAGS),
1029 GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0,
1030 RK3588_CLKGATE_CON(16), 6, GFLAGS),
1031 GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0,
1032 RK3588_CLKGATE_CON(16), 7, GFLAGS),
1033 GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0,
1034 RK3588_CLKGATE_CON(16), 8, GFLAGS),
1035 GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0,
1036 RK3588_CLKGATE_CON(16), 9, GFLAGS),
1037 GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0,
1038 RK3588_CLKGATE_CON(16), 10, GFLAGS),
1039
1040 GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0,
1041 RK3588_CLKGATE_CON(15), 0, GFLAGS),
1042 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
1043 RK3588_CLKGATE_CON(15), 1, GFLAGS),
1044
1045 GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0,
1046 RK3588_CLKGATE_CON(11), 8, GFLAGS),
1047 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
1048 RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS,
1049 RK3588_CLKGATE_CON(11), 9, GFLAGS),
1050 GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0,
1051 RK3588_CLKGATE_CON(11), 10, GFLAGS),
1052 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
1053 RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS,
1054 RK3588_CLKGATE_CON(11), 11, GFLAGS),
1055 GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0,
1056 RK3588_CLKGATE_CON(11), 12, GFLAGS),
1057 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
1058 RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS,
1059 RK3588_CLKGATE_CON(11), 13, GFLAGS),
1060
1061 GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0,
1062 RK3588_CLKGATE_CON(17), 6, GFLAGS),
1063 GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0,
1064 RK3588_CLKGATE_CON(17), 7, GFLAGS),
1065 COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0,
1066 RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS,
1067 RK3588_CLKGATE_CON(17), 8, GFLAGS),
1068 GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0,
1069 RK3588_CLKGATE_CON(10), 5, GFLAGS),
1070 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0,
1071 RK3588_CLKGATE_CON(10), 6, GFLAGS),
1072 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0,
1073 RK3588_CLKGATE_CON(10), 7, GFLAGS),
1074 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL,
1075 RK3588_CLKGATE_CON(10), 3, GFLAGS),
1076
1077 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0,
1078 RK3588_CLKGATE_CON(16), 14, GFLAGS),
1079 COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0,
1080 RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS,
1081 RK3588_CLKGATE_CON(16), 15, GFLAGS),
1082 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0,
1083 RK3588_CLKGATE_CON(17), 0, GFLAGS),
1084 COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0,
1085 RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS,
1086 RK3588_CLKGATE_CON(17), 1, GFLAGS),
1087 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0,
1088 RK3588_CLKGATE_CON(17), 2, GFLAGS),
1089 COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0,
1090 RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS,
1091 RK3588_CLKGATE_CON(17), 3, GFLAGS),
1092 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0,
1093 RK3588_CLKGATE_CON(17), 4, GFLAGS),
1094 COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0,
1095 RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS,
1096 RK3588_CLKGATE_CON(17), 5, GFLAGS),
1097
1098 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0,
1099 RK3588_CLKGATE_CON(10), 8, GFLAGS),
1100 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0,
1101 RK3588_CLKGATE_CON(10), 9, GFLAGS),
1102 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0,
1103 RK3588_CLKGATE_CON(10), 10, GFLAGS),
1104 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0,
1105 RK3588_CLKGATE_CON(10), 11, GFLAGS),
1106 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0,
1107 RK3588_CLKGATE_CON(10), 12, GFLAGS),
1108 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0,
1109 RK3588_CLKGATE_CON(10), 13, GFLAGS),
1110 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0,
1111 RK3588_CLKGATE_CON(10), 14, GFLAGS),
1112 GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0,
1113 RK3588_CLKGATE_CON(10), 15, GFLAGS),
1114 COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0,
1115 RK3588_CLKSEL_CON(38), 6, 1, MFLAGS,
1116 RK3588_CLKGATE_CON(11), 0, GFLAGS),
1117 COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0,
1118 RK3588_CLKSEL_CON(38), 7, 1, MFLAGS,
1119 RK3588_CLKGATE_CON(11), 1, GFLAGS),
1120 COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0,
1121 RK3588_CLKSEL_CON(38), 8, 1, MFLAGS,
1122 RK3588_CLKGATE_CON(11), 2, GFLAGS),
1123 COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0,
1124 RK3588_CLKSEL_CON(38), 9, 1, MFLAGS,
1125 RK3588_CLKGATE_CON(11), 3, GFLAGS),
1126 COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0,
1127 RK3588_CLKSEL_CON(38), 10, 1, MFLAGS,
1128 RK3588_CLKGATE_CON(11), 4, GFLAGS),
1129 COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0,
1130 RK3588_CLKSEL_CON(38), 11, 1, MFLAGS,
1131 RK3588_CLKGATE_CON(11), 5, GFLAGS),
1132 COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0,
1133 RK3588_CLKSEL_CON(38), 12, 1, MFLAGS,
1134 RK3588_CLKGATE_CON(11), 6, GFLAGS),
1135 COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0,
1136 RK3588_CLKSEL_CON(38), 13, 1, MFLAGS,
1137 RK3588_CLKGATE_CON(11), 7, GFLAGS),
1138
1139 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0,
1140 RK3588_CLKGATE_CON(18), 9, GFLAGS),
1141 GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
1142 RK3588_CLKGATE_CON(18), 10, GFLAGS),
1143 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
1144 RK3588_CLKGATE_CON(18), 11, GFLAGS),
1145 GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
1146 RK3588_CLKGATE_CON(18), 13, GFLAGS),
1147 GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
1148 RK3588_CLKGATE_CON(18), 12, GFLAGS),
1149
1150 GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0,
1151 RK3588_CLKGATE_CON(11), 14, GFLAGS),
1152 COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0,
1153 RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS,
1154 RK3588_CLKGATE_CON(11), 15, GFLAGS),
1155
1156 GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0,
1157 RK3588_CLKGATE_CON(14), 6, GFLAGS),
1158 GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0,
1159 RK3588_CLKGATE_CON(14), 7, GFLAGS),
1160 GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0,
1161 RK3588_CLKGATE_CON(14), 8, GFLAGS),
1162 GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0,
1163 RK3588_CLKGATE_CON(14), 9, GFLAGS),
1164 GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0,
1165 RK3588_CLKGATE_CON(14), 10, GFLAGS),
1166 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0,
1167 RK3588_CLKSEL_CON(59), 2, 2, MFLAGS,
1168 RK3588_CLKGATE_CON(14), 11, GFLAGS),
1169 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0,
1170 RK3588_CLKSEL_CON(59), 4, 2, MFLAGS,
1171 RK3588_CLKGATE_CON(14), 12, GFLAGS),
1172 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0,
1173 RK3588_CLKSEL_CON(59), 6, 2, MFLAGS,
1174 RK3588_CLKGATE_CON(14), 13, GFLAGS),
1175 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0,
1176 RK3588_CLKSEL_CON(59), 8, 2, MFLAGS,
1177 RK3588_CLKGATE_CON(14), 14, GFLAGS),
1178 COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0,
1179 RK3588_CLKSEL_CON(59), 10, 2, MFLAGS,
1180 RK3588_CLKGATE_CON(14), 15, GFLAGS),
1181
1182 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED,
1183 RK3588_CLKGATE_CON(18), 6, GFLAGS),
1184 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0,
1185 RK3588_CLKGATE_CON(12), 0, GFLAGS),
1186 COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0,
1187 RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS,
1188 RK3588_CLKGATE_CON(12), 1, GFLAGS),
1189
1190 GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0,
1191 RK3588_CLKGATE_CON(12), 2, GFLAGS),
1192 GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0,
1193 RK3588_CLKGATE_CON(12), 3, GFLAGS),
1194 GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0,
1195 RK3588_CLKGATE_CON(12), 4, GFLAGS),
1196 GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0,
1197 RK3588_CLKGATE_CON(12), 5, GFLAGS),
1198 GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0,
1199 RK3588_CLKGATE_CON(12), 6, GFLAGS),
1200 GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0,
1201 RK3588_CLKGATE_CON(12), 7, GFLAGS),
1202 GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0,
1203 RK3588_CLKGATE_CON(12), 8, GFLAGS),
1204 GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0,
1205 RK3588_CLKGATE_CON(12), 9, GFLAGS),
1206 GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0,
1207 RK3588_CLKGATE_CON(12), 10, GFLAGS),
1208
1209 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0,
1210 RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS,
1211 RK3588_CLKGATE_CON(12), 11, GFLAGS),
1212 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
1213 RK3588_CLKSEL_CON(42), CLK_FRAC_DIVIDER_NO_LIMIT,
1214 RK3588_CLKGATE_CON(12), 12, GFLAGS,
1215 &rk3588_uart1_fracmux),
1216 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
1217 RK3588_CLKGATE_CON(12), 13, GFLAGS),
1218 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0,
1219 RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS,
1220 RK3588_CLKGATE_CON(12), 14, GFLAGS),
1221 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
1222 RK3588_CLKSEL_CON(44), CLK_FRAC_DIVIDER_NO_LIMIT,
1223 RK3588_CLKGATE_CON(12), 15, GFLAGS,
1224 &rk3588_uart2_fracmux),
1225 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
1226 RK3588_CLKGATE_CON(13), 0, GFLAGS),
1227 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0,
1228 RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS,
1229 RK3588_CLKGATE_CON(13), 1, GFLAGS),
1230 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
1231 RK3588_CLKSEL_CON(46), CLK_FRAC_DIVIDER_NO_LIMIT,
1232 RK3588_CLKGATE_CON(13), 2, GFLAGS,
1233 &rk3588_uart3_fracmux),
1234 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
1235 RK3588_CLKGATE_CON(13), 3, GFLAGS),
1236 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0,
1237 RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS,
1238 RK3588_CLKGATE_CON(13), 4, GFLAGS),
1239 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
1240 RK3588_CLKSEL_CON(48), CLK_FRAC_DIVIDER_NO_LIMIT,
1241 RK3588_CLKGATE_CON(13), 5, GFLAGS,
1242 &rk3588_uart4_fracmux),
1243 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
1244 RK3588_CLKGATE_CON(13), 6, GFLAGS),
1245 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0,
1246 RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS,
1247 RK3588_CLKGATE_CON(13), 7, GFLAGS),
1248 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
1249 RK3588_CLKSEL_CON(50), CLK_FRAC_DIVIDER_NO_LIMIT,
1250 RK3588_CLKGATE_CON(13), 8, GFLAGS,
1251 &rk3588_uart5_fracmux),
1252 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
1253 RK3588_CLKGATE_CON(13), 9, GFLAGS),
1254 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0,
1255 RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS,
1256 RK3588_CLKGATE_CON(13), 10, GFLAGS),
1257 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
1258 RK3588_CLKSEL_CON(52), CLK_FRAC_DIVIDER_NO_LIMIT,
1259 RK3588_CLKGATE_CON(13), 11, GFLAGS,
1260 &rk3588_uart6_fracmux),
1261 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
1262 RK3588_CLKGATE_CON(13), 12, GFLAGS),
1263 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0,
1264 RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS,
1265 RK3588_CLKGATE_CON(13), 13, GFLAGS),
1266 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
1267 RK3588_CLKSEL_CON(54), CLK_FRAC_DIVIDER_NO_LIMIT,
1268 RK3588_CLKGATE_CON(13), 14, GFLAGS,
1269 &rk3588_uart7_fracmux),
1270 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
1271 RK3588_CLKGATE_CON(13), 15, GFLAGS),
1272 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0,
1273 RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS,
1274 RK3588_CLKGATE_CON(14), 0, GFLAGS),
1275 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
1276 RK3588_CLKSEL_CON(56), CLK_FRAC_DIVIDER_NO_LIMIT,
1277 RK3588_CLKGATE_CON(14), 1, GFLAGS,
1278 &rk3588_uart8_fracmux),
1279 GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0,
1280 RK3588_CLKGATE_CON(14), 2, GFLAGS),
1281 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0,
1282 RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS,
1283 RK3588_CLKGATE_CON(14), 3, GFLAGS),
1284 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
1285 RK3588_CLKSEL_CON(58), CLK_FRAC_DIVIDER_NO_LIMIT,
1286 RK3588_CLKGATE_CON(14), 4, GFLAGS,
1287 &rk3588_uart9_fracmux),
1288 GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0,
1289 RK3588_CLKGATE_CON(14), 5, GFLAGS),
1290
1291 /* center */
1292 COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p, CLK_IS_CRITICAL,
1293 RK3588_CLKSEL_CON(165), 0, 2, MFLAGS,
1294 RK3588_CLKGATE_CON(69), 0, GFLAGS),
1295 COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, CLK_IS_CRITICAL,
1296 RK3588_CLKSEL_CON(165), 2, 2, MFLAGS,
1297 RK3588_CLKGATE_CON(69), 1, GFLAGS),
1298 COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
1299 RK3588_CLKSEL_CON(165), 4, 2, MFLAGS,
1300 RK3588_CLKGATE_CON(69), 2, GFLAGS),
1301 COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
1302 RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY,
1303 RK3588_CLKGATE_CON(69), 3, GFLAGS),
1304 GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL,
1305 RK3588_CLKGATE_CON(69), 5, GFLAGS),
1306 GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL,
1307 RK3588_CLKGATE_CON(69), 6, GFLAGS),
1308 COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
1309 RK3588_CLKSEL_CON(165), 8, 2, MFLAGS,
1310 RK3588_CLKGATE_CON(69), 8, GFLAGS),
1311 COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
1312 RK3588_CLKSEL_CON(165), 10, 2, MFLAGS,
1313 RK3588_CLKGATE_CON(69), 9, GFLAGS),
1314 GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL,
1315 RK3588_CLKGATE_CON(69), 14, GFLAGS),
1316 COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED,
1317 RK3588_CLKSEL_CON(165), 12, 1, MFLAGS,
1318 RK3588_CLKGATE_CON(69), 15, GFLAGS),
1319 GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0,
1320 RK3588_CLKGATE_CON(70), 0, GFLAGS),
1321 GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0,
1322 RK3588_CLKGATE_CON(70), 1, GFLAGS),
1323 GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0,
1324 RK3588_CLKGATE_CON(70), 2, GFLAGS),
1325 COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL,
1326 RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS,
1327 RK3588_CLKGATE_CON(70), 4, GFLAGS),
1328 GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0,
1329 RK3588_CLKGATE_CON(70), 7, GFLAGS),
1330 GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0,
1331 RK3588_CLKGATE_CON(70), 8, GFLAGS),
1332 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL,
1333 RK3588_CLKGATE_CON(70), 9, GFLAGS),
1334 GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL,
1335 RK3588_CLKGATE_CON(70), 10, GFLAGS),
1336
1337 /* gpu */
1338 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0,
1339 RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS,
1340 RK3588_CLKGATE_CON(66), 1, GFLAGS),
1341 GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0,
1342 RK3588_CLKGATE_CON(66), 4, GFLAGS),
1343 GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0,
1344 RK3588_CLKGATE_CON(66), 6, GFLAGS),
1345 COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0,
1346 RK3588_CLKSEL_CON(159), 0, 5, DFLAGS,
1347 RK3588_CLKGATE_CON(66), 7, GFLAGS),
1348 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
1349 RK3588_CLKGATE_CON(67), 0, GFLAGS),
1350 GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0,
1351 RK3588_CLKGATE_CON(67), 1, GFLAGS),
1352
1353 /* isp1 */
1354 COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0,
1355 RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS,
1356 RK3588_CLKGATE_CON(26), 0, GFLAGS),
1357 COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0,
1358 RK3588_CLKSEL_CON(67), 7, 2, MFLAGS,
1359 RK3588_CLKGATE_CON(26), 1, GFLAGS),
1360 COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0,
1361 RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS,
1362 RK3588_CLKGATE_CON(26), 2, GFLAGS),
1363 GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0,
1364 RK3588_CLKGATE_CON(26), 3, GFLAGS),
1365 GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0,
1366 RK3588_CLKGATE_CON(26), 4, GFLAGS),
1367
1368 /* npu */
1369 COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0,
1370 RK3588_CLKSEL_CON(73), 0, 2, MFLAGS,
1371 RK3588_CLKGATE_CON(29), 0, GFLAGS),
1372 COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0,
1373 RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS,
1374 RK3588_CLKGATE_CON(29), 1, GFLAGS),
1375 COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0,
1376 RK3588_CLKSEL_CON(74), 1, 2, MFLAGS,
1377 RK3588_CLKGATE_CON(29), 4, GFLAGS),
1378 GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0,
1379 RK3588_CLKGATE_CON(27), 0, GFLAGS),
1380 GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0,
1381 RK3588_CLKGATE_CON(27), 2, GFLAGS),
1382 GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0,
1383 RK3588_CLKGATE_CON(28), 0, GFLAGS),
1384 GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0,
1385 RK3588_CLKGATE_CON(28), 2, GFLAGS),
1386 COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0,
1387 RK3588_CLKSEL_CON(74), 5, 2, MFLAGS,
1388 RK3588_CLKGATE_CON(30), 1, GFLAGS),
1389 GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0,
1390 RK3588_CLKGATE_CON(30), 3, GFLAGS),
1391 COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0,
1392 RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS,
1393 RK3588_CLKGATE_CON(30), 5, GFLAGS),
1394 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0,
1395 RK3588_CLKGATE_CON(29), 12, GFLAGS),
1396 GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED,
1397 RK3588_CLKGATE_CON(29), 13, GFLAGS),
1398 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
1399 RK3588_CLKGATE_CON(29), 14, GFLAGS),
1400 GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0,
1401 RK3588_CLKGATE_CON(29), 15, GFLAGS),
1402 GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0,
1403 RK3588_CLKGATE_CON(30), 6, GFLAGS),
1404 GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0,
1405 RK3588_CLKGATE_CON(30), 8, GFLAGS),
1406 GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0,
1407 RK3588_CLKGATE_CON(29), 6, GFLAGS),
1408 COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0,
1409 RK3588_CLKSEL_CON(74), 3, 1, MFLAGS,
1410 RK3588_CLKGATE_CON(29), 7, GFLAGS),
1411 GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0,
1412 RK3588_CLKGATE_CON(29), 8, GFLAGS),
1413 GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0,
1414 RK3588_CLKGATE_CON(29), 9, GFLAGS),
1415 GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0,
1416 RK3588_CLKGATE_CON(29), 10, GFLAGS),
1417 GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,
1418 RK3588_CLKGATE_CON(29), 11, GFLAGS),
1419
1420 /* nvm */
1421 COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
1422 RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
1423 RK3588_CLKGATE_CON(31), 0, GFLAGS),
1424 COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
1425 RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
1426 RK3588_CLKGATE_CON(31), 1, GFLAGS),
1427 GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
1428 RK3588_CLKGATE_CON(31), 5, GFLAGS),
1429 COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0,
1430 RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS,
1431 RK3588_CLKGATE_CON(31), 6, GFLAGS),
1432 COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0,
1433 RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS,
1434 RK3588_CLKGATE_CON(31), 7, GFLAGS),
1435 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
1436 RK3588_CLKGATE_CON(31), 8, GFLAGS),
1437
1438 COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0,
1439 RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS,
1440 RK3588_CLKGATE_CON(31), 9, GFLAGS),
1441
1442 /* php */
1443 COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0,
1444 RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS,
1445 RK3588_CLKGATE_CON(34), 10, GFLAGS),
1446 COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0,
1447 RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS,
1448 RK3588_CLKGATE_CON(34), 11, GFLAGS),
1449 COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0,
1450 RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS,
1451 RK3588_CLKGATE_CON(35), 5, GFLAGS),
1452 COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0,
1453 RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS,
1454 RK3588_CLKGATE_CON(35), 6, GFLAGS),
1455
1456 COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL,
1457 RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS,
1458 RK3588_CLKGATE_CON(32), 6, GFLAGS),
1459 COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL,
1460 RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS,
1461 RK3588_CLKGATE_CON(32), 7, GFLAGS),
1462 COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0,
1463 RK3588_CLKSEL_CON(80), 0, 2, MFLAGS,
1464 RK3588_CLKGATE_CON(32), 0, GFLAGS),
1465 GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL,
1466 RK3588_CLKGATE_CON(34), 6, GFLAGS),
1467 GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0,
1468 RK3588_CLKGATE_CON(32), 8, GFLAGS),
1469 GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0,
1470 RK3588_CLKGATE_CON(34), 7, GFLAGS),
1471 GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0,
1472 RK3588_CLKGATE_CON(34), 8, GFLAGS),
1473 GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0,
1474 RK3588_CLKGATE_CON(32), 13, GFLAGS),
1475 GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0,
1476 RK3588_CLKGATE_CON(32), 14, GFLAGS),
1477 GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0,
1478 RK3588_CLKGATE_CON(32), 15, GFLAGS),
1479 GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0,
1480 RK3588_CLKGATE_CON(33), 0, GFLAGS),
1481 GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0,
1482 RK3588_CLKGATE_CON(33), 1, GFLAGS),
1483 GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0,
1484 RK3588_CLKGATE_CON(33), 2, GFLAGS),
1485 GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0,
1486 RK3588_CLKGATE_CON(33), 3, GFLAGS),
1487 GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0,
1488 RK3588_CLKGATE_CON(33), 4, GFLAGS),
1489 GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0,
1490 RK3588_CLKGATE_CON(33), 5, GFLAGS),
1491 GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0,
1492 RK3588_CLKGATE_CON(33), 6, GFLAGS),
1493 GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0,
1494 RK3588_CLKGATE_CON(33), 7, GFLAGS),
1495 GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0,
1496 RK3588_CLKGATE_CON(33), 8, GFLAGS),
1497 GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0,
1498 RK3588_CLKGATE_CON(33), 9, GFLAGS),
1499 GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0,
1500 RK3588_CLKGATE_CON(33), 10, GFLAGS),
1501 GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0,
1502 RK3588_CLKGATE_CON(33), 11, GFLAGS),
1503 GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0,
1504 RK3588_CLKGATE_CON(33), 12, GFLAGS),
1505 GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0,
1506 RK3588_CLKGATE_CON(33), 13, GFLAGS),
1507 GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0,
1508 RK3588_CLKGATE_CON(33), 14, GFLAGS),
1509 GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0,
1510 RK3588_CLKGATE_CON(33), 15, GFLAGS),
1511 GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0,
1512 RK3588_CLKGATE_CON(34), 0, GFLAGS),
1513 GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0,
1514 RK3588_CLKGATE_CON(34), 1, GFLAGS),
1515 GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0,
1516 RK3588_CLKGATE_CON(34), 2, GFLAGS),
1517 GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0,
1518 RK3588_CLKGATE_CON(34), 3, GFLAGS),
1519 GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0,
1520 RK3588_CLKGATE_CON(34), 4, GFLAGS),
1521 GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0,
1522 RK3588_CLKGATE_CON(34), 5, GFLAGS),
1523 GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0,
1524 RK3588_CLKGATE_CON(37), 0, GFLAGS),
1525 GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0,
1526 RK3588_CLKGATE_CON(37), 1, GFLAGS),
1527 GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0,
1528 RK3588_CLKGATE_CON(37), 2, GFLAGS),
1529 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0,
1530 RK3588_CLKGATE_CON(32), 3, GFLAGS),
1531 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0,
1532 RK3588_CLKGATE_CON(32), 4, GFLAGS),
1533 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0,
1534 RK3588_CLKGATE_CON(32), 10, GFLAGS),
1535 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0,
1536 RK3588_CLKGATE_CON(32), 11, GFLAGS),
1537 GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0,
1538 RK3588_CLKGATE_CON(37), 4, GFLAGS),
1539 GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0,
1540 RK3588_CLKGATE_CON(37), 5, GFLAGS),
1541 GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0,
1542 RK3588_CLKGATE_CON(37), 6, GFLAGS),
1543 GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0,
1544 RK3588_CLKGATE_CON(37), 7, GFLAGS),
1545 GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0,
1546 RK3588_CLKGATE_CON(37), 8, GFLAGS),
1547 GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0,
1548 RK3588_CLKGATE_CON(37), 9, GFLAGS),
1549 COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0,
1550 RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS,
1551 RK3588_CLKGATE_CON(37), 10, GFLAGS),
1552 COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0,
1553 RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS,
1554 RK3588_CLKGATE_CON(37), 11, GFLAGS),
1555 COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0,
1556 RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS,
1557 RK3588_CLKGATE_CON(37), 12, GFLAGS),
1558 GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0,
1559 RK3588_CLKGATE_CON(35), 7, GFLAGS),
1560 GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0,
1561 RK3588_CLKGATE_CON(35), 8, GFLAGS),
1562 GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0,
1563 RK3588_CLKGATE_CON(35), 9, GFLAGS),
1564 COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0,
1565 RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS,
1566 RK3588_CLKGATE_CON(35), 10, GFLAGS),
1567 GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0,
1568 RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS),
1569 GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0,
1570 RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS),
1571 GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0,
1572 RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS),
1573 GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0,
1574 RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS),
1575
1576 /* rga */
1577 COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0,
1578 RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS,
1579 RK3588_CLKGATE_CON(76), 6, GFLAGS),
1580 COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0,
1581 RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS,
1582 RK3588_CLKGATE_CON(76), 0, GFLAGS),
1583 COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0,
1584 RK3588_CLKSEL_CON(174), 7, 2, MFLAGS,
1585 RK3588_CLKGATE_CON(76), 1, GFLAGS),
1586 GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0,
1587 RK3588_CLKGATE_CON(76), 4, GFLAGS),
1588 GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0,
1589 RK3588_CLKGATE_CON(76), 5, GFLAGS),
1590
1591 /* vdec */
1592 COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0,
1593 RK3588_CLKSEL_CON(89), 0, 2, MFLAGS,
1594 RK3588_CLKGATE_CON(40), 0, GFLAGS),
1595 COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0,
1596 RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS,
1597 RK3588_CLKGATE_CON(40), 1, GFLAGS),
1598 COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0,
1599 RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS,
1600 RK3588_CLKGATE_CON(40), 2, GFLAGS),
1601 COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0,
1602 RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS,
1603 RK3588_CLKGATE_CON(40), 7, GFLAGS),
1604 COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0,
1605 RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS,
1606 RK3588_CLKGATE_CON(40), 8, GFLAGS),
1607 COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0,
1608 RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS,
1609 RK3588_CLKGATE_CON(40), 9, GFLAGS),
1610 COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0,
1611 RK3588_CLKSEL_CON(93), 0, 2, MFLAGS,
1612 RK3588_CLKGATE_CON(41), 0, GFLAGS),
1613 COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0,
1614 RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS,
1615 RK3588_CLKGATE_CON(41), 1, GFLAGS),
1616 COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0,
1617 RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS,
1618 RK3588_CLKGATE_CON(41), 6, GFLAGS),
1619 COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0,
1620 RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS,
1621 RK3588_CLKGATE_CON(41), 7, GFLAGS),
1622 COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0,
1623 RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS,
1624 RK3588_CLKGATE_CON(41), 8, GFLAGS),
1625
1626 /* sdio */
1627 COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0,
1628 RK3588_CLKSEL_CON(172), 0, 2, MFLAGS,
1629 RK3588_CLKGATE_CON(75), 0, GFLAGS),
1630 COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0,
1631 RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS,
1632 RK3588_CLKGATE_CON(75), 3, GFLAGS),
1633 MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1),
1634 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1),
1635
1636 /* usb */
1637 COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0,
1638 RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS,
1639 RK3588_CLKGATE_CON(42), 0, GFLAGS),
1640 COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0,
1641 RK3588_CLKSEL_CON(96), 6, 2, MFLAGS,
1642 RK3588_CLKGATE_CON(42), 1, GFLAGS),
1643 GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0,
1644 RK3588_CLKGATE_CON(42), 5, GFLAGS),
1645 GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0,
1646 RK3588_CLKGATE_CON(42), 6, GFLAGS),
1647 GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0,
1648 RK3588_CLKGATE_CON(42), 8, GFLAGS),
1649 GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0,
1650 RK3588_CLKGATE_CON(42), 9, GFLAGS),
1651
1652 /* vdpu */
1653 COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
1654 RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
1655 RK3588_CLKGATE_CON(44), 0, GFLAGS),
1656 COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
1657 RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
1658 RK3588_CLKGATE_CON(44), 1, GFLAGS),
1659 COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
1660 RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
1661 RK3588_CLKGATE_CON(44), 2, GFLAGS),
1662 COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
1663 RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS,
1664 RK3588_CLKGATE_CON(44), 3, GFLAGS),
1665 GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0,
1666 RK3588_CLKGATE_CON(45), 4, GFLAGS),
1667 COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0,
1668 RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS,
1669 RK3588_CLKGATE_CON(45), 6, GFLAGS),
1670 GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0,
1671 RK3588_CLKGATE_CON(44), 11, GFLAGS),
1672 GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0,
1673 RK3588_CLKGATE_CON(44), 13, GFLAGS),
1674 GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0,
1675 RK3588_CLKGATE_CON(44), 15, GFLAGS),
1676 GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0,
1677 RK3588_CLKGATE_CON(45), 1, GFLAGS),
1678 GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0,
1679 RK3588_CLKGATE_CON(45), 3, GFLAGS),
1680 GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0,
1681 RK3588_CLKGATE_CON(45), 7, GFLAGS),
1682 GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0,
1683 RK3588_CLKGATE_CON(45), 8, GFLAGS),
1684 COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0,
1685 RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS,
1686 RK3588_CLKGATE_CON(45), 9, GFLAGS),
1687 GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0,
1688 RK3588_CLKGATE_CON(45), 10, GFLAGS),
1689 GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0,
1690 RK3588_CLKGATE_CON(45), 11, GFLAGS),
1691 COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0,
1692 RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS,
1693 RK3588_CLKGATE_CON(45), 12, GFLAGS),
1694 GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0,
1695 RK3588_CLKGATE_CON(44), 9, GFLAGS),
1696
1697 /* venc */
1698 COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0,
1699 RK3588_CLKSEL_CON(104), 0, 2, MFLAGS,
1700 RK3588_CLKGATE_CON(48), 0, GFLAGS),
1701 COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0,
1702 RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS,
1703 RK3588_CLKGATE_CON(48), 1, GFLAGS),
1704 COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0,
1705 RK3588_CLKSEL_CON(102), 0, 2, MFLAGS,
1706 RK3588_CLKGATE_CON(47), 0, GFLAGS),
1707 COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
1708 RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
1709 RK3588_CLKGATE_CON(47), 1, GFLAGS),
1710 GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
1711 RK3588_CLKGATE_CON(47), 4, GFLAGS),
1712 GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
1713 RK3588_CLKGATE_CON(47), 5, GFLAGS),
1714 COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
1715 RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
1716 RK3588_CLKGATE_CON(47), 6, GFLAGS),
1717 COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0,
1718 RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS,
1719 RK3588_CLKGATE_CON(48), 6, GFLAGS),
1720
1721 /* vi */
1722 COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
1723 RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
1724 RK3588_CLKGATE_CON(49), 0, GFLAGS),
1725 COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
1726 RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
1727 RK3588_CLKGATE_CON(49), 1, GFLAGS),
1728 COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
1729 RK3588_CLKSEL_CON(106), 10, 2, MFLAGS,
1730 RK3588_CLKGATE_CON(49), 2, GFLAGS),
1731 COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0,
1732 RK3588_CLKSEL_CON(108), 14, 2, MFLAGS,
1733 RK3588_CLKGATE_CON(51), 10, GFLAGS),
1734 GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0,
1735 RK3588_CLKGATE_CON(51), 11, GFLAGS),
1736 GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0,
1737 RK3588_CLKGATE_CON(51), 12, GFLAGS),
1738 GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0,
1739 RK3588_CLKGATE_CON(50), 4, GFLAGS),
1740 GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0,
1741 RK3588_CLKGATE_CON(50), 5, GFLAGS),
1742 GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0,
1743 RK3588_CLKGATE_CON(50), 6, GFLAGS),
1744 GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0,
1745 RK3588_CLKGATE_CON(50), 7, GFLAGS),
1746 GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0,
1747 RK3588_CLKGATE_CON(50), 8, GFLAGS),
1748 GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0,
1749 RK3588_CLKGATE_CON(50), 9, GFLAGS),
1750 GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0,
1751 RK3588_CLKGATE_CON(49), 14, GFLAGS),
1752 GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0,
1753 RK3588_CLKGATE_CON(49), 15, GFLAGS),
1754 COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0,
1755 RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS,
1756 RK3588_CLKGATE_CON(50), 0, GFLAGS),
1757 GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0,
1758 RK3588_CLKGATE_CON(50), 1, GFLAGS),
1759 GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0,
1760 RK3588_CLKGATE_CON(50), 2, GFLAGS),
1761 COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0,
1762 RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS,
1763 RK3588_CLKGATE_CON(50), 3, GFLAGS),
1764 COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0,
1765 RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS,
1766 RK3588_CLKGATE_CON(49), 9, GFLAGS),
1767 GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0,
1768 RK3588_CLKGATE_CON(49), 10, GFLAGS),
1769 GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0,
1770 RK3588_CLKGATE_CON(49), 11, GFLAGS),
1771 GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0,
1772 RK3588_CLKGATE_CON(49), 12, GFLAGS),
1773 GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0,
1774 RK3588_CLKGATE_CON(49), 13, GFLAGS),
1775 COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0,
1776 RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS,
1777 RK3588_CLKGATE_CON(49), 6, GFLAGS),
1778 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
1779 RK3588_CLKGATE_CON(49), 7, GFLAGS),
1780 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
1781 RK3588_CLKGATE_CON(49), 8, GFLAGS),
1782
1783 /* vo0 */
1784 COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0,
1785 RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS,
1786 RK3588_CLKGATE_CON(55), 0, GFLAGS),
1787 COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0,
1788 RK3588_CLKSEL_CON(116), 6, 2, MFLAGS,
1789 RK3588_CLKGATE_CON(55), 1, GFLAGS),
1790 COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0,
1791 RK3588_CLKSEL_CON(116), 8, 2, MFLAGS,
1792 RK3588_CLKGATE_CON(55), 2, GFLAGS),
1793 COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0,
1794 RK3588_CLKSEL_CON(116), 10, 2, MFLAGS,
1795 RK3588_CLKGATE_CON(55), 3, GFLAGS),
1796 COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0,
1797 RK3588_CLKSEL_CON(116), 12, 2, MFLAGS,
1798 RK3588_CLKGATE_CON(55), 4, GFLAGS),
1799 GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0,
1800 RK3588_CLKGATE_CON(56), 4, GFLAGS),
1801 GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0,
1802 RK3588_CLKGATE_CON(56), 5, GFLAGS),
1803 GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0,
1804 RK3588_CLKGATE_CON(56), 6, GFLAGS),
1805 GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0,
1806 RK3588_CLKGATE_CON(56), 7, GFLAGS),
1807 GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0,
1808 RK3588_CLKGATE_CON(56), 8, GFLAGS),
1809 GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0,
1810 RK3588_CLKGATE_CON(56), 9, GFLAGS),
1811 GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0,
1812 RK3588_CLKGATE_CON(55), 11, GFLAGS),
1813 GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0,
1814 RK3588_CLKGATE_CON(55), 14, GFLAGS),
1815 GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0,
1816 RK3588_CLKGATE_CON(56), 0, GFLAGS),
1817 GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
1818 RK3588_CLKGATE_CON(56), 1, GFLAGS),
1819 GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
1820 RK3588_CLKGATE_CON(55), 10, GFLAGS),
1821 COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
1822 RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
1823 RK3588_CLKGATE_CON(56), 11, GFLAGS),
1824 COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src", CLK_SET_RATE_PARENT,
1825 RK3588_CLKSEL_CON(119), 0,
1826 RK3588_CLKGATE_CON(56), 12, GFLAGS,
1827 &rk3588_i2s4_8ch_tx_fracmux),
1828 GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0,
1829 RK3588_CLKGATE_CON(56), 13, GFLAGS),
1830 COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0,
1831 RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS,
1832 RK3588_CLKGATE_CON(56), 15, GFLAGS),
1833 COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src", CLK_SET_RATE_PARENT,
1834 RK3588_CLKSEL_CON(121), 0,
1835 RK3588_CLKGATE_CON(57), 0, GFLAGS,
1836 &rk3588_i2s8_8ch_tx_fracmux),
1837 GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0,
1838 RK3588_CLKGATE_CON(57), 1, GFLAGS),
1839 COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0,
1840 RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS,
1841 RK3588_CLKGATE_CON(57), 3, GFLAGS),
1842 COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src", CLK_SET_RATE_PARENT,
1843 RK3588_CLKSEL_CON(123), 0,
1844 RK3588_CLKGATE_CON(57), 4, GFLAGS,
1845 &rk3588_spdif2_dp0_fracmux),
1846 GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0,
1847 RK3588_CLKGATE_CON(57), 5, GFLAGS),
1848 GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0,
1849 RK3588_CLKGATE_CON(57), 6, GFLAGS),
1850 COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0,
1851 RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS,
1852 RK3588_CLKGATE_CON(57), 8, GFLAGS),
1853 COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src", CLK_SET_RATE_PARENT,
1854 RK3588_CLKSEL_CON(125), 0,
1855 RK3588_CLKGATE_CON(57), 9, GFLAGS,
1856 &rk3588_spdif5_dp1_fracmux),
1857 GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0,
1858 RK3588_CLKGATE_CON(57), 10, GFLAGS),
1859 GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0,
1860 RK3588_CLKGATE_CON(57), 11, GFLAGS),
1861 COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0,
1862 RK3588_CLKSEL_CON(117), 0, 8, DFLAGS,
1863 RK3588_CLKGATE_CON(56), 2, GFLAGS),
1864 COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0,
1865 RK3588_CLKSEL_CON(117), 8, 8, DFLAGS,
1866 RK3588_CLKGATE_CON(56), 3, GFLAGS),
1867
1868 /* vo1 */
1869 COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0,
1870 RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS,
1871 RK3588_CLKGATE_CON(65), 9, GFLAGS),
1872 COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0,
1873 RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS,
1874 RK3588_CLKGATE_CON(59), 0, GFLAGS),
1875 COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0,
1876 RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS,
1877 RK3588_CLKGATE_CON(59), 1, GFLAGS),
1878 COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0,
1879 RK3588_CLKSEL_CON(128), 13, 2, MFLAGS,
1880 RK3588_CLKGATE_CON(59), 2, GFLAGS),
1881 COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0,
1882 RK3588_CLKSEL_CON(129), 0, 2, MFLAGS,
1883 RK3588_CLKGATE_CON(59), 3, GFLAGS),
1884 COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0,
1885 RK3588_CLKSEL_CON(129), 2, 2, MFLAGS,
1886 RK3588_CLKGATE_CON(59), 4, GFLAGS),
1887 COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0,
1888 RK3588_CLKSEL_CON(129), 4, 2, MFLAGS,
1889 RK3588_CLKGATE_CON(59), 5, GFLAGS),
1890 COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
1891 RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
1892 RK3588_CLKGATE_CON(52), 0, GFLAGS),
1893 FACTOR(ACLK_VOP_DIV2_SRC, "aclk_vop_div2_src", "aclk_vop_root", 0, 1, 2),
1894 COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
1895 RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
1896 RK3588_CLKGATE_CON(52), 1, GFLAGS),
1897 COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
1898 RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
1899 RK3588_CLKGATE_CON(52), 2, GFLAGS),
1900 COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
1901 RK3588_CLKSEL_CON(110), 12, 2, MFLAGS,
1902 RK3588_CLKGATE_CON(52), 3, GFLAGS),
1903 COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
1904 RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS,
1905 RK3588_CLKGATE_CON(74), 0, GFLAGS),
1906 COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
1907 RK3588_CLKSEL_CON(170), 6, 2, MFLAGS,
1908 RK3588_CLKGATE_CON(74), 2, GFLAGS),
1909 COMPOSITE_NODIV(ACLK_VOP, "aclk_vop", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT,
1910 RK3588_CLKSEL_CON(115), 9, 1, MFLAGS,
1911 RK3588_CLKGATE_CON(52), 9, GFLAGS),
1912 GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0,
1913 RK3588_CLKGATE_CON(62), 0, GFLAGS),
1914 GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,
1915 RK3588_CLKGATE_CON(62), 1, GFLAGS),
1916 COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0,
1917 RK3588_CLKSEL_CON(140), 1, 2, MFLAGS,
1918 RK3588_CLKGATE_CON(62), 2, GFLAGS),
1919 GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0,
1920 RK3588_CLKGATE_CON(62), 3, GFLAGS),
1921 GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0,
1922 RK3588_CLKGATE_CON(62), 4, GFLAGS),
1923 COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0,
1924 RK3588_CLKSEL_CON(140), 3, 2, MFLAGS,
1925 RK3588_CLKGATE_CON(62), 5, GFLAGS),
1926 GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0,
1927 RK3588_CLKGATE_CON(60), 4, GFLAGS),
1928 GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0,
1929 RK3588_CLKGATE_CON(60), 7, GFLAGS),
1930 GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0,
1931 RK3588_CLKGATE_CON(61), 9, GFLAGS),
1932 GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0,
1933 RK3588_CLKGATE_CON(61), 10, GFLAGS),
1934 GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0,
1935 RK3588_CLKGATE_CON(61), 11, GFLAGS),
1936 COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0,
1937 RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS,
1938 RK3588_CLKGATE_CON(61), 12, GFLAGS),
1939 COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src", CLK_SET_RATE_PARENT,
1940 RK3588_CLKSEL_CON(139), 0,
1941 RK3588_CLKGATE_CON(61), 13, GFLAGS,
1942 &rk3588_hdmirx_aud_fracmux),
1943 GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0,
1944 RK3588_CLKGATE_CON(61), 14, GFLAGS),
1945 GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0,
1946 RK3588_CLKGATE_CON(60), 11, GFLAGS),
1947 COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0,
1948 RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS,
1949 RK3588_CLKGATE_CON(60), 15, GFLAGS),
1950 GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0,
1951 RK3588_CLKGATE_CON(61), 0, GFLAGS),
1952 GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0,
1953 RK3588_CLKGATE_CON(61), 2, GFLAGS),
1954 COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0,
1955 RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS,
1956 RK3588_CLKGATE_CON(61), 6, GFLAGS),
1957 GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0,
1958 RK3588_CLKGATE_CON(61), 7, GFLAGS),
1959 GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0,
1960 RK3588_CLKGATE_CON(60), 9, GFLAGS),
1961 GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
1962 RK3588_CLKGATE_CON(60), 10, GFLAGS),
1963 GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
1964 RK3588_CLKGATE_CON(59), 12, GFLAGS),
1965 GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
1966 RK3588_CLKGATE_CON(59), 14, GFLAGS),
1967 GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
1968 RK3588_CLKGATE_CON(59), 15, GFLAGS),
1969 GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0,
1970 RK3588_CLKGATE_CON(65), 8, GFLAGS),
1971 COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0,
1972 RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS,
1973 RK3588_CLKGATE_CON(65), 5, GFLAGS),
1974 COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src", CLK_SET_RATE_PARENT,
1975 RK3588_CLKSEL_CON(156), 0,
1976 RK3588_CLKGATE_CON(65), 6, GFLAGS,
1977 &rk3588_i2s10_8ch_rx_fracmux),
1978 GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0,
1979 RK3588_CLKGATE_CON(65), 7, GFLAGS),
1980 COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0,
1981 RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS,
1982 RK3588_CLKGATE_CON(60), 1, GFLAGS),
1983 COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src", CLK_SET_RATE_PARENT,
1984 RK3588_CLKSEL_CON(130), 0,
1985 RK3588_CLKGATE_CON(60), 2, GFLAGS,
1986 &rk3588_i2s7_8ch_rx_fracmux),
1987 GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0,
1988 RK3588_CLKGATE_CON(60), 3, GFLAGS),
1989 COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0,
1990 RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS,
1991 RK3588_CLKGATE_CON(65), 1, GFLAGS),
1992 COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src", CLK_SET_RATE_PARENT,
1993 RK3588_CLKSEL_CON(154), 0,
1994 RK3588_CLKGATE_CON(65), 2, GFLAGS,
1995 &rk3588_i2s9_8ch_rx_fracmux),
1996 GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0,
1997 RK3588_CLKGATE_CON(65), 3, GFLAGS),
1998 COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, CLK_SET_RATE_NO_REPARENT,
1999 RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS,
2000 RK3588_CLKGATE_CON(62), 6, GFLAGS),
2001 COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", CLK_SET_RATE_PARENT,
2002 RK3588_CLKSEL_CON(141), 0,
2003 RK3588_CLKGATE_CON(62), 7, GFLAGS,
2004 &rk3588_i2s5_8ch_tx_fracmux),
2005 GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0,
2006 RK3588_CLKGATE_CON(62), 8, GFLAGS),
2007 COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, CLK_SET_RATE_NO_REPARENT,
2008 RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS,
2009 RK3588_CLKGATE_CON(62), 13, GFLAGS),
2010 COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", CLK_SET_RATE_PARENT,
2011 RK3588_CLKSEL_CON(145), 0,
2012 RK3588_CLKGATE_CON(62), 14, GFLAGS,
2013 &rk3588_i2s6_8ch_tx_fracmux),
2014 GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0,
2015 RK3588_CLKGATE_CON(62), 15, GFLAGS),
2016 COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0,
2017 RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS,
2018 RK3588_CLKGATE_CON(63), 0, GFLAGS),
2019 COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", CLK_SET_RATE_PARENT,
2020 RK3588_CLKSEL_CON(147), 0,
2021 RK3588_CLKGATE_CON(63), 1, GFLAGS,
2022 &rk3588_i2s6_8ch_rx_fracmux),
2023 GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0,
2024 RK3588_CLKGATE_CON(63), 2, GFLAGS),
2025 MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT,
2026 RK3588_CLKSEL_CON(148), 2, 2, MFLAGS),
2027 COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0,
2028 RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS,
2029 RK3588_CLKGATE_CON(63), 5, GFLAGS),
2030 COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src", CLK_SET_RATE_PARENT,
2031 RK3588_CLKSEL_CON(149), 0,
2032 RK3588_CLKGATE_CON(63), 6, GFLAGS,
2033 &rk3588_spdif3_fracmux),
2034 GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0,
2035 RK3588_CLKGATE_CON(63), 7, GFLAGS),
2036 COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0,
2037 RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS,
2038 RK3588_CLKGATE_CON(63), 9, GFLAGS),
2039 COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src", CLK_SET_RATE_PARENT,
2040 RK3588_CLKSEL_CON(151), 0,
2041 RK3588_CLKGATE_CON(63), 10, GFLAGS,
2042 &rk3588_spdif4_fracmux),
2043 GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0,
2044 RK3588_CLKGATE_CON(63), 11, GFLAGS),
2045 COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0,
2046 RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS,
2047 RK3588_CLKGATE_CON(63), 13, GFLAGS),
2048 COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0,
2049 RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS,
2050 RK3588_CLKGATE_CON(63), 15, GFLAGS),
2051 COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0,
2052 RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS,
2053 RK3588_CLKGATE_CON(64), 1, GFLAGS),
2054 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
2055 RK3588_CLKGATE_CON(73), 12, GFLAGS),
2056 GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0,
2057 RK3588_CLKGATE_CON(73), 13, GFLAGS),
2058 GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0,
2059 RK3588_CLKGATE_CON(72), 5, GFLAGS),
2060 GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0,
2061 RK3588_CLKGATE_CON(72), 6, GFLAGS),
2062 GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0,
2063 RK3588_CLKGATE_CON(72), 2, GFLAGS),
2064 GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0,
2065 RK3588_CLKGATE_CON(72), 4, GFLAGS),
2066 GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0,
2067 RK3588_CLKGATE_CON(52), 8, GFLAGS),
2068 COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0,
2069 RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS,
2070 RK3588_CLKGATE_CON(52), 10, GFLAGS),
2071 COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0,
2072 RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS,
2073 RK3588_CLKGATE_CON(52), 11, GFLAGS),
2074 COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
2075 RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS,
2076 RK3588_CLKGATE_CON(52), 12, GFLAGS),
2077 COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
2078 RK3588_CLKSEL_CON(112), 7, 2, MFLAGS,
2079 RK3588_CLKGATE_CON(52), 13, GFLAGS),
2080 COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
2081 RK3588_CLKSEL_CON(112), 9, 2, MFLAGS,
2082 RK3588_CLKGATE_CON(53), 0, GFLAGS),
2083 COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
2084 RK3588_CLKSEL_CON(112), 11, 2, MFLAGS,
2085 RK3588_CLKGATE_CON(53), 1, GFLAGS),
2086 COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0,
2087 RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS,
2088 RK3588_CLKGATE_CON(53), 2, GFLAGS),
2089 GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0,
2090 RK3588_CLKGATE_CON(53), 4, GFLAGS),
2091 GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0,
2092 RK3588_CLKGATE_CON(53), 5, GFLAGS),
2093 COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0,
2094 RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS,
2095 RK3588_CLKGATE_CON(53), 6, GFLAGS),
2096 COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0,
2097 RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS,
2098 RK3588_CLKGATE_CON(53), 7, GFLAGS),
2099 GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED,
2100 RK3588_CLKGATE_CON(53), 8, GFLAGS),
2101 GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0,
2102 RK3588_CLKGATE_CON(53), 10, GFLAGS),
2103 GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED,
2104 RK3588_CLKGATE_CON(2), 8, GFLAGS),
2105 GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED,
2106 RK3588_CLKGATE_CON(2), 15, GFLAGS),
2107
2108 GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0,
2109 RK3588_CLKGATE_CON(77), 0, GFLAGS),
2110 GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0,
2111 RK3588_CLKGATE_CON(77), 1, GFLAGS),
2112 GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0,
2113 RK3588_CLKGATE_CON(77), 2, GFLAGS),
2114 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0,
2115 RK3588_CLKSEL_CON(176), 0, 6, DFLAGS,
2116 RK3588_CLKGATE_CON(77), 3, GFLAGS),
2117 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0,
2118 RK3588_CLKSEL_CON(176), 6, 6, DFLAGS,
2119 RK3588_CLKGATE_CON(77), 4, GFLAGS),
2120 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0,
2121 RK3588_CLKSEL_CON(177), 0, 6, DFLAGS,
2122 RK3588_CLKGATE_CON(77), 5, GFLAGS),
2123 MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT,
2124 RK3588_CLKSEL_CON(177), 6, 1, MFLAGS),
2125 MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT,
2126 RK3588_CLKSEL_CON(177), 7, 1, MFLAGS),
2127 MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT,
2128 RK3588_CLKSEL_CON(177), 8, 1, MFLAGS),
2129
2130 /* pmu */
2131 COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0,
2132 RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS,
2133 RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS),
2134 COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0,
2135 RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
2136 RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS),
2137 COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0,
2138 RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS,
2139 RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS),
2140 COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0,
2141 RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS,
2142 RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS),
2143 COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0,
2144 RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS,
2145 RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS),
2146 COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL,
2147 RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS,
2148 RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS),
2149 COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL,
2150 RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS,
2151 RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS),
2152 GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL,
2153 RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS),
2154 COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL,
2155 RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS,
2156 RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS),
2157 GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL,
2158 RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS),
2159 GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL,
2160 RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS),
2161 GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL,
2162 RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS),
2163 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0,
2164 RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS),
2165 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0,
2166 RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS,
2167 RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS),
2168 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0,
2169 RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS),
2170 COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0,
2171 RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS,
2172 RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS),
2173 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0,
2174 RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS),
2175 COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0,
2176 RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS,
2177 RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS),
2178 COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
2179 RK3588_PMU_CLKSEL_CON(6), 0,
2180 RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS,
2181 &rk3588_i2s1_8ch_tx_fracmux),
2182 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
2183 RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS),
2184 COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0,
2185 RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS,
2186 RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS),
2187 COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
2188 RK3588_PMU_CLKSEL_CON(8), 0,
2189 RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS,
2190 &rk3588_i2s1_8ch_rx_fracmux),
2191 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
2192 RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS),
2193 MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT,
2194 RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS),
2195 GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL,
2196 RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS),
2197 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED,
2198 RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS),
2199 GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL,
2200 RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS),
2201 GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0,
2202 RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS),
2203 COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0,
2204 RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS,
2205 RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS),
2206 GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0,
2207 RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS),
2208 GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL,
2209 RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS),
2210 COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL,
2211 RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
2212 RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS),
2213 GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED,
2214 RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS),
2215 GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0,
2216 RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS),
2217 COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0,
2218 RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS,
2219 RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS),
2220 GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0,
2221 RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS),
2222 GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0,
2223 RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS),
2224 COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0,
2225 RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS,
2226 RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS),
2227 GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0,
2228 RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS),
2229 GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0,
2230 RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS),
2231 COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0,
2232 RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS,
2233 RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS),
2234 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
2235 RK3588_PMU_CLKSEL_CON(4), CLK_FRAC_DIVIDER_NO_LIMIT,
2236 RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS,
2237 &rk3588_uart0_fracmux),
2238 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
2239 RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS),
2240 GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0,
2241 RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS),
2242 GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0,
2243 RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS),
2244 COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0,
2245 RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
2246 RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS),
2247 COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0,
2248 RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS,
2249 RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS),
2250 COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p, CLK_IS_CRITICAL,
2251 RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS,
2252 RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS),
2253 COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p, CLK_IS_CRITICAL,
2254 RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS,
2255 RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS),
2256
2257 GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0,
2258 RK3588_PHYREF_ALT_GATE, 0, GFLAGS),
2259 GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0,
2260 RK3588_PHYREF_ALT_GATE, 1, GFLAGS),
2261 GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0,
2262 RK3588_PHYREF_ALT_GATE, 2, GFLAGS),
2263 GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0,
2264 RK3588_PHYREF_ALT_GATE, 3, GFLAGS),
2265
2266 GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0,
2267 RK3588_CLKGATE_CON(63), 12, GFLAGS),
2268 GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0,
2269 RK3588_CLKGATE_CON(63), 14, GFLAGS),
2270 GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0,
2271 RK3588_CLKGATE_CON(64), 0, GFLAGS),
2272 GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0,
2273 RK3588_CLKGATE_CON(63), 8, GFLAGS),
2274 GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0,
2275 RK3588_CLKGATE_CON(63), 4, GFLAGS),
2276 GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0,
2277 RK3588_CLKGATE_CON(63), 3, GFLAGS),
2278 GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0,
2279 RK3588_CLKGATE_CON(62), 12, GFLAGS),
2280 GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0,
2281 RK3588_CLKGATE_CON(65), 0, GFLAGS),
2282 GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0,
2283 RK3588_CLKGATE_CON(60), 0, GFLAGS),
2284 GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0,
2285 RK3588_CLKGATE_CON(65), 4, GFLAGS),
2286 GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0,
2287 RK3588_CLKGATE_CON(60), 5, GFLAGS),
2288 GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0,
2289 RK3588_CLKGATE_CON(60), 6, GFLAGS),
2290 GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0,
2291 RK3588_CLKGATE_CON(57), 7, GFLAGS),
2292 GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0,
2293 RK3588_CLKGATE_CON(57), 2, GFLAGS),
2294 GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0,
2295 RK3588_CLKGATE_CON(56), 14, GFLAGS),
2296 GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0,
2297 RK3588_CLKGATE_CON(56), 10, GFLAGS),
2298 GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0,
2299 RK3588_CLKGATE_CON(55), 12, GFLAGS),
2300 GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0,
2301 RK3588_CLKGATE_CON(55), 13, GFLAGS),
2302 GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0,
2303 RK3588_CLKGATE_CON(48), 4, GFLAGS),
2304 GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0,
2305 RK3588_CLKGATE_CON(48), 5, GFLAGS),
2306 GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0,
2307 RK3588_CLKGATE_CON(44), 8, GFLAGS),
2308 GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0,
2309 RK3588_CLKGATE_CON(45), 5, GFLAGS),
2310 GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0,
2311 RK3588_CLKGATE_CON(44), 10, GFLAGS),
2312 GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0,
2313 RK3588_CLKGATE_CON(44), 12, GFLAGS),
2314 GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0,
2315 RK3588_CLKGATE_CON(44), 14, GFLAGS),
2316 GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0,
2317 RK3588_CLKGATE_CON(45), 0, GFLAGS),
2318 GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0,
2319 RK3588_CLKGATE_CON(45), 2, GFLAGS),
2320 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0,
2321 RK3588_CLKGATE_CON(42), 7, GFLAGS),
2322 GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0,
2323 RK3588_CLKGATE_CON(42), 10, GFLAGS),
2324 GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0,
2325 RK3588_CLKGATE_CON(42), 11, GFLAGS),
2326 GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0,
2327 RK3588_CLKGATE_CON(42), 12, GFLAGS),
2328 GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0,
2329 RK3588_CLKGATE_CON(42), 13, GFLAGS),
2330 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0,
2331 RK3588_CLKGATE_CON(42), 4, GFLAGS),
2332 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1),
2333 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1),
2334 GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0,
2335 RK3588_CLKGATE_CON(75), 2, GFLAGS),
2336 GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0,
2337 RK3588_CLKGATE_CON(41), 2, GFLAGS),
2338 GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0,
2339 RK3588_CLKGATE_CON(41), 3, GFLAGS),
2340 GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0,
2341 RK3588_CLKGATE_CON(40), 3, GFLAGS),
2342 GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0,
2343 RK3588_CLKGATE_CON(40), 4, GFLAGS),
2344 GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0,
2345 RK3588_CLKGATE_CON(39), 0, GFLAGS),
2346 GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0,
2347 RK3588_CLKGATE_CON(39), 1, GFLAGS),
2348 GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0,
2349 RK3588_CLKGATE_CON(38), 3, GFLAGS),
2350 GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0,
2351 RK3588_CLKGATE_CON(38), 4, GFLAGS),
2352 GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0,
2353 RK3588_CLKGATE_CON(38), 5, GFLAGS),
2354 GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0,
2355 RK3588_CLKGATE_CON(38), 6, GFLAGS),
2356 GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0,
2357 RK3588_CLKGATE_CON(38), 7, GFLAGS),
2358 GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0,
2359 RK3588_CLKGATE_CON(38), 8, GFLAGS),
2360 GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0,
2361 RK3588_CLKGATE_CON(38), 9, GFLAGS),
2362 GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0,
2363 RK3588_CLKGATE_CON(38), 13, GFLAGS),
2364 GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0,
2365 RK3588_CLKGATE_CON(38), 14, GFLAGS),
2366 GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0,
2367 RK3588_CLKGATE_CON(38), 15, GFLAGS),
2368 GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0,
2369 RK3588_CLKGATE_CON(31), 10, GFLAGS),
2370 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0,
2371 RK3588_CLKGATE_CON(31), 11, GFLAGS),
2372 GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0,
2373 RK3588_CLKGATE_CON(31), 4, GFLAGS),
2374 GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0,
2375 RK3588_CLKGATE_CON(26), 5, GFLAGS),
2376 GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0,
2377 RK3588_CLKGATE_CON(26), 7, GFLAGS),
2378 GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0,
2379 RK3588_CLKGATE_CON(68), 5, GFLAGS),
2380 GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
2381 RK3588_CLKGATE_CON(68), 2, GFLAGS),
2382 };
2383
2384 static void __iomem *rk3588_cru_base;
2385
dump_offset(const char * name,u32 offset,u32 len)2386 static void dump_offset(const char *name, u32 offset, u32 len)
2387 {
2388 int i = 0, cnt = 0;
2389
2390 if (!offset)
2391 return;
2392
2393 cnt = DIV_ROUND_UP(len, 32);
2394 for (i = 0; i < cnt; i++) {
2395 pr_warn("%-12s 0x%05x: ", name, offset + i * 32);
2396 print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 32, 4,
2397 rk3588_cru_base + offset + i * 0x10, 32, false);
2398 }
2399 }
2400
rk3588_dump_cru(void)2401 static void rk3588_dump_cru(void)
2402 {
2403 if (rk3588_cru_base) {
2404 pr_warn("CRU REGS:\n");
2405 dump_offset("LPLL", RK3588_LPLL_CON(16), 0x10);
2406 dump_offset("B0PLL", RK3588_B0_PLL_CON(0), 0x10);
2407 dump_offset("B1PLL", RK3588_B1_PLL_CON(8), 0x10);
2408 dump_offset("GPLL", RK3588_PLL_CON(112), 0x10);
2409 dump_offset("CPLL", RK3588_PLL_CON(104), 0x10);
2410 dump_offset("V0PLL", RK3588_PLL_CON(88), 0x10);
2411 dump_offset("AUPLL", RK3588_PLL_CON(96), 0x10);
2412 dump_offset("PPLL", RK3588_PMU_PLL_CON(128), 0x10);
2413 dump_offset("DSUCRU_SEL", RK3588_DSU_CLKSEL_CON(0), 0x20);
2414 dump_offset("DSUCRU_GATE", RK3588_DSU_CLKGATE_CON(0), 0x10);
2415 dump_offset("BIG0CRU_SEL", RK3588_BIGCORE0_CLKSEL_CON(0), 0x10);
2416 dump_offset("BIG0CRU_GATE", RK3588_BIGCORE0_CLKGATE_CON(0), 0x10);
2417 dump_offset("BIG1CRU_SEL", RK3588_BIGCORE1_CLKSEL_CON(0), 0x10);
2418 dump_offset("BIG1CRU_GATE", RK3588_BIGCORE1_CLKGATE_CON(0), 0x10);
2419 dump_offset("CRU_SEL", RK3588_CLKSEL_CON(0), 0x2d0);
2420 dump_offset("CRU_GATE", RK3588_CLKGATE_CON(0), 0x140);
2421 dump_offset("PMUCRU_SEL", RK3588_PMU_CLKSEL_CON(0), 0x50);
2422 dump_offset("PMUCRU_GATE", RK3588_PMU_CLKGATE_CON(0), 0x20);
2423 }
2424 }
2425
rk3588_clk_init(struct device_node * np)2426 static void __init rk3588_clk_init(struct device_node *np)
2427 {
2428 struct rockchip_clk_provider *ctx;
2429 void __iomem *reg_base;
2430 struct clk **clks;
2431
2432 reg_base = of_iomap(np, 0);
2433 if (!reg_base) {
2434 pr_err("%s: could not map cru region\n", __func__);
2435 return;
2436 }
2437
2438 rk3588_cru_base = reg_base;
2439
2440 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
2441 if (IS_ERR(ctx)) {
2442 pr_err("%s: rockchip clk init failed\n", __func__);
2443 iounmap(reg_base);
2444 return;
2445 }
2446 clks = ctx->clk_data.clks;
2447
2448 rockchip_clk_register_plls(ctx, rk3588_pll_clks,
2449 ARRAY_SIZE(rk3588_pll_clks),
2450 RK3588_GRF_SOC_STATUS0);
2451
2452 rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l",
2453 3, clks[PLL_LPLL], clks[PLL_GPLL],
2454 &rk3588_cpulclk_data, rk3588_cpulclk_rates,
2455 ARRAY_SIZE(rk3588_cpulclk_rates));
2456 rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01",
2457 3, clks[PLL_B0PLL], clks[PLL_GPLL],
2458 &rk3588_cpub0clk_data, rk3588_cpub0clk_rates,
2459 ARRAY_SIZE(rk3588_cpub0clk_rates));
2460 rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23",
2461 3, clks[PLL_B1PLL], clks[PLL_GPLL],
2462 &rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
2463 ARRAY_SIZE(rk3588_cpub1clk_rates));
2464
2465 rockchip_clk_register_branches(ctx, rk3588_clk_branches,
2466 ARRAY_SIZE(rk3588_clk_branches));
2467
2468 rockchip_register_softrst(np, 49158, reg_base + RK3588_SOFTRST_CON(0),
2469 ROCKCHIP_SOFTRST_HIWORD_MASK);
2470
2471 rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL);
2472
2473 rockchip_clk_of_add_provider(np, ctx);
2474
2475 if (!rk_dump_cru)
2476 rk_dump_cru = rk3588_dump_cru;
2477 }
2478
2479 CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
2480
2481 #ifdef MODULE
2482 struct clk_rk3588_inits {
2483 void (*inits)(struct device_node *np);
2484 };
2485
2486 static const struct clk_rk3588_inits clk_3588_cru_init = {
2487 .inits = rk3588_clk_init,
2488 };
2489
2490 static const struct of_device_id clk_rk3588_match_table[] = {
2491 {
2492 .compatible = "rockchip,rk3588-cru",
2493 .data = &clk_3588_cru_init,
2494 },
2495 { }
2496 };
2497 MODULE_DEVICE_TABLE(of, clk_rk3588_match_table);
2498
clk_rk3588_probe(struct platform_device * pdev)2499 static int clk_rk3588_probe(struct platform_device *pdev)
2500 {
2501 struct device_node *np = pdev->dev.of_node;
2502 const struct of_device_id *match;
2503 const struct clk_rk3588_inits *init_data;
2504
2505 match = of_match_device(clk_rk3588_match_table, &pdev->dev);
2506 if (!match || !match->data)
2507 return -EINVAL;
2508
2509 init_data = match->data;
2510 if (init_data->inits)
2511 init_data->inits(np);
2512
2513 return 0;
2514 }
2515
2516 static struct platform_driver clk_rk3588_driver = {
2517 .probe = clk_rk3588_probe,
2518 .driver = {
2519 .name = "clk-rk3588",
2520 .of_match_table = clk_rk3588_match_table,
2521 .suppress_bind_attrs = true,
2522 },
2523 };
2524 module_platform_driver(clk_rk3588_driver);
2525
2526 MODULE_DESCRIPTION("Rockchip RK3588 Clock Driver");
2527 MODULE_LICENSE("GPL");
2528 #endif /* MODULE */
2529