clk/rockchip/clk-rk3288.c

197 PNAME(mux_pll_p)		= { "xin24m", "xin32k" };
207 PNAME(mux_mmc_src_p)	= { "cpll", "gpll", "xin24m", "xin24m" };
212 PNAME(mux_uart0_p)	= { "uart0_src", "uart0_frac", "xin24m" };
213 PNAME(mux_uart1_p)	= { "uart1_src", "uart1_frac", "xin24m" };
214 PNAME(mux_uart2_p)	= { "uart2_src", "uart2_frac", "xin24m" };
215 PNAME(mux_uart3_p)	= { "uart3_src", "uart3_frac", "xin24m" };
216 PNAME(mux_uart4_p)	= { "uart4_src", "uart4_frac", "xin24m" };
217 PNAME(mux_vip_out_p)	= { "vip_src", "xin24m" };
220 PNAME(mux_edp_24m_p)	= { "ext_edp_24m", "xin24m" };
226 			     "xin24m", "xin27m", "xin32k", "clk_wifi",
371 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
407 	GATE(0, "sclk_acc_efuse", "xin24m", 0,
410 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
412 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
414 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
416 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
418 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
420 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
479 	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
571 	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
573 	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
575 	GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,
590 	COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
594 	GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
771 	GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
772 	GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
773 	GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
774 	GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
775 	GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),