1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4 * Author: Joseph Chen <chenjh@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/of_address.h>
12 #include <linux/syscore_ops.h>
13 #include <dt-bindings/clock/rk3528-cru.h>
14 #include "clk.h"
15
16 /* A placeholder for rk3066 pll type. We are rk3328 pll type */
17 #define RK3528_GRF_SOC_STATUS0 0x1a0
18
19 enum rk3528_plls {
20 apll, cpll, gpll, ppll, dpll,
21 };
22
23 /*
24 * ## PLL attention.
25 *
26 * [FRAC PLL]: GPLL, PPLL, DPLL
27 * - frac mode: refdiv can be 1 or 2 only
28 * - int mode: refdiv has no special limit
29 * - VCO range: [950, 3800] MHZ
30 *
31 * [INT PLL]: CPLL, APLL
32 * - int mode: refdiv can be 1 or 2 only
33 * - VCO range: [475, 1900] MHZ
34 *
35 * [PPLL]: normal mode only.
36 *
37 *
38 * ## CRU access attention.
39 *
40 * pclk_cru => pclk_vo_root => aclk_vo_root
41 * pclk_cru_pcie => pclk_vpu_root => aclk_vpu_root
42 * pclk_cru_ddrphy => hclk_rkvdec_root => aclk_rkvdec_root
43 */
44 static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
45 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
46 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
55 RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
58 RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */
59 RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
60 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
61 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
62 RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
63 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
64 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
65 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
66 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
67 RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
68 { /* sentinel */ },
69 };
70
71 #define RK3528_DIV_ACLK_M_CORE_MASK 0x1f
72 #define RK3528_DIV_ACLK_M_CORE_SHIFT 11
73 #define RK3528_DIV_PCLK_DBG_MASK 0x1f
74 #define RK3528_DIV_PCLK_DBG_SHIFT 1
75
76 #define RK3528_CLKSEL39(_aclk_m_core) \
77 { \
78 .reg = RK3528_CLKSEL_CON(39), \
79 .val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \
80 RK3528_DIV_ACLK_M_CORE_SHIFT), \
81 }
82
83 #define RK3528_CLKSEL40(_pclk_dbg) \
84 { \
85 .reg = RK3528_CLKSEL_CON(40), \
86 .val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \
87 RK3528_DIV_PCLK_DBG_SHIFT), \
88 }
89
90 /* SIGN-OFF: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */
91 #define RK3528_CPUCLK_RATE(_prate, _aclk_m_core, _pclk_dbg) \
92 { \
93 .prate = _prate, \
94 .divs = { \
95 RK3528_CLKSEL39(_aclk_m_core), \
96 RK3528_CLKSEL40(_pclk_dbg), \
97 }, \
98 }
99
100 static struct rockchip_cpuclk_rate_table rk3528_cpuclk_rates[] __initdata = {
101 /* APLL(CPU) rate <= 1900M, due to APLL VCO limit */
102 RK3528_CPUCLK_RATE(1896000000, 1, 13),
103 RK3528_CPUCLK_RATE(1800000000, 1, 12),
104 RK3528_CPUCLK_RATE(1704000000, 1, 11),
105 RK3528_CPUCLK_RATE(1608000000, 1, 11),
106 RK3528_CPUCLK_RATE(1512000000, 1, 11),
107 RK3528_CPUCLK_RATE(1416000000, 1, 9),
108 RK3528_CPUCLK_RATE(1296000000, 1, 8),
109 RK3528_CPUCLK_RATE(1200000000, 1, 8),
110 RK3528_CPUCLK_RATE(1188000000, 1, 8),
111 RK3528_CPUCLK_RATE(1092000000, 1, 7),
112 RK3528_CPUCLK_RATE(1008000000, 1, 6),
113 RK3528_CPUCLK_RATE(1000000000, 1, 6),
114 RK3528_CPUCLK_RATE(996000000, 1, 6),
115 RK3528_CPUCLK_RATE(960000000, 1, 6),
116 RK3528_CPUCLK_RATE(912000000, 1, 6),
117 RK3528_CPUCLK_RATE(816000000, 1, 5),
118 RK3528_CPUCLK_RATE(600000000, 1, 3),
119 RK3528_CPUCLK_RATE(594000000, 1, 3),
120 RK3528_CPUCLK_RATE(408000000, 1, 2),
121 RK3528_CPUCLK_RATE(312000000, 1, 2),
122 RK3528_CPUCLK_RATE(216000000, 1, 1),
123 RK3528_CPUCLK_RATE(96000000, 1, 0),
124 };
125
126 static const struct rockchip_cpuclk_reg_data rk3528_cpuclk_data = {
127 .core_reg[0] = RK3528_CLKSEL_CON(39),
128 .div_core_shift[0] = 5,
129 .div_core_mask[0] = 0x1f,
130 .num_cores = 1,
131 .mux_core_alt = 1,
132 .mux_core_main = 0,
133 .mux_core_shift = 10,
134 .mux_core_mask = 0x1,
135 };
136
137 PNAME(mux_pll_p) = { "xin24m" };
138 PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
139 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
140 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
141 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
142 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" };
143 PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src", "xin24m" };
144 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
145 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
146 PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
147 PNAME(mux_500m_200m_100m_24m_p) = { "clk_500m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
148 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
149 PNAME(mux_600m_300m_200m_24m_p) = { "clk_600m_src", "clk_300m_src", "clk_200m_src", "xin24m" };
150 PNAME(aclk_gpu_p) = { "aclk_gpu_root", "clk_gpu_pvtpll_src" };
151 PNAME(aclk_rkvdec_pvtmux_root_p) = { "aclk_rkvdec_root", "clk_rkvdec_pvtpll_src" };
152 PNAME(clk_i2c2_p) = { "clk_200m_src", "clk_100m_src", "xin24m", "clk_32k" };
153 PNAME(clk_ref_pcie_inner_phy_p) = { "clk_ppll_100m_src", "xin24m" };
154 PNAME(dclk_vop0_p) = { "dclk_vop_src0", "clk_hdmiphy_pixel_io" };
155 PNAME(mclk_i2s0_2ch_sai_src_p) = { "clk_i2s0_2ch_src", "clk_i2s0_2ch_frac", "xin12m" };
156 PNAME(mclk_i2s1_8ch_sai_src_p) = { "clk_i2s1_8ch_src", "clk_i2s1_8ch_frac", "xin12m" };
157 PNAME(mclk_i2s2_2ch_sai_src_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "xin12m" };
158 PNAME(mclk_i2s3_8ch_sai_src_p) = { "clk_i2s3_8ch_src", "clk_i2s3_8ch_frac", "xin12m" };
159 PNAME(mclk_sai_i2s0_p) = { "mclk_i2s0_2ch_sai_src", "i2s0_mclkin" };
160 PNAME(mclk_sai_i2s1_p) = { "mclk_i2s1_8ch_sai_src", "i2s1_mclkin" };
161 PNAME(mclk_spdif_src_p) = { "clk_spdif_src", "clk_spdif_frac", "xin12m" };
162 PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
163 PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
164 PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
165 PNAME(sclk_uart3_src_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
166 PNAME(sclk_uart4_src_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
167 PNAME(sclk_uart5_src_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
168 PNAME(sclk_uart6_src_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
169 PNAME(sclk_uart7_src_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
170 PNAME(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" };
171
172 /* Pass 0 to PLL() '_lshift' as a placeholder for rk3066 pll type. We are rk3328 pll type */
173 static struct rockchip_pll_clock rk3528_pll_clks[] __initdata = {
174 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
175 CLK_IS_CRITICAL, RK3528_PLL_CON(0),
176 RK3528_MODE_CON, 0, 0, 0, rk3528_pll_rates),
177
178 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
179 CLK_IS_CRITICAL, RK3528_PLL_CON(8),
180 RK3528_MODE_CON, 2, 0, 0, rk3528_pll_rates),
181
182 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
183 CLK_IS_CRITICAL, RK3528_PLL_CON(24),
184 RK3528_MODE_CON, 4, 0, 0, rk3528_pll_rates),
185
186 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
187 CLK_IS_CRITICAL, RK3528_PCIE_PLL_CON(32),
188 RK3528_MODE_CON, 6, 0,
189 ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates),
190
191 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
192 CLK_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16),
193 RK3528_DDRPHY_MODE_CON, 0, 0, 0, rk3528_pll_rates),
194 };
195
196 #define MFLAGS CLK_MUX_HIWORD_MASK
197 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
198 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
199
200 static struct rockchip_clk_branch rk3528_uart0_fracmux __initdata =
201 MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
202 RK3528_CLKSEL_CON(6), 0, 2, MFLAGS);
203
204 static struct rockchip_clk_branch rk3528_uart1_fracmux __initdata =
205 MUX(CLK_UART1, "clk_uart1", sclk_uart1_src_p, CLK_SET_RATE_PARENT,
206 RK3528_CLKSEL_CON(8), 0, 2, MFLAGS);
207
208 static struct rockchip_clk_branch rk3528_uart2_fracmux __initdata =
209 MUX(CLK_UART2, "clk_uart2", sclk_uart2_src_p, CLK_SET_RATE_PARENT,
210 RK3528_CLKSEL_CON(10), 0, 2, MFLAGS);
211
212 static struct rockchip_clk_branch rk3528_uart3_fracmux __initdata =
213 MUX(CLK_UART3, "clk_uart3", sclk_uart3_src_p, CLK_SET_RATE_PARENT,
214 RK3528_CLKSEL_CON(12), 0, 2, MFLAGS);
215
216 static struct rockchip_clk_branch rk3528_uart4_fracmux __initdata =
217 MUX(CLK_UART4, "clk_uart4", sclk_uart4_src_p, CLK_SET_RATE_PARENT,
218 RK3528_CLKSEL_CON(14), 0, 2, MFLAGS);
219
220 static struct rockchip_clk_branch rk3528_uart5_fracmux __initdata =
221 MUX(CLK_UART5, "clk_uart5", sclk_uart5_src_p, CLK_SET_RATE_PARENT,
222 RK3528_CLKSEL_CON(16), 0, 2, MFLAGS);
223
224 static struct rockchip_clk_branch rk3528_uart6_fracmux __initdata =
225 MUX(CLK_UART6, "clk_uart6", sclk_uart6_src_p, CLK_SET_RATE_PARENT,
226 RK3528_CLKSEL_CON(18), 0, 2, MFLAGS);
227
228 static struct rockchip_clk_branch rk3528_uart7_fracmux __initdata =
229 MUX(CLK_UART7, "clk_uart7", sclk_uart7_src_p, CLK_SET_RATE_PARENT,
230 RK3528_CLKSEL_CON(20), 0, 2, MFLAGS);
231
232 static struct rockchip_clk_branch mclk_i2s0_2ch_sai_src_fracmux __initdata =
233 MUX(MCLK_I2S0_2CH_SAI_SRC_PRE, "mclk_i2s0_2ch_sai_src_pre", mclk_i2s0_2ch_sai_src_p, CLK_SET_RATE_PARENT,
234 RK3528_CLKSEL_CON(22), 0, 2, MFLAGS);
235
236 static struct rockchip_clk_branch mclk_i2s1_8ch_sai_src_fracmux __initdata =
237 MUX(MCLK_I2S1_8CH_SAI_SRC_PRE, "mclk_i2s1_8ch_sai_src_pre", mclk_i2s1_8ch_sai_src_p, CLK_SET_RATE_PARENT,
238 RK3528_CLKSEL_CON(26), 0, 2, MFLAGS);
239
240 static struct rockchip_clk_branch mclk_i2s2_2ch_sai_src_fracmux __initdata =
241 MUX(MCLK_I2S2_2CH_SAI_SRC_PRE, "mclk_i2s2_2ch_sai_src_pre", mclk_i2s2_2ch_sai_src_p, CLK_SET_RATE_PARENT,
242 RK3528_CLKSEL_CON(28), 0, 2, MFLAGS);
243
244 static struct rockchip_clk_branch mclk_i2s3_8ch_sai_src_fracmux __initdata =
245 MUX(MCLK_I2S3_8CH_SAI_SRC_PRE, "mclk_i2s3_8ch_sai_src_pre", mclk_i2s3_8ch_sai_src_p, CLK_SET_RATE_PARENT,
246 RK3528_CLKSEL_CON(24), 0, 2, MFLAGS);
247
248 static struct rockchip_clk_branch mclk_spdif_src_fracmux __initdata =
249 MUX(MCLK_SDPDIF_SRC_PRE, "mclk_spdif_src_pre", mclk_spdif_src_p, CLK_SET_RATE_PARENT,
250 RK3528_CLKSEL_CON(32), 0, 2, MFLAGS);
251
252 /*
253 * CRU Clock-Architecture
254 */
255 static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = {
256 /* top */
257 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
258
259 COMPOSITE(CLK_MATRIX_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
260 RK3528_CLKSEL_CON(1), 15, 1, MFLAGS, 10, 5, DFLAGS,
261 RK3528_CLKGATE_CON(0), 5, GFLAGS),
262 COMPOSITE(CLK_MATRIX_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
263 RK3528_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
264 RK3528_CLKGATE_CON(0), 10, GFLAGS),
265 COMPOSITE_NOMUX(CLK_MATRIX_50M_SRC, "clk_50m_src", "cpll", CLK_IS_CRITICAL,
266 RK3528_CLKSEL_CON(0), 2, 5, DFLAGS,
267 RK3528_CLKGATE_CON(0), 1, GFLAGS),
268 COMPOSITE_NOMUX(CLK_MATRIX_100M_SRC, "clk_100m_src", "cpll", CLK_IS_CRITICAL,
269 RK3528_CLKSEL_CON(0), 7, 5, DFLAGS,
270 RK3528_CLKGATE_CON(0), 2, GFLAGS),
271 COMPOSITE_NOMUX(CLK_MATRIX_150M_SRC, "clk_150m_src", "gpll", CLK_IS_CRITICAL,
272 RK3528_CLKSEL_CON(1), 0, 5, DFLAGS,
273 RK3528_CLKGATE_CON(0), 3, GFLAGS),
274 COMPOSITE_NOMUX(CLK_MATRIX_200M_SRC, "clk_200m_src", "gpll", CLK_IS_CRITICAL,
275 RK3528_CLKSEL_CON(1), 5, 5, DFLAGS,
276 RK3528_CLKGATE_CON(0), 4, GFLAGS),
277 COMPOSITE_NOMUX(CLK_MATRIX_300M_SRC, "clk_300m_src", "gpll", CLK_IS_CRITICAL,
278 RK3528_CLKSEL_CON(2), 0, 5, DFLAGS,
279 RK3528_CLKGATE_CON(0), 6, GFLAGS),
280 COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", CLK_IS_CRITICAL,
281 RK3528_CLKSEL_CON(2), 5, 5, DFLAGS,
282 RK3528_CLKGATE_CON(0), 7, GFLAGS),
283 COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", CLK_IGNORE_UNUSED,
284 RK3528_CLKSEL_CON(2), 10, 5, DFLAGS,
285 RK3528_CLKGATE_CON(0), 8, GFLAGS),
286 COMPOSITE_NOMUX(CLK_MATRIX_600M_SRC, "clk_600m_src", "gpll", CLK_IS_CRITICAL,
287 RK3528_CLKSEL_CON(4), 0, 5, DFLAGS,
288 RK3528_CLKGATE_CON(0), 11, GFLAGS),
289 COMPOSITE(DCLK_VOP_SRC0, "dclk_vop_src0", mux_gpll_cpll_p, 0,
290 RK3528_CLKSEL_CON(32), 10, 1, MFLAGS, 2, 8, DFLAGS,
291 RK3528_CLKGATE_CON(3), 7, GFLAGS),
292 COMPOSITE(DCLK_VOP_SRC1, "dclk_vop_src1", mux_gpll_cpll_p, 0,
293 RK3528_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 8, DFLAGS,
294 RK3528_CLKGATE_CON(3), 8, GFLAGS),
295 COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0,
296 RK3528_CLKSEL_CON(36), 5, 5, DFLAGS,
297 RK3528_CLKGATE_CON(3), 13, GFLAGS),
298
299 COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0,
300 RK3528_CLKSEL_CON(4), 5, 5, DFLAGS,
301 RK3528_CLKGATE_CON(0), 12, GFLAGS),
302 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
303 RK3528_CLKSEL_CON(5), 0,
304 RK3528_CLKGATE_CON(0), 13, GFLAGS, &rk3528_uart0_fracmux),
305 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
306 RK3528_CLKGATE_CON(0), 14, GFLAGS),
307
308 COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0,
309 RK3528_CLKSEL_CON(6), 2, 5, DFLAGS,
310 RK3528_CLKGATE_CON(0), 15, GFLAGS),
311 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
312 RK3528_CLKSEL_CON(7), 0,
313 RK3528_CLKGATE_CON(1), 0, GFLAGS, &rk3528_uart1_fracmux),
314 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
315 RK3528_CLKGATE_CON(1), 1, GFLAGS),
316
317 COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0,
318 RK3528_CLKSEL_CON(8), 2, 5, DFLAGS,
319 RK3528_CLKGATE_CON(1), 2, GFLAGS),
320 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
321 RK3528_CLKSEL_CON(9), 0,
322 RK3528_CLKGATE_CON(1), 3, GFLAGS, &rk3528_uart2_fracmux),
323 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
324 RK3528_CLKGATE_CON(1), 4, GFLAGS),
325
326 COMPOSITE_NOMUX(CLK_UART3_SRC, "clk_uart3_src", "gpll", 0,
327 RK3528_CLKSEL_CON(10), 2, 5, DFLAGS,
328 RK3528_CLKGATE_CON(1), 5, GFLAGS),
329 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
330 RK3528_CLKSEL_CON(11), 0,
331 RK3528_CLKGATE_CON(1), 6, GFLAGS, &rk3528_uart3_fracmux),
332 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
333 RK3528_CLKGATE_CON(1), 7, GFLAGS),
334
335 COMPOSITE_NOMUX(CLK_UART4_SRC, "clk_uart4_src", "gpll", 0,
336 RK3528_CLKSEL_CON(12), 2, 5, DFLAGS,
337 RK3528_CLKGATE_CON(1), 8, GFLAGS),
338 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
339 RK3528_CLKSEL_CON(13), 0,
340 RK3528_CLKGATE_CON(1), 9, GFLAGS, &rk3528_uart4_fracmux),
341 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
342 RK3528_CLKGATE_CON(1), 10, GFLAGS),
343
344 COMPOSITE_NOMUX(CLK_UART5_SRC, "clk_uart5_src", "gpll", 0,
345 RK3528_CLKSEL_CON(14), 2, 5, DFLAGS,
346 RK3528_CLKGATE_CON(1), 11, GFLAGS),
347 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
348 RK3528_CLKSEL_CON(15), 0,
349 RK3528_CLKGATE_CON(1), 12, GFLAGS, &rk3528_uart5_fracmux),
350 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
351 RK3528_CLKGATE_CON(1), 13, GFLAGS),
352
353 COMPOSITE_NOMUX(CLK_UART6_SRC, "clk_uart6_src", "gpll", 0,
354 RK3528_CLKSEL_CON(16), 2, 5, DFLAGS,
355 RK3528_CLKGATE_CON(1), 14, GFLAGS),
356 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
357 RK3528_CLKSEL_CON(17), 0,
358 RK3528_CLKGATE_CON(1), 15, GFLAGS, &rk3528_uart6_fracmux),
359 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
360 RK3528_CLKGATE_CON(2), 0, GFLAGS),
361
362 COMPOSITE_NOMUX(CLK_UART7_SRC, "clk_uart7_src", "gpll", 0,
363 RK3528_CLKSEL_CON(18), 2, 5, DFLAGS,
364 RK3528_CLKGATE_CON(2), 1, GFLAGS),
365 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
366 RK3528_CLKSEL_CON(19), 0,
367 RK3528_CLKGATE_CON(2), 2, GFLAGS, &rk3528_uart7_fracmux),
368 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
369 RK3528_CLKGATE_CON(2), 3, GFLAGS),
370
371 COMPOSITE_NOMUX(CLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", "gpll", 0,
372 RK3528_CLKSEL_CON(20), 8, 5, DFLAGS,
373 RK3528_CLKGATE_CON(2), 5, GFLAGS),
374 COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
375 RK3528_CLKSEL_CON(21), 0,
376 RK3528_CLKGATE_CON(2), 6, GFLAGS, &mclk_i2s0_2ch_sai_src_fracmux),
377 GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0,
378 RK3528_CLKGATE_CON(2), 7, GFLAGS),
379
380 COMPOSITE_NOMUX(CLK_I2S1_8CH_SRC, "clk_i2s1_8ch_src", "gpll", 0,
381 RK3528_CLKSEL_CON(24), 3, 5, DFLAGS,
382 RK3528_CLKGATE_CON(2), 11, GFLAGS),
383 COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", "clk_i2s1_8ch_src", CLK_SET_RATE_PARENT,
384 RK3528_CLKSEL_CON(25), 0,
385 RK3528_CLKGATE_CON(2), 12, GFLAGS, &mclk_i2s1_8ch_sai_src_fracmux),
386 GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0,
387 RK3528_CLKGATE_CON(2), 13, GFLAGS),
388
389 COMPOSITE_NOMUX(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "gpll", 0,
390 RK3528_CLKSEL_CON(26), 3, 5, DFLAGS,
391 RK3528_CLKGATE_CON(2), 14, GFLAGS),
392 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
393 RK3528_CLKSEL_CON(27), 0,
394 RK3528_CLKGATE_CON(2), 15, GFLAGS, &mclk_i2s2_2ch_sai_src_fracmux),
395 GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0,
396 RK3528_CLKGATE_CON(3), 0, GFLAGS),
397
398 COMPOSITE_NOMUX(CLK_I2S3_8CH_SRC, "clk_i2s3_8ch_src", "gpll", 0,
399 RK3528_CLKSEL_CON(22), 3, 5, DFLAGS,
400 RK3528_CLKGATE_CON(2), 8, GFLAGS),
401 COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", "clk_i2s3_8ch_src", CLK_SET_RATE_PARENT,
402 RK3528_CLKSEL_CON(23), 0,
403 RK3528_CLKGATE_CON(2), 9, GFLAGS, &mclk_i2s3_8ch_sai_src_fracmux),
404 GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0,
405 RK3528_CLKGATE_CON(2), 10, GFLAGS),
406
407 COMPOSITE_NOMUX(CLK_SPDIF_SRC, "clk_spdif_src", "gpll", 0,
408 RK3528_CLKSEL_CON(30), 2, 5, DFLAGS,
409 RK3528_CLKGATE_CON(3), 4, GFLAGS),
410 COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT,
411 RK3528_CLKSEL_CON(31), 0,
412 RK3528_CLKGATE_CON(3), 5, GFLAGS, &mclk_spdif_src_fracmux),
413 GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0,
414 RK3528_CLKGATE_CON(3), 6, GFLAGS),
415
416 /* bus */
417 COMPOSITE_NODIV(ACLK_BUS_M_ROOT, "aclk_bus_m_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
418 RK3528_CLKSEL_CON(43), 12, 2, MFLAGS,
419 RK3528_CLKGATE_CON(8), 7, GFLAGS),
420 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", CLK_IS_CRITICAL,
421 RK3528_CLKGATE_CON(9), 1, GFLAGS),
422
423 COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
424 RK3528_CLKSEL_CON(43), 6, 2, MFLAGS,
425 RK3528_CLKGATE_CON(8), 4, GFLAGS),
426 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0,
427 RK3528_CLKGATE_CON(9), 2, GFLAGS),
428 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
429 RK3528_CLKGATE_CON(9), 4, GFLAGS),
430 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0,
431 RK3528_CLKGATE_CON(11), 11, GFLAGS),
432 COMPOSITE(ACLK_BUS_VOPGL_ROOT, "aclk_bus_vopgl_root", mux_gpll_cpll_p, CLK_IS_CRITICAL,
433 RK3528_CLKSEL_CON(43), 3, 1, MFLAGS, 0, 3, DFLAGS,
434 RK3528_CLKGATE_CON(8), 0, GFLAGS),
435 COMPOSITE_NODIV(ACLK_BUS_H_ROOT, "aclk_bus_h_root", mux_500m_200m_100m_24m_p, CLK_IS_CRITICAL,
436 RK3528_CLKSEL_CON(43), 4, 2, MFLAGS,
437 RK3528_CLKGATE_CON(8), 2, GFLAGS),
438 GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_h_root", 0,
439 RK3528_CLKGATE_CON(10), 14, GFLAGS),
440
441 COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
442 RK3528_CLKSEL_CON(43), 8, 2, MFLAGS,
443 RK3528_CLKGATE_CON(8), 5, GFLAGS),
444
445 COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
446 RK3528_CLKSEL_CON(43), 10, 2, MFLAGS,
447 RK3528_CLKGATE_CON(8), 6, GFLAGS),
448 GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus_root", 0,
449 RK3528_CLKGATE_CON(8), 13, GFLAGS),
450 GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IS_CRITICAL,
451 RK3528_CLKGATE_CON(8), 15, GFLAGS),
452 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0,
453 RK3528_CLKGATE_CON(9), 5, GFLAGS),
454 GATE(PCLK_JDBCK_DAP, "pclk_jdbck_dap", "pclk_bus_root", 0,
455 RK3528_CLKGATE_CON(9), 12, GFLAGS),
456 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0,
457 RK3528_CLKGATE_CON(9), 15, GFLAGS),
458 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0,
459 RK3528_CLKGATE_CON(10), 7, GFLAGS),
460 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0,
461 RK3528_CLKGATE_CON(11), 4, GFLAGS),
462 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0,
463 RK3528_CLKGATE_CON(11), 7, GFLAGS),
464 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", 0,
465 RK3528_CLKGATE_CON(10), 13, GFLAGS),
466 GATE(PCLK_SCR, "pclk_scr", "pclk_bus_root", 0,
467 RK3528_CLKGATE_CON(11), 10, GFLAGS),
468 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", CLK_IGNORE_UNUSED,
469 RK3528_CLKGATE_CON(11), 12, GFLAGS),
470
471 COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_p, 0,
472 RK3528_CLKSEL_CON(44), 6, 2, MFLAGS,
473 RK3528_CLKGATE_CON(11), 5, GFLAGS),
474 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0,
475 RK3528_CLKSEL_CON(44), 8, 2, MFLAGS,
476 RK3528_CLKGATE_CON(11), 8, GFLAGS),
477
478 GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
479 RK3528_CLKGATE_CON(11), 9, GFLAGS),
480 GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
481 RK3528_CLKGATE_CON(11), 6, GFLAGS),
482 GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0,
483 RK3528_CLKGATE_CON(9), 13, GFLAGS),
484 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
485 RK3528_CLKGATE_CON(10), 0, GFLAGS),
486
487 GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
488 RK3528_CLKGATE_CON(8), 9, GFLAGS),
489 GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
490 RK3528_CLKGATE_CON(9), 6, GFLAGS),
491 GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
492 RK3528_CLKGATE_CON(9), 7, GFLAGS),
493 GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
494 RK3528_CLKGATE_CON(9), 8, GFLAGS),
495 GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
496 RK3528_CLKGATE_CON(9), 9, GFLAGS),
497 GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
498 RK3528_CLKGATE_CON(9), 10, GFLAGS),
499 GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
500 RK3528_CLKGATE_CON(9), 11, GFLAGS),
501
502 /* pmu */
503 GATE(HCLK_PMU_ROOT, "hclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED,
504 RK3528_PMU_CLKGATE_CON(0), 1, GFLAGS),
505 GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED,
506 RK3528_PMU_CLKGATE_CON(0), 0, GFLAGS),
507
508 GATE(FCLK_MCU, "fclk_mcu", "hclk_pmu_root", 0,
509 RK3528_PMU_CLKGATE_CON(0), 7, GFLAGS),
510 GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IS_CRITICAL,
511 RK3528_PMU_CLKGATE_CON(5), 4, GFLAGS),
512
513 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pmu_root", 0,
514 RK3528_PMU_CLKGATE_CON(0), 2, GFLAGS),
515 GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", 0,
516 RK3528_PMU_CLKGATE_CON(1), 2, GFLAGS),
517 GATE(PCLK_PMU_IOC, "pclk_pmu_ioc", "pclk_pmu_root", CLK_IS_CRITICAL,
518 RK3528_PMU_CLKGATE_CON(1), 5, GFLAGS),
519 GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IS_CRITICAL,
520 RK3528_PMU_CLKGATE_CON(1), 6, GFLAGS),
521 GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IS_CRITICAL,
522 RK3528_PMU_CLKGATE_CON(1), 7, GFLAGS),
523 GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
524 RK3528_PMU_CLKGATE_CON(1), 10, GFLAGS),
525 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
526 RK3528_PMU_CLKGATE_CON(0), 13, GFLAGS),
527 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0,
528 RK3528_PMU_CLKGATE_CON(0), 14, GFLAGS),
529 GATE(PCLK_OSCCHK, "pclk_oscchk", "pclk_pmu_root", 0,
530 RK3528_PMU_CLKGATE_CON(0), 9, GFLAGS),
531 GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
532 RK3528_PMU_CLKGATE_CON(1), 12, GFLAGS),
533 GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pmu_root", 0,
534 RK3528_PMU_CLKGATE_CON(1), 15, GFLAGS),
535 GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
536 RK3528_PMU_CLKGATE_CON(5), 1, GFLAGS),
537
538 COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", clk_i2c2_p, 0,
539 RK3528_PMU_CLKSEL_CON(0), 0, 2, MFLAGS,
540 RK3528_PMU_CLKGATE_CON(0), 3, GFLAGS),
541
542 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
543 RK3528_PMU_CLKGATE_CON(2), 4, GFLAGS),
544 COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
545 RK3528_PMU_CLKSEL_CON(5), 0, 5, DFLAGS,
546 RK3528_PMU_CLKGATE_CON(5), 0, GFLAGS),
547
548 COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0,
549 RK3528_PMU_CLKSEL_CON(1), 0,
550 RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS),
551 /* clk_32k: internal! No path from external osc 32k */
552 MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL,
553 RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS),
554 GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0,
555 RK3528_PMU_CLKGATE_CON(0), 8, GFLAGS),
556 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
557 RK3528_PMU_CLKGATE_CON(1), 1, GFLAGS),
558
559 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0,
560 RK3528_PMU_CLKSEL_CON(0), 2, 1, MFLAGS,
561 RK3528_PMU_CLKGATE_CON(0), 15, GFLAGS),
562 COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0,
563 RK3528_PMU_CLKSEL_CON(2), 1, 1, MFLAGS,
564 RK3528_PMU_CLKGATE_CON(1), 11, GFLAGS),
565
566 /* core */
567 COMPOSITE_NOMUX(ACLK_M_CORE_BIU, "aclk_m_core", "armclk", CLK_IS_CRITICAL,
568 RK3528_CLKSEL_CON(39), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
569 RK3528_CLKGATE_CON(5), 12, GFLAGS),
570 COMPOSITE_NOMUX(PCLK_DBG, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
571 RK3528_CLKSEL_CON(40), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
572 RK3528_CLKGATE_CON(5), 13, GFLAGS),
573 GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
574 RK3528_CLKGATE_CON(6), 1, GFLAGS),
575 GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_cpu_root", CLK_IS_CRITICAL,
576 RK3528_CLKGATE_CON(6), 2, GFLAGS),
577
578 /* ddr */
579 GATE(CLK_DDRC_SRC, "clk_ddrc_src", "dpll", CLK_IS_CRITICAL,
580 RK3528_DDRPHY_CLKGATE_CON(0), 0, GFLAGS),
581 GATE(CLK_DDR_PHY, "clk_ddr_phy", "dpll", CLK_IS_CRITICAL,
582 RK3528_DDRPHY_CLKGATE_CON(0), 1, GFLAGS),
583
584 COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
585 RK3528_CLKSEL_CON(90), 0, 2, MFLAGS,
586 RK3528_CLKGATE_CON(45), 0, GFLAGS),
587 GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IGNORE_UNUSED,
588 RK3528_CLKGATE_CON(45), 3, GFLAGS),
589 GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
590 RK3528_CLKGATE_CON(45), 8, GFLAGS),
591 GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
592 RK3528_CLKGATE_CON(45), 4, GFLAGS),
593
594 GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL,
595 RK3528_CLKGATE_CON(45), 2, GFLAGS),
596 GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr_root", CLK_IS_CRITICAL,
597 RK3528_CLKGATE_CON(45), 6, GFLAGS),
598 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL,
599 RK3528_CLKGATE_CON(45), 9, GFLAGS),
600
601 GATE(ACLK_DDR_UPCTL, "aclk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL,
602 RK3528_CLKGATE_CON(45), 11, GFLAGS),
603 GATE(CLK_DDR_UPCTL, "clk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL,
604 RK3528_CLKGATE_CON(45), 12, GFLAGS),
605 GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IS_CRITICAL,
606 RK3528_CLKGATE_CON(45), 13, GFLAGS),
607 GATE(ACLK_DDR_SCRAMBLE, "aclk_ddr_scramble", "clk_ddrc_src", CLK_IS_CRITICAL,
608 RK3528_CLKGATE_CON(45), 14, GFLAGS),
609 GATE(ACLK_SPLIT, "aclk_split", "clk_ddrc_src", CLK_IS_CRITICAL,
610 RK3528_CLKGATE_CON(45), 15, GFLAGS),
611
612 /* gpu */
613 COMPOSITE_NODIV(ACLK_GPU_ROOT, "aclk_gpu_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
614 RK3528_CLKSEL_CON(76), 0, 2, MFLAGS,
615 RK3528_CLKGATE_CON(34), 0, GFLAGS),
616 COMPOSITE_NODIV(ACLK_GPU, "aclk_gpu", aclk_gpu_p, CLK_SET_RATE_PARENT,
617 RK3528_CLKSEL_CON(76), 6, 1, MFLAGS,
618 RK3528_CLKGATE_CON(34), 7, GFLAGS),
619 GATE(ACLK_GPU_MALI, "aclk_gpu_mali", "aclk_gpu", 0,
620 RK3528_CLKGATE_CON(34), 8, GFLAGS),
621 COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
622 RK3528_CLKSEL_CON(76), 4, 2, MFLAGS,
623 RK3528_CLKGATE_CON(34), 2, GFLAGS),
624
625 /* rkvdec */
626 COMPOSITE_NODIV(ACLK_RKVDEC_ROOT_NDFT, "aclk_rkvdec_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
627 RK3528_CLKSEL_CON(88), 6, 2, MFLAGS,
628 RK3528_CLKGATE_CON(44), 3, GFLAGS),
629 COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
630 RK3528_CLKSEL_CON(88), 4, 2, MFLAGS,
631 RK3528_CLKGATE_CON(44), 2, GFLAGS),
632 GATE(PCLK_DDRPHY_CRU, "pclk_ddrphy_cru", "hclk_rkvdec_root", CLK_IS_CRITICAL,
633 RK3528_CLKGATE_CON(44), 4, GFLAGS),
634 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0,
635 RK3528_CLKGATE_CON(44), 9, GFLAGS),
636 COMPOSITE_NODIV(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", mux_600m_300m_200m_24m_p, 0,
637 RK3528_CLKSEL_CON(88), 11, 2, MFLAGS,
638 RK3528_CLKGATE_CON(44), 11, GFLAGS),
639 MUX(ACLK_RKVDEC_PVTMUX_ROOT, "aclk_rkvdec_pvtmux_root", aclk_rkvdec_pvtmux_root_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
640 RK3528_CLKSEL_CON(88), 13, 1, MFLAGS),
641 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pvtmux_root", 0,
642 RK3528_CLKGATE_CON(44), 8, GFLAGS),
643
644 /* rkvenc */
645 COMPOSITE_NODIV(ACLK_RKVENC_ROOT, "aclk_rkvenc_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
646 RK3528_CLKSEL_CON(79), 2, 2, MFLAGS,
647 RK3528_CLKGATE_CON(36), 1, GFLAGS),
648 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0,
649 RK3528_CLKGATE_CON(36), 7, GFLAGS),
650
651 COMPOSITE_NODIV(PCLK_RKVENC_ROOT, "pclk_rkvenc_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
652 RK3528_CLKSEL_CON(79), 4, 2, MFLAGS,
653 RK3528_CLKGATE_CON(36), 2, GFLAGS),
654 GATE(PCLK_RKVENC_IOC, "pclk_rkvenc_ioc", "pclk_rkvenc_root", CLK_IS_CRITICAL,
655 RK3528_CLKGATE_CON(37), 10, GFLAGS),
656 GATE(PCLK_RKVENC_GRF, "pclk_rkvenc_grf", "pclk_rkvenc_root", CLK_IS_CRITICAL,
657 RK3528_CLKGATE_CON(38), 6, GFLAGS),
658 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_rkvenc_root", 0,
659 RK3528_CLKGATE_CON(36), 11, GFLAGS),
660 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_rkvenc_root", 0,
661 RK3528_CLKGATE_CON(36), 13, GFLAGS),
662 GATE(PCLK_SPI0, "pclk_spi0", "pclk_rkvenc_root", 0,
663 RK3528_CLKGATE_CON(37), 2, GFLAGS),
664 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_rkvenc_root", 0,
665 RK3528_CLKGATE_CON(37), 8, GFLAGS),
666 GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0,
667 RK3528_CLKGATE_CON(38), 2, GFLAGS),
668 GATE(PCLK_UART3, "pclk_uart3", "pclk_rkvenc_root", 0,
669 RK3528_CLKGATE_CON(38), 4, GFLAGS),
670 GATE(PCLK_CAN0, "pclk_can0", "pclk_rkvenc_root", 0,
671 RK3528_CLKGATE_CON(38), 7, GFLAGS),
672 GATE(PCLK_CAN1, "pclk_can1", "pclk_rkvenc_root", 0,
673 RK3528_CLKGATE_CON(38), 9, GFLAGS),
674
675 COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mux_150m_100m_24m_p, 0,
676 RK3528_CLKSEL_CON(80), 12, 2, MFLAGS,
677 RK3528_CLKGATE_CON(38), 1, GFLAGS),
678 COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_p, 0,
679 RK3528_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS,
680 RK3528_CLKGATE_CON(38), 8, GFLAGS),
681 COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_p, 0,
682 RK3528_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS,
683 RK3528_CLKGATE_CON(38), 10, GFLAGS),
684
685 COMPOSITE_NODIV(HCLK_RKVENC_ROOT, "hclk_rkvenc_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
686 RK3528_CLKSEL_CON(79), 0, 2, MFLAGS,
687 RK3528_CLKGATE_CON(36), 0, GFLAGS),
688 GATE(HCLK_SAI_I2S1, "hclk_sai_i2s1", "hclk_rkvenc_root", 0,
689 RK3528_CLKGATE_CON(36), 9, GFLAGS),
690 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_rkvenc_root", 0,
691 RK3528_CLKGATE_CON(37), 14, GFLAGS),
692 GATE(HCLK_PDM, "hclk_pdm", "hclk_rkvenc_root", 0,
693 RK3528_CLKGATE_CON(38), 0, GFLAGS),
694 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0,
695 RK3528_CLKGATE_CON(36), 6, GFLAGS),
696
697 COMPOSITE_NODIV(CLK_CORE_RKVENC, "clk_core_rkvenc", mux_300m_200m_100m_24m_p, 0,
698 RK3528_CLKSEL_CON(79), 6, 2, MFLAGS,
699 RK3528_CLKGATE_CON(36), 8, GFLAGS),
700 COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
701 RK3528_CLKSEL_CON(79), 11, 2, MFLAGS,
702 RK3528_CLKGATE_CON(36), 14, GFLAGS),
703 COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0,
704 RK3528_CLKSEL_CON(79), 9, 2, MFLAGS,
705 RK3528_CLKGATE_CON(36), 12, GFLAGS),
706 #if 0
707 GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0,
708 RK3528_CLKGATE_CON(37), 4, GFLAGS),
709 GATE(CLK_UART_JTAG, "clk_uart_jtag", "xin24m", 0,
710 RK3528_CLKGATE_CON(37), 0, GFLAGS),
711 #endif
712 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
713 RK3528_CLKSEL_CON(79), 13, 2, MFLAGS,
714 RK3528_CLKGATE_CON(37), 3, GFLAGS),
715 COMPOSITE_NODIV(MCLK_SAI_I2S1, "mclk_sai_i2s1", mclk_sai_i2s1_p, CLK_SET_RATE_PARENT,
716 RK3528_CLKSEL_CON(79), 8, 1, MFLAGS,
717 RK3528_CLKGATE_CON(36), 10, GFLAGS),
718 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
719 RK3528_CLKGATE_CON(37), 9, GFLAGS),
720
721 /* vo */
722 COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL,
723 RK3528_CLKSEL_CON(83), 2, 2, MFLAGS,
724 RK3528_CLKGATE_CON(39), 1, GFLAGS),
725 GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
726 RK3528_CLKGATE_CON(40), 2, GFLAGS),
727 GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_vo_root", 0,
728 RK3528_CLKGATE_CON(43), 3, GFLAGS),
729 GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vo_root", 0,
730 RK3528_CLKGATE_CON(41), 7, GFLAGS),
731 GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vo_root", 0,
732 RK3528_CLKGATE_CON(39), 10, GFLAGS),
733 GATE(HCLK_CVBS, "hclk_cvbs", "hclk_vo_root", 0,
734 RK3528_CLKGATE_CON(41), 3, GFLAGS),
735 GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_vo_root", 0,
736 RK3528_CLKGATE_CON(43), 4, GFLAGS),
737 GATE(HCLK_SAI_I2S3, "hclk_sai_i2s3", "hclk_vo_root", 0,
738 RK3528_CLKGATE_CON(42), 1, GFLAGS),
739 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo_root", 0,
740 RK3528_CLKGATE_CON(41), 1, GFLAGS),
741 GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
742 RK3528_CLKGATE_CON(39), 7, GFLAGS),
743 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vo_root", 0,
744 RK3528_CLKGATE_CON(42), 9, GFLAGS),
745 GATE(HCLK_HDCP_KEY, "hclk_hdcp_key", "hclk_vo_root", 0,
746 RK3528_CLKGATE_CON(40), 15, GFLAGS),
747
748 COMPOSITE_NODIV(ACLK_VO_L_ROOT, "aclk_vo_l_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL,
749 RK3528_CLKSEL_CON(84), 1, 2, MFLAGS,
750 RK3528_CLKGATE_CON(41), 8, GFLAGS),
751 GATE(ACLK_MAC_VO, "aclk_gmac0", "aclk_vo_l_root", 0,
752 RK3528_CLKGATE_CON(41), 10, GFLAGS),
753
754 COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
755 RK3528_CLKSEL_CON(83), 4, 2, MFLAGS,
756 RK3528_CLKGATE_CON(39), 2, GFLAGS),
757 GATE(PCLK_MAC_VO, "pclk_gmac0", "pclk_vo_root", 0,
758 RK3528_CLKGATE_CON(41), 11, GFLAGS),
759 GATE(PCLK_VCDCPHY, "pclk_vcdcphy", "pclk_vo_root", 0,
760 RK3528_CLKGATE_CON(42), 4, GFLAGS),
761 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
762 RK3528_CLKGATE_CON(42), 5, GFLAGS),
763 GATE(PCLK_VO_IOC, "pclk_vo_ioc", "pclk_vo_root", CLK_IS_CRITICAL,
764 RK3528_CLKGATE_CON(42), 7, GFLAGS),
765 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
766 RK3528_CLKGATE_CON(42), 11, GFLAGS),
767 GATE(PCLK_UART4, "pclk_uart4", "pclk_vo_root", 0,
768 RK3528_CLKGATE_CON(43), 7, GFLAGS),
769 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_vo_root", 0,
770 RK3528_CLKGATE_CON(43), 9, GFLAGS),
771 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_vo_root", 0,
772 RK3528_CLKGATE_CON(43), 11, GFLAGS),
773
774 GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_vo_root", 0,
775 RK3528_CLKGATE_CON(43), 13, GFLAGS),
776
777 GATE(PCLK_VO_GRF, "pclk_vo_grf", "pclk_vo_root", CLK_IS_CRITICAL,
778 RK3528_CLKGATE_CON(39), 13, GFLAGS),
779 GATE(PCLK_CRU, "pclk_cru", "pclk_vo_root", CLK_IS_CRITICAL,
780 RK3528_CLKGATE_CON(39), 15, GFLAGS),
781 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_vo_root", 0,
782 RK3528_CLKGATE_CON(40), 6, GFLAGS),
783 GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_vo_root", 0,
784 RK3528_CLKGATE_CON(40), 14, GFLAGS),
785 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo_root", 0,
786 RK3528_CLKGATE_CON(41), 2, GFLAGS),
787
788 COMPOSITE_NODIV(CLK_CORE_VDPP, "clk_core_vdpp", mux_339m_200m_100m_24m_p, 0,
789 RK3528_CLKSEL_CON(83), 10, 2, MFLAGS,
790 RK3528_CLKGATE_CON(39), 12, GFLAGS),
791 COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_339m_200m_100m_24m_p, 0,
792 RK3528_CLKSEL_CON(83), 8, 2, MFLAGS,
793 RK3528_CLKGATE_CON(39), 9, GFLAGS),
794 COMPOSITE_NODIV(ACLK_JPEG_ROOT, "aclk_jpeg_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
795 RK3528_CLKSEL_CON(84), 9, 2, MFLAGS,
796 RK3528_CLKGATE_CON(41), 15, GFLAGS),
797 GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_root", 0,
798 RK3528_CLKGATE_CON(41), 6, GFLAGS),
799
800 COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
801 RK3528_CLKSEL_CON(83), 0, 2, MFLAGS,
802 RK3528_CLKGATE_CON(39), 0, GFLAGS),
803 GATE_NO_SET_RATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
804 RK3528_CLKGATE_CON(39), 8, GFLAGS),
805 GATE_NO_SET_RATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0,
806 RK3528_CLKGATE_CON(39), 11, GFLAGS),
807 GATE_NO_SET_RATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0,
808 RK3528_CLKGATE_CON(41), 0, GFLAGS),
809
810 COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0,
811 RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS,
812 RK3528_CLKGATE_CON(42), 8, GFLAGS),
813
814 COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", mux_gpll_cpll_p, CLK_IS_CRITICAL,
815 RK3528_CLKSEL_CON(83), 15, 1, MFLAGS, 12, 3, DFLAGS,
816 RK3528_CLKGATE_CON(40), 0, GFLAGS),
817 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
818 RK3528_CLKGATE_CON(40), 5, GFLAGS),
819
820 COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,
821 RK3528_CLKSEL_CON(85), 13, 2, MFLAGS,
822 RK3528_CLKGATE_CON(43), 10, GFLAGS),
823 COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0,
824 RK3528_CLKSEL_CON(86), 0, 2, MFLAGS,
825 RK3528_CLKGATE_CON(43), 12, GFLAGS),
826 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
827 RK3528_CLKGATE_CON(42), 6, GFLAGS),
828
829 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
830 RK3528_CLKGATE_CON(43), 2, GFLAGS),
831 GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
832 RK3528_CLKGATE_CON(42), 3, GFLAGS),
833 GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
834 RK3528_CLKGATE_CON(43), 14, GFLAGS),
835 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
836 RK3528_CLKGATE_CON(42), 12, GFLAGS),
837 FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns", 0, 1, 2),
838
839 GATE(MCLK_SAI_I2S3, "mclk_sai_i2s3", "mclk_i2s3_8ch_sai_src", 0,
840 RK3528_CLKGATE_CON(42), 2, GFLAGS),
841 COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
842 RK3528_CLKSEL_CON(84), 0, 1, MFLAGS,
843 RK3528_CLKGATE_CON(40), 3, GFLAGS),
844 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", CLK_SET_RATE_PARENT,
845 RK3528_CLKGATE_CON(40), 4, GFLAGS),
846 FACTOR_GATE(DCLK_CVBS, "dclk_cvbs", "dclk_vop1", 0, 1, 4,
847 RK3528_CLKGATE_CON(41), 4, GFLAGS),
848 GATE(DCLK_4X_CVBS, "dclk_4x_cvbs", "dclk_vop1", 0,
849 RK3528_CLKGATE_CON(41), 5, GFLAGS),
850
851 FACTOR_GATE(CLK_SFR_HDMI, "clk_sfr_hdmi", "dclk_vop_src1", 0, 1, 4,
852 RK3528_CLKGATE_CON(40), 7, GFLAGS),
853
854 GATE(CLK_SPDIF_HDMI, "clk_spdif_hdmi", "mclk_spdif_src", 0,
855 RK3528_CLKGATE_CON(40), 10, GFLAGS),
856 GATE(MCLK_SPDIF, "mclk_spdif", "mclk_spdif_src", 0,
857 RK3528_CLKGATE_CON(37), 15, GFLAGS),
858 GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0,
859 RK3528_CLKGATE_CON(40), 8, GFLAGS),
860 #if 0
861 GATE(CLK_USBHOST_OHCI, "clk_usbhost_ohci", "clk_usbhost_ohci_io", 0,
862 RK3528_CLKGATE_CON(43), 5, GFLAGS),
863 GATE(CLK_USBHOST_UTMI, "clk_usbhost_utmi", "clk_usbhost_utmi_io", 0,
864 RK3528_CLKGATE_CON(43), 6, GFLAGS),
865 GATE(CLK_HDMIPHY_TMDSSRC, "clk_hdmiphy_tmdssrc", "clk_hdmiphy_tmdssrc_io", 0,
866 RK3528_CLKGATE_CON(40), 11, GFLAGS),
867 GATE(CLK_HDMIPHY_PREP, "clk_hdmiphy_prep", "clk_hdmiphy_prep_io", 0,
868 RK3528_CLKGATE_CON(40), 12, GFLAGS),
869 #endif
870 /* vpu */
871 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
872 RK3528_CLKGATE_CON(26), 5, GFLAGS),
873 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
874 RK3528_CLKGATE_CON(27), 1, GFLAGS),
875 GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0,
876 RK3528_CLKGATE_CON(33), 4, GFLAGS),
877 GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0,
878 RK3528_CLKGATE_CON(30), 2, GFLAGS),
879 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
880 RK3528_CLKGATE_CON(26), 3, GFLAGS),
881 GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0,
882 RK3528_CLKGATE_CON(33), 2, GFLAGS),
883 COMPOSITE(CCLK_SRC_SDIO0, "cclk_src_sdio0", mux_gpll_cpll_xin24m_p, 0,
884 RK3528_CLKSEL_CON(72), 6, 2, MFLAGS, 0, 6, DFLAGS,
885 RK3528_CLKGATE_CON(32), 1, GFLAGS),
886
887 COMPOSITE_NODIV(PCLK_VPU_ROOT, "pclk_vpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
888 RK3528_CLKSEL_CON(61), 4, 2, MFLAGS,
889 RK3528_CLKGATE_CON(25), 5, GFLAGS),
890 GATE(PCLK_VPU_GRF, "pclk_vpu_grf", "pclk_vpu_root", CLK_IS_CRITICAL,
891 RK3528_CLKGATE_CON(25), 12, GFLAGS),
892 GATE(PCLK_CRU_PCIE, "pclk_cru_pcie", "pclk_vpu_root", CLK_IS_CRITICAL,
893 RK3528_CLKGATE_CON(25), 11, GFLAGS),
894 GATE(PCLK_UART6, "pclk_uart6", "pclk_vpu_root", 0,
895 RK3528_CLKGATE_CON(27), 11, GFLAGS),
896 GATE(PCLK_CAN2, "pclk_can2", "pclk_vpu_root", 0,
897 RK3528_CLKGATE_CON(32), 7, GFLAGS),
898 GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0,
899 RK3528_CLKGATE_CON(27), 4, GFLAGS),
900 GATE(PCLK_CAN3, "pclk_can3", "pclk_vpu_root", 0,
901 RK3528_CLKGATE_CON(32), 9, GFLAGS),
902 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vpu_root", 0,
903 RK3528_CLKGATE_CON(27), 0, GFLAGS),
904 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0,
905 RK3528_CLKGATE_CON(26), 4, GFLAGS),
906 GATE(PCLK_SARADC, "pclk_saradc", "pclk_vpu_root", 0,
907 RK3528_CLKGATE_CON(32), 11, GFLAGS),
908 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_vpu_root", 0,
909 RK3528_CLKGATE_CON(26), 13, GFLAGS),
910 GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0,
911 RK3528_CLKGATE_CON(27), 13, GFLAGS),
912 GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0,
913 RK3528_CLKGATE_CON(27), 9, GFLAGS),
914 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vpu_root", 0,
915 RK3528_CLKGATE_CON(32), 14, GFLAGS),
916 GATE(PCLK_PCIE, "pclk_pcie", "pclk_vpu_root", 0,
917 RK3528_CLKGATE_CON(30), 1, GFLAGS),
918 GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0,
919 RK3528_CLKGATE_CON(27), 7, GFLAGS),
920 GATE(PCLK_VPU_IOC, "pclk_vpu_ioc", "pclk_vpu_root", CLK_IS_CRITICAL,
921 RK3528_CLKGATE_CON(26), 8, GFLAGS),
922 GATE(PCLK_PIPE_GRF, "pclk_pipe_grf", "pclk_vpu_root", CLK_IS_CRITICAL,
923 RK3528_CLKGATE_CON(30), 7, GFLAGS),
924 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_vpu_root", 0,
925 RK3528_CLKGATE_CON(28), 1, GFLAGS),
926 GATE(PCLK_PCIE_PHY, "pclk_pcie_phy", "pclk_vpu_root", 0,
927 RK3528_CLKGATE_CON(30), 6, GFLAGS),
928 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_vpu_root", 0,
929 RK3528_CLKGATE_CON(27), 15, GFLAGS),
930 GATE(PCLK_MAC_VPU, "pclk_gmac1", "pclk_vpu_root", CLK_IS_CRITICAL,
931 RK3528_CLKGATE_CON(28), 6, GFLAGS),
932 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_vpu_root", 0,
933 RK3528_CLKGATE_CON(28), 3, GFLAGS),
934
935 COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
936 RK3528_CLKSEL_CON(60), 0, 2, MFLAGS,
937 RK3528_CLKGATE_CON(25), 0, GFLAGS),
938 GATE_NO_SET_RATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0,
939 RK3528_CLKGATE_CON(26), 1, GFLAGS),
940 GATE_NO_SET_RATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0,
941 RK3528_CLKGATE_CON(28), 5, GFLAGS),
942 GATE_NO_SET_RATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0,
943 RK3528_CLKGATE_CON(30), 3, GFLAGS),
944
945 GATE_NO_SET_RATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0,
946 RK3528_CLKGATE_CON(33), 1, GFLAGS),
947
948 COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
949 RK3528_CLKSEL_CON(61), 2, 2, MFLAGS,
950 RK3528_CLKGATE_CON(25), 4, GFLAGS),
951 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0,
952 RK3528_CLKGATE_CON(25), 10, GFLAGS),
953 GATE(HCLK_SFC, "hclk_sfc", "hclk_vpu_root", 0,
954 RK3528_CLKGATE_CON(25), 13, GFLAGS),
955 GATE(HCLK_EMMC, "hclk_emmc", "hclk_vpu_root", 0,
956 RK3528_CLKGATE_CON(26), 0, GFLAGS),
957 GATE(HCLK_SAI_I2S0, "hclk_sai_i2s0", "hclk_vpu_root", 0,
958 RK3528_CLKGATE_CON(26), 9, GFLAGS),
959 GATE(HCLK_SAI_I2S2, "hclk_sai_i2s2", "hclk_vpu_root", 0,
960 RK3528_CLKGATE_CON(26), 11, GFLAGS),
961
962 GATE(HCLK_PCIE_SLV, "hclk_pcie_slv", "hclk_vpu_root", 0,
963 RK3528_CLKGATE_CON(30), 4, GFLAGS),
964 GATE(HCLK_PCIE_DBI, "hclk_pcie_dbi", "hclk_vpu_root", 0,
965 RK3528_CLKGATE_CON(30), 5, GFLAGS),
966 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_vpu_root", 0,
967 RK3528_CLKGATE_CON(32), 2, GFLAGS),
968 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0,
969 RK3528_CLKGATE_CON(32), 4, GFLAGS),
970
971 COMPOSITE_NOMUX(CLK_GMAC1_VPU_25M, "clk_gmac1_25m", "ppll", 0,
972 RK3528_CLKSEL_CON(60), 2, 8, DFLAGS,
973 RK3528_CLKGATE_CON(25), 1, GFLAGS),
974 COMPOSITE_NOMUX(CLK_PPLL_125M_MATRIX, "clk_ppll_125m_src", "ppll", 0,
975 RK3528_CLKSEL_CON(60), 10, 5, DFLAGS,
976 RK3528_CLKGATE_CON(25), 2, GFLAGS),
977
978 COMPOSITE(CLK_CAN3, "clk_can3", mux_gpll_cpll_p, 0,
979 RK3528_CLKSEL_CON(73), 13, 1, MFLAGS, 7, 6, DFLAGS,
980 RK3528_CLKGATE_CON(32), 10, GFLAGS),
981 COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0,
982 RK3528_CLKSEL_CON(64), 0, 2, MFLAGS,
983 RK3528_CLKGATE_CON(28), 4, GFLAGS),
984
985 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_gpll_cpll_xin24m_p, 0,
986 RK3528_CLKSEL_CON(61), 12, 2, MFLAGS, 6, 6, DFLAGS,
987 RK3528_CLKGATE_CON(25), 14, GFLAGS),
988 COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_gpll_cpll_xin24m_p, 0,
989 RK3528_CLKSEL_CON(62), 6, 2, MFLAGS, 0, 6, DFLAGS,
990 RK3528_CLKGATE_CON(25), 15, GFLAGS),
991
992 COMPOSITE_NODIV(ACLK_VPU_ROOT, "aclk_vpu_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
993 RK3528_CLKSEL_CON(61), 0, 2, MFLAGS,
994 RK3528_CLKGATE_CON(25), 3, GFLAGS),
995 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0,
996 RK3528_CLKGATE_CON(25), 9, GFLAGS),
997
998 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
999 RK3528_CLKSEL_CON(63), 10, 2, MFLAGS,
1000 RK3528_CLKGATE_CON(27), 5, GFLAGS),
1001 COMPOSITE(CCLK_SRC_SDIO1, "cclk_src_sdio1", mux_gpll_cpll_xin24m_p, 0,
1002 RK3528_CLKSEL_CON(72), 14, 2, MFLAGS, 8, 6, DFLAGS,
1003 RK3528_CLKGATE_CON(32), 3, GFLAGS),
1004 COMPOSITE(CLK_CAN2, "clk_can2", mux_gpll_cpll_p, 0,
1005 RK3528_CLKSEL_CON(73), 6, 1, MFLAGS, 0, 6, DFLAGS,
1006 RK3528_CLKGATE_CON(32), 8, GFLAGS),
1007 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
1008 RK3528_CLKSEL_CON(74), 3, 5, DFLAGS,
1009 RK3528_CLKGATE_CON(32), 15, GFLAGS),
1010 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
1011 RK3528_CLKSEL_CON(74), 0, 3, DFLAGS,
1012 RK3528_CLKGATE_CON(32), 12, GFLAGS),
1013 COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
1014 RK3528_CLKSEL_CON(74), 8, 5, DFLAGS,
1015 RK3528_CLKGATE_CON(33), 0, GFLAGS),
1016 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0,
1017 RK3528_CLKSEL_CON(62), 8, 2, MFLAGS,
1018 RK3528_CLKGATE_CON(26), 2, GFLAGS),
1019 COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s2_2ch_sai_src", 0,
1020 RK3528_CLKSEL_CON(63), 0, 8, DFLAGS,
1021 RK3528_CLKGATE_CON(26), 14, GFLAGS),
1022 COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,
1023 RK3528_CLKSEL_CON(63), 12, 2, MFLAGS,
1024 RK3528_CLKGATE_CON(28), 0, GFLAGS),
1025 COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0,
1026 RK3528_CLKSEL_CON(63), 14, 2, MFLAGS,
1027 RK3528_CLKGATE_CON(28), 2, GFLAGS),
1028 COMPOSITE_NODIV(MCLK_SAI_I2S0, "mclk_sai_i2s0", mclk_sai_i2s0_p, CLK_SET_RATE_PARENT,
1029 RK3528_CLKSEL_CON(62), 10, 1, MFLAGS,
1030 RK3528_CLKGATE_CON(26), 10, GFLAGS),
1031 GATE(MCLK_SAI_I2S2, "mclk_sai_i2s2", "mclk_i2s2_2ch_sai_src", 0,
1032 RK3528_CLKGATE_CON(26), 12, GFLAGS),
1033 #if 0
1034 GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0,
1035 RK3528_CLKGATE_CON(27), 6, GFLAGS),
1036
1037 /* vpuphy */
1038 GATE(CLK_PIPE_USB3OTG_COMBO, "clk_pipe_usb3otg_combo", "clk_pipe_usb3otg_io", 0,
1039 RK3528_CLKGATE_CON(31), 0, GFLAGS),
1040 GATE(CLK_UTMI_USB3OTG, "clk_utmi_usb3otg", "clk_utmi_usb3otg_io", 0,
1041 RK3528_CLKGATE_CON(31), 1, GFLAGS),
1042 GATE(CLK_PCIE_PIPE_PHY, "clk_pcie_pipe_phy", "clk_pipe_usb3otg_io", 0,
1043 RK3528_CLKGATE_CON(31), 2, GFLAGS),
1044 #endif
1045 /* pcie */
1046 COMPOSITE_NOMUX(CLK_PPLL_100M_MATRIX, "clk_ppll_100m_src", "ppll", CLK_IS_CRITICAL,
1047 RK3528_PCIE_CLKSEL_CON(1), 2, 5, DFLAGS,
1048 RK3528_PCIE_CLKGATE_CON(0), 1, GFLAGS),
1049 COMPOSITE_NOMUX(CLK_PPLL_50M_MATRIX, "clk_ppll_50m_src", "ppll", CLK_IS_CRITICAL,
1050 RK3528_PCIE_CLKSEL_CON(1), 7, 5, DFLAGS,
1051 RK3528_PCIE_CLKGATE_CON(0), 2, GFLAGS),
1052 MUX(CLK_REF_PCIE_INNER_PHY, "clk_ref_pcie_inner_phy", clk_ref_pcie_inner_phy_p, 0,
1053 RK3528_PCIE_CLKSEL_CON(1), 13, 1, MFLAGS),
1054 FACTOR(CLK_REF_PCIE_100M_PHY, "clk_ref_pcie_100m_phy", "clk_ppll_100m_src", 0, 1, 1),
1055
1056 /* gmac */
1057 FACTOR(CLK_GMAC1_RMII_VPU, "clk_gmac1_50m", "clk_ppll_50m_src", 0, 1, 1),
1058 FACTOR(CLK_GMAC1_SRC_VPU, "clk_gmac1_125m", "clk_ppll_125m_src", 0, 1, 1),
1059
1060 /* they are orphans */
1061 DIV(CLK_GMAC0_SRC, "clk_gmac0_src", "clk_gmac0_io_i", 0,
1062 RK3528_CLKSEL_CON(84), 3, 6, DFLAGS),
1063 GATE(CLK_GMAC0_TX, "clk_gmac0_tx", "clk_gmac0_src", 0,
1064 RK3528_CLKGATE_CON(41), 13, GFLAGS),
1065 GATE(CLK_GMAC0_RX, "clk_gmac0_rx", "clk_gmac0_src", 0,
1066 RK3528_CLKGATE_CON(41), 14, GFLAGS),
1067 GATE(CLK_GMAC0_RMII_50M, "clk_gmac0_rmii_50m", "clk_gmac0_io_i", 0,
1068 RK3528_CLKGATE_CON(41), 12, GFLAGS),
1069 GATE(CLK_SCRKEYGEN, "clk_scrkeygen", "clk_pmupvtm_out", 0,
1070 RK3528_PMU_CLKGATE_CON(2), 0, GFLAGS),
1071 GATE(CLK_PVTM_OSCCHK, "clk_pvtm_oscchk", "clk_pmupvtm_out", 0,
1072 RK3528_PMU_CLKGATE_CON(2), 1, GFLAGS),
1073 };
1074
1075 static struct rockchip_clk_branch rk3528_grf_clk_branches[] __initdata = {
1076 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc0", RK3528_SDMMC_CON0, 1),
1077 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc0", RK3528_SDMMC_CON1, 1),
1078 MMC(SCLK_SDIO0_DRV, "sdio0_drv", "cclk_src_sdio0", RK3528_SDIO0_CON0, 1),
1079 MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "cclk_src_sdio0", RK3528_SDIO0_CON1, 1),
1080 MMC(SCLK_SDIO1_DRV, "sdio1_drv", "cclk_src_sdio1", RK3528_SDIO1_CON0, 1),
1081 MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "cclk_src_sdio1", RK3528_SDIO1_CON1, 1),
1082 };
1083
1084 static void __iomem *rk3528_cru_base;
1085
rk3528_dump_cru(void)1086 static void rk3528_dump_cru(void)
1087 {
1088 if (rk3528_cru_base) {
1089 pr_warn("CRU:\n");
1090 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1091 32, 4, rk3528_cru_base,
1092 0x8b8, false);
1093 pr_warn("PCIE CRU:\n");
1094 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1095 32, 4, rk3528_cru_base + RK3528_PCIE_CRU_BASE,
1096 0x804, false);
1097 pr_warn("DDRPHY CRU:\n");
1098 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1099 32, 4, rk3528_cru_base + RK3528_DDRPHY_CRU_BASE,
1100 0x804, false);
1101 }
1102 }
1103
rk3528_clk_init(struct device_node * np)1104 static void __init rk3528_clk_init(struct device_node *np)
1105 {
1106 struct rockchip_clk_provider *ctx;
1107 void __iomem *reg_base;
1108 struct clk **clks;
1109
1110 reg_base = of_iomap(np, 0);
1111 if (!reg_base) {
1112 pr_err("%s: could not map cru region\n", __func__);
1113 return;
1114 }
1115
1116 rk3528_cru_base = reg_base;
1117
1118 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1119 if (IS_ERR(ctx)) {
1120 pr_err("%s: rockchip clk init failed\n", __func__);
1121 iounmap(reg_base);
1122 return;
1123 }
1124 clks = ctx->clk_data.clks;
1125
1126 rockchip_clk_register_plls(ctx, rk3528_pll_clks,
1127 ARRAY_SIZE(rk3528_pll_clks),
1128 RK3528_GRF_SOC_STATUS0);
1129
1130 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1131 2, clks[PLL_APLL], clks[PLL_GPLL],
1132 &rk3528_cpuclk_data, rk3528_cpuclk_rates,
1133 ARRAY_SIZE(rk3528_cpuclk_rates));
1134 rockchip_clk_register_branches(ctx, rk3528_clk_branches,
1135 ARRAY_SIZE(rk3528_clk_branches));
1136
1137 rockchip_register_softrst(np, 47, reg_base + RK3528_SOFTRST_CON(0),
1138 ROCKCHIP_SOFTRST_HIWORD_MASK);
1139 rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL);
1140
1141 rockchip_clk_of_add_provider(np, ctx);
1142
1143 if (!rk_dump_cru)
1144 rk_dump_cru = rk3528_dump_cru;
1145
1146 }
1147
1148 CLK_OF_DECLARE(rk3528_cru, "rockchip,rk3528-cru", rk3528_clk_init);
1149
rk3528_grf_clk_init(struct device_node * np)1150 static void __init rk3528_grf_clk_init(struct device_node *np)
1151 {
1152 struct rockchip_clk_provider *ctx;
1153 void __iomem *reg_base;
1154
1155 reg_base = of_iomap(of_get_parent(np), 0);
1156 if (!reg_base) {
1157 pr_err("%s: could not map cru grf region\n", __func__);
1158 return;
1159 }
1160
1161 ctx = rockchip_clk_init(np, reg_base, CLK_NR_GRF_CLKS);
1162 if (IS_ERR(ctx)) {
1163 pr_err("%s: rockchip grf clk init failed\n", __func__);
1164 return;
1165 }
1166
1167 rockchip_clk_register_branches(ctx, rk3528_grf_clk_branches,
1168 ARRAY_SIZE(rk3528_grf_clk_branches));
1169
1170 rockchip_clk_of_add_provider(np, ctx);
1171 }
1172
1173 CLK_OF_DECLARE(rk3528_grf_cru, "rockchip,rk3528-grf-cru", rk3528_grf_clk_init);
1174
1175