| 6dbcc962 | 13-Sep-2016 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: add peripheral clock init table
Currently, Tegra peripheral drivers control two aspects of their HW module
clock(s):
1) The clock enable/rate for the peripheral clock itself.
2) The sy
ARM: tegra: add peripheral clock init table
Currently, Tegra peripheral drivers control two aspects of their HW module
clock(s):
1) The clock enable/rate for the peripheral clock itself.
2) The system-level clock tree setup, i.e. the clock parent.
Aspect 1 is reasonable, but aspect 2 is a system-level decision, not
something that an individual peripheral driver should in general know
about or influence. Such system-level knowledge ties the driver to a
specific SoC implementation, even when they use generic APIs for clock
manipulation, since they must have SoC-specific knowledge such as parent
clock IDs. Limited exceptions exist, such as where peripheral HW is
expected to dynamically switch between clock sources at run-time, such
as CPU clock scaling or display clock conflict management in a multi-head
scenario.
This patch enhances the Tegra core code to perform system-level clock
tree setup, in a similar fashion to the Linux kernel Tegra clock driver.
This will allow future patches to simplify peripheral drivers by removing
the clock parent setup logic.
This change is required prior to converting peripheral drivers to use the
standard clock APIs, since:
1) The clock uclass doesn't currently support a set_parent() operation.
Adding one is possible, but not necessary at the moment.
2) The clock APIs retrieve all clock IDs from device tree, and the DT
bindings for almost all peripherals only includes information about the
relevant peripheral clocks, and not any potential parent clocks.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 6a474db4 | 13-Sep-2016 |
Tom Warren <twarren@nvidia.com> |
mmc: tegra: Add DM_MMC support to Tegra MMC driver
Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed
to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds.
Cc:
mmc: tegra: Add DM_MMC support to Tegra MMC driver
Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed
to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
(swarren, fixed some NULL pointer dereferences, removed extraneous
changes, rebased on various other changes, removed non-DM support etc.)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| c0be77db | 13-Sep-2016 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: set MMC pin mux in board_init()
Most other pin mux is configured in this function. This removes the
need to do it in an MMC-specific initialization function, which is good
since that fun
ARM: tegra: set MMC pin mux in board_init()
Most other pin mux is configured in this function. This removes the
need to do it in an MMC-specific initialization function, which is good
since that function is going away later in this series.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 027638d3 | 11-Aug-2016 |
Bryan Wu <pengw@nvidia.com> |
ARM: tegra: reduce CSITE clock from 204M to 136M
The L4T kernel complains about a CSITE clock rate above 144MHz, presumably
because the HW is only characterized for a clock less than that. Adjust th
ARM: tegra: reduce CSITE clock from 204M to 136M
The L4T kernel complains about a CSITE clock rate above 144MHz, presumably
because the HW is only characterized for a clock less than that. Adjust the
rate to 136MHz to avoid the warning and stay in spec.
Signed-off-by: Bryan Wu <pengw@nvidia.com>
(swarren, re-wrote commit description)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 4dd99d14 | 08-Aug-2016 |
Stephen Warren <swarren@nvidia.com> |
reset: add Tegra186 reset driver
In Tegra186, on-SoC reset signals are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does tha
reset: add Tegra186 reset driver
In Tegra186, on-SoC reset signals are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that. It is unconditionally selected by CONFIG_TEGRA186
since virtually any Tegra186 build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| d9fd7008 | 08-Aug-2016 |
Stephen Warren <swarren@nvidia.com> |
clock: add Tegra186 clock driver
In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A te
clock: add Tegra186 clock driver
In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A tegra/ sub-directory is created to follow the existing
pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually
any Tegra186 build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 2a5f7f20 | 18-Jul-2016 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: pick up actual memory size
On Tegra186, U-Boot is booted by the binary firmware as if it were a
Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address
of that DTB, and
ARM: tegra: pick up actual memory size
On Tegra186, U-Boot is booted by the binary firmware as if it were a
Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address
of that DTB, and parse the /memory/reg property to determine the actual
RAM regions that U-Boot and subsequent EL2/EL1 SW may actually use.
Given the binary FW passes a DTB to U-Boot, I anticipate the suggestion
that U-Boot use that DTB as its control DTB. I don't believe that would
work well, so I do not plan to put any effort into this. By default the
FW-supplied DTB is the L4T kernel's DTB, which uses non-upstreamed DT
bindings. U-Boot aims to use only upstreamed DT bindings, or as close as
it can get. Replacing this DTB with a DTB using upstream bindings is
physically quite easy; simply replace the content of one of the GPT
partitions on the eMMC. However, the binary FW at least partially relies
on the existence/content of some nodes in the DTB, and that requires the
DTB to be written according to downstream bindings. Equally, if U-Boot
continues to use appended DTBs built from its own source tree, as it does
for all other Tegra platforms, development and deployment is much easier.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 49626ea8 | 18-Jul-2016 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: add IVC protocol implementation
IVC (Inter-VM Communication) protocol is a Tegra-specific IPC (Inter
Processor Communication) framework. Within the context of U-Boot, it is
typically use
ARM: tegra: add IVC protocol implementation
IVC (Inter-VM Communication) protocol is a Tegra-specific IPC (Inter
Processor Communication) framework. Within the context of U-Boot, it is
typically used for communication between the main CPU and various
auxiliary processors. In particular, it will be used to communicate with
the BPMP (Boot and Power Management Processor) on Tegra186 in order to
manipulate clocks and reset signals.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| d0f45000 | 18-Jul-2016 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: unify Tegra186 Makefile a bit
Many files in arch/arm/mach-tegra are compiled conditionally based on
Kconfig variables, or applicable to all platforms. We can let the main
Tegra Makefile
ARM: tegra: unify Tegra186 Makefile a bit
Many files in arch/arm/mach-tegra are compiled conditionally based on
Kconfig variables, or applicable to all platforms. We can let the main
Tegra Makefile handle compiling (or not) those files to avoid each SoC-
specific Makefile needing to duplicate entries for those files. This
leaves the SoC-specific Makefiles to compile truly SoC-specific code.
In the future, we'll hopefully add Kconfig variables for all the other
files, and refactor those files, and so reduce the need for SoC-specific
Makefiles and/or ifdefs in the Makefiles.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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