1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <linux/compiler.h> 13 #include <linux/sizes.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/funcmux.h> 17 #include <asm/arch/pinmux.h> 18 #include <asm/arch/pmu.h> 19 #include <asm/arch/tegra.h> 20 #include <asm/arch-tegra/ap.h> 21 #include <asm/arch-tegra/board.h> 22 #include <asm/arch-tegra/clk_rst.h> 23 #include <asm/arch-tegra/pmc.h> 24 #include <asm/arch-tegra/sys_proto.h> 25 #include <asm/arch-tegra/uart.h> 26 #include <asm/arch-tegra/warmboot.h> 27 #include <asm/arch-tegra/gpu.h> 28 #ifdef CONFIG_TEGRA_CLOCK_SCALING 29 #include <asm/arch/emc.h> 30 #endif 31 #include <asm/arch-tegra/usb.h> 32 #ifdef CONFIG_USB_EHCI_TEGRA 33 #include <usb.h> 34 #endif 35 #ifdef CONFIG_TEGRA_MMC 36 #include <asm/arch-tegra/mmc.h> 37 #endif 38 #include <asm/arch-tegra/xusb-padctl.h> 39 #include <power/as3722.h> 40 #include <i2c.h> 41 #include <spi.h> 42 #include "emc.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 #ifdef CONFIG_SPL_BUILD 47 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 48 U_BOOT_DEVICE(tegra_gpios) = { 49 "gpio_tegra" 50 }; 51 #endif 52 53 __weak void pinmux_init(void) {} 54 __weak void pin_mux_usb(void) {} 55 __weak void pin_mux_spi(void) {} 56 __weak void gpio_early_init_uart(void) {} 57 __weak void pin_mux_display(void) {} 58 __weak void start_cpu_fan(void) {} 59 60 #if defined(CONFIG_TEGRA_NAND) 61 __weak void pin_mux_nand(void) 62 { 63 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); 64 } 65 #endif 66 67 /* 68 * Routine: power_det_init 69 * Description: turn off power detects 70 */ 71 static void power_det_init(void) 72 { 73 #if defined(CONFIG_TEGRA20) 74 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 75 76 /* turn off power detects */ 77 writel(0, &pmc->pmc_pwr_det_latch); 78 writel(0, &pmc->pmc_pwr_det); 79 #endif 80 } 81 82 __weak int tegra_board_id(void) 83 { 84 return -1; 85 } 86 87 #ifdef CONFIG_DISPLAY_BOARDINFO 88 int checkboard(void) 89 { 90 int board_id = tegra_board_id(); 91 92 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); 93 if (board_id != -1) 94 printf(", ID: %d\n", board_id); 95 printf("\n"); 96 97 return 0; 98 } 99 #endif /* CONFIG_DISPLAY_BOARDINFO */ 100 101 __weak int tegra_lcd_pmic_init(int board_it) 102 { 103 return 0; 104 } 105 106 __weak int nvidia_board_init(void) 107 { 108 return 0; 109 } 110 111 /* 112 * Routine: board_init 113 * Description: Early hardware init. 114 */ 115 int board_init(void) 116 { 117 __maybe_unused int err; 118 __maybe_unused int board_id; 119 120 /* Do clocks and UART first so that printf() works */ 121 clock_init(); 122 clock_verify(); 123 124 tegra_gpu_config(); 125 126 #ifdef CONFIG_TEGRA_SPI 127 pin_mux_spi(); 128 #endif 129 130 /* Init is handled automatically in the driver-model case */ 131 #if defined(CONFIG_DM_VIDEO) 132 pin_mux_display(); 133 #endif 134 /* boot param addr */ 135 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 136 137 power_det_init(); 138 139 #ifdef CONFIG_SYS_I2C_TEGRA 140 # ifdef CONFIG_TEGRA_PMU 141 if (pmu_set_nominal()) 142 debug("Failed to select nominal voltages\n"); 143 # ifdef CONFIG_TEGRA_CLOCK_SCALING 144 err = board_emc_init(); 145 if (err) 146 debug("Memory controller init failed: %d\n", err); 147 # endif 148 # endif /* CONFIG_TEGRA_PMU */ 149 #ifdef CONFIG_AS3722_POWER 150 err = as3722_init(NULL); 151 if (err && err != -ENODEV) 152 return err; 153 #endif 154 #endif /* CONFIG_SYS_I2C_TEGRA */ 155 156 #ifdef CONFIG_USB_EHCI_TEGRA 157 pin_mux_usb(); 158 #endif 159 160 #if defined(CONFIG_DM_VIDEO) 161 board_id = tegra_board_id(); 162 err = tegra_lcd_pmic_init(board_id); 163 if (err) 164 return err; 165 #endif 166 167 #ifdef CONFIG_TEGRA_NAND 168 pin_mux_nand(); 169 #endif 170 171 tegra_xusb_padctl_init(gd->fdt_blob); 172 173 #ifdef CONFIG_TEGRA_LP0 174 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ 175 warmboot_save_sdram_params(); 176 177 /* prepare the WB code to LP0 location */ 178 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); 179 #endif 180 return nvidia_board_init(); 181 } 182 183 #ifdef CONFIG_BOARD_EARLY_INIT_F 184 static void __gpio_early_init(void) 185 { 186 } 187 188 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); 189 190 int board_early_init_f(void) 191 { 192 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) 193 #define USBCMD_FS2 (1 << 15) 194 { 195 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; 196 writel(USBCMD_FS2, &usbctlr->usb_cmd); 197 } 198 #endif 199 200 /* Do any special system timer/TSC setup */ 201 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 202 if (!tegra_cpu_is_non_secure()) 203 #endif 204 arch_timer_init(); 205 206 pinmux_init(); 207 board_init_uart_f(); 208 209 /* Initialize periph GPIOs */ 210 gpio_early_init(); 211 gpio_early_init_uart(); 212 213 return 0; 214 } 215 #endif /* EARLY_INIT */ 216 217 int board_late_init(void) 218 { 219 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 220 if (tegra_cpu_is_non_secure()) { 221 printf("CPU is in NS mode\n"); 222 setenv("cpu_ns_mode", "1"); 223 } else { 224 setenv("cpu_ns_mode", ""); 225 } 226 #endif 227 start_cpu_fan(); 228 229 return 0; 230 } 231 232 #if defined(CONFIG_TEGRA_MMC) 233 __weak void pin_mux_mmc(void) 234 { 235 } 236 237 /* this is a weak define that we are overriding */ 238 int board_mmc_init(bd_t *bd) 239 { 240 debug("%s called\n", __func__); 241 242 /* Enable muxes, etc. for SDMMC controllers */ 243 pin_mux_mmc(); 244 245 debug("%s: init MMC\n", __func__); 246 tegra_mmc_init(); 247 248 return 0; 249 } 250 #endif /* MMC */ 251 252 /* 253 * In some SW environments, a memory carve-out exists to house a secure 254 * monitor, a trusted OS, and/or various statically allocated media buffers. 255 * 256 * This carveout exists at the highest possible address that is within a 257 * 32-bit physical address space. 258 * 259 * This function returns the total size of this carve-out. At present, the 260 * returned value is hard-coded for simplicity. In the future, it may be 261 * possible to determine the carve-out size: 262 * - By querying some run-time information source, such as: 263 * - A structure passed to U-Boot by earlier boot software. 264 * - SoC registers. 265 * - A call into the secure monitor. 266 * - In the per-board U-Boot configuration header, based on knowledge of the 267 * SW environment that U-Boot is being built for. 268 * 269 * For now, we support two configurations in U-Boot: 270 * - 32-bit ports without any form of carve-out. 271 * - 64 bit ports which are assumed to use a carve-out of a conservatively 272 * hard-coded size. 273 */ 274 static ulong carveout_size(void) 275 { 276 #ifdef CONFIG_ARM64 277 return SZ_512M; 278 #else 279 return 0; 280 #endif 281 } 282 283 /* 284 * Determine the amount of usable RAM below 4GiB, taking into account any 285 * carve-out that may be assigned. 286 */ 287 static ulong usable_ram_size_below_4g(void) 288 { 289 ulong total_size_below_4g; 290 ulong usable_size_below_4g; 291 292 /* 293 * The total size of RAM below 4GiB is the lesser address of: 294 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). 295 * (b) The size RAM physically present in the system. 296 */ 297 if (gd->ram_size < SZ_2G) 298 total_size_below_4g = gd->ram_size; 299 else 300 total_size_below_4g = SZ_2G; 301 302 /* Calculate usable RAM by subtracting out any carve-out size */ 303 usable_size_below_4g = total_size_below_4g - carveout_size(); 304 305 return usable_size_below_4g; 306 } 307 308 /* 309 * Represent all available RAM in either one or two banks. 310 * 311 * The first bank describes any usable RAM below 4GiB. 312 * The second bank describes any RAM above 4GiB. 313 * 314 * This split is driven by the following requirements: 315 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg 316 * property for memory below and above the 4GiB boundary. The layout of that 317 * DT property is directly driven by the entries in the U-Boot bank array. 318 * - The potential existence of a carve-out at the end of RAM below 4GiB can 319 * only be represented using multiple banks. 320 * 321 * Explicitly removing the carve-out RAM from the bank entries makes the RAM 322 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot 323 * command-line. 324 * 325 * This does mean that the DT U-Boot passes to the Linux kernel will not 326 * include this RAM in /memory/reg at all. An alternative would be to include 327 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node 328 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the 329 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU 330 * mapping, so either way is acceptable. 331 * 332 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the 333 * start address of that bank cannot be represented in the 32-bit .size 334 * field. 335 */ 336 void dram_init_banksize(void) 337 { 338 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 339 gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); 340 341 #ifdef CONFIG_PCI 342 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; 343 #endif 344 345 #ifdef CONFIG_PHYS_64BIT 346 if (gd->ram_size > SZ_2G) { 347 gd->bd->bi_dram[1].start = 0x100000000; 348 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; 349 } else 350 #endif 351 { 352 gd->bd->bi_dram[1].start = 0; 353 gd->bd->bi_dram[1].size = 0; 354 } 355 } 356 357 /* 358 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower 359 * 32-bits of the physical address space. Cap the maximum usable RAM area 360 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit 361 * boundary that most devices can address. Also, don't let U-Boot use any 362 * carve-out, as mentioned above. 363 * 364 * This function is called before dram_init_banksize(), so we can't simply 365 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. 366 */ 367 ulong board_get_usable_ram_top(ulong total_size) 368 { 369 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); 370 } 371