1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 #define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS 14 15 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 16 17 #define CONFIG_SYS_FSL_CLK 18 19 #define CONFIG_DISPLAY_CPUINFO 20 #define CONFIG_DISPLAY_BOARDINFO 21 22 #define CONFIG_SKIP_LOWLEVEL_INIT 23 #define CONFIG_BOARD_EARLY_INIT_F 24 #define CONFIG_DEEP_SLEEP 25 #ifdef CONFIG_DEEP_SLEEP 26 #define CONFIG_SILENT_CONSOLE 27 #endif 28 29 /* 30 * Size of malloc() pool 31 */ 32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 33 34 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 35 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 36 37 /* 38 * USB 39 */ 40 41 /* 42 * EHCI Support - disbaled by default as 43 * there is no signal coming out of soc on 44 * this board for this controller. However, 45 * the silicon still has this controller, 46 * and anyone can use this controller by 47 * taking signals out on their board. 48 */ 49 50 /*#define CONFIG_HAS_FSL_DR_USB*/ 51 52 #ifdef CONFIG_HAS_FSL_DR_USB 53 #define CONFIG_USB_EHCI 54 #define CONFIG_USB_EHCI_FSL 55 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 56 #endif 57 58 /* XHCI Support - enabled by default */ 59 #define CONFIG_HAS_FSL_XHCI_USB 60 61 #ifdef CONFIG_HAS_FSL_XHCI_USB 62 #define CONFIG_USB_XHCI_FSL 63 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 64 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 65 #endif 66 67 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) 68 #define CONFIG_USB_STORAGE 69 #endif 70 71 /* 72 * Generic Timer Definitions 73 */ 74 #define GENERIC_TIMER_CLK 12500000 75 76 #define CONFIG_SYS_CLK_FREQ 100000000 77 #define CONFIG_DDR_CLK_FREQ 100000000 78 79 #define DDR_SDRAM_CFG 0x470c0008 80 #define DDR_CS0_BNDS 0x008000bf 81 #define DDR_CS0_CONFIG 0x80014302 82 #define DDR_TIMING_CFG_0 0x50550004 83 #define DDR_TIMING_CFG_1 0xbcb38c56 84 #define DDR_TIMING_CFG_2 0x0040d120 85 #define DDR_TIMING_CFG_3 0x010e1000 86 #define DDR_TIMING_CFG_4 0x00000001 87 #define DDR_TIMING_CFG_5 0x03401400 88 #define DDR_SDRAM_CFG_2 0x00401010 89 #define DDR_SDRAM_MODE 0x00061c60 90 #define DDR_SDRAM_MODE_2 0x00180000 91 #define DDR_SDRAM_INTERVAL 0x18600618 92 #define DDR_DDR_WRLVL_CNTL 0x8655f605 93 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 94 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 95 #define DDR_DDR_CDR1 0x80040000 96 #define DDR_DDR_CDR2 0x00000001 97 #define DDR_SDRAM_CLK_CNTL 0x02000000 98 #define DDR_DDR_ZQ_CNTL 0x89080600 99 #define DDR_CS0_CONFIG_2 0 100 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 101 #define SDRAM_CFG2_D_INIT 0x00000010 102 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 103 #define SDRAM_CFG2_FRC_SR 0x80000000 104 #define SDRAM_CFG_BI 0x00000001 105 106 #ifdef CONFIG_RAMBOOT_PBL 107 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 108 #endif 109 110 #ifdef CONFIG_SD_BOOT 111 #ifdef CONFIG_SD_BOOT_QSPI 112 #define CONFIG_SYS_FSL_PBL_RCW \ 113 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 114 #else 115 #define CONFIG_SYS_FSL_PBL_RCW \ 116 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 117 #endif 118 #define CONFIG_SPL_FRAMEWORK 119 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 120 #define CONFIG_SPL_LIBCOMMON_SUPPORT 121 #define CONFIG_SPL_LIBGENERIC_SUPPORT 122 #define CONFIG_SPL_ENV_SUPPORT 123 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 124 #define CONFIG_SPL_I2C_SUPPORT 125 #define CONFIG_SPL_WATCHDOG_SUPPORT 126 #define CONFIG_SPL_SERIAL_SUPPORT 127 #define CONFIG_SPL_MMC_SUPPORT 128 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 129 130 #ifdef CONFIG_SECURE_BOOT 131 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 132 /* 133 * HDR would be appended at end of image and copied to DDR along 134 * with U-Boot image. 135 */ 136 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ 137 (CONFIG_U_BOOT_HDR_SIZE / 512) 138 #else 139 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 140 #endif /* ifdef CONFIG_SECURE_BOOT */ 141 142 #define CONFIG_SPL_TEXT_BASE 0x10000000 143 #define CONFIG_SPL_MAX_SIZE 0x1a000 144 #define CONFIG_SPL_STACK 0x1001d000 145 #define CONFIG_SPL_PAD_TO 0x1c000 146 #define CONFIG_SYS_TEXT_BASE 0x82000000 147 148 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 149 CONFIG_SYS_MONITOR_LEN) 150 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 151 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 152 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 153 154 #ifdef CONFIG_U_BOOT_HDR_SIZE 155 /* 156 * HDR would be appended at end of image and copied to DDR along 157 * with U-Boot image. Here u-boot max. size is 512K. So if binary 158 * size increases then increase this size in case of secure boot as 159 * it uses raw u-boot image instead of fit image. 160 */ 161 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) 162 #else 163 #define CONFIG_SYS_MONITOR_LEN 0x80000 164 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 165 #endif 166 167 #ifdef CONFIG_QSPI_BOOT 168 #define CONFIG_SYS_TEXT_BASE 0x40010000 169 #endif 170 171 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 172 #define CONFIG_SYS_NO_FLASH 173 #endif 174 175 #ifndef CONFIG_SYS_TEXT_BASE 176 #define CONFIG_SYS_TEXT_BASE 0x60100000 177 #endif 178 179 #define CONFIG_NR_DRAM_BANKS 1 180 #define PHYS_SDRAM 0x80000000 181 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 182 183 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 184 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 185 186 #define CONFIG_SYS_HAS_SERDES 187 188 #define CONFIG_FSL_CAAM /* Enable CAAM */ 189 190 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 191 !defined(CONFIG_QSPI_BOOT) 192 #define CONFIG_U_QE 193 #endif 194 195 /* 196 * IFC Definitions 197 */ 198 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 199 #define CONFIG_FSL_IFC 200 #define CONFIG_SYS_FLASH_BASE 0x60000000 201 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 202 203 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 204 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 205 CSPR_PORT_SIZE_16 | \ 206 CSPR_MSEL_NOR | \ 207 CSPR_V) 208 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 209 210 /* NOR Flash Timing Params */ 211 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 212 CSOR_NOR_TRHZ_80) 213 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 214 FTIM0_NOR_TEADC(0x5) | \ 215 FTIM0_NOR_TAVDS(0x0) | \ 216 FTIM0_NOR_TEAHC(0x5)) 217 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 218 FTIM1_NOR_TRAD_NOR(0x1A) | \ 219 FTIM1_NOR_TSEQRAD_NOR(0x13)) 220 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 221 FTIM2_NOR_TCH(0x4) | \ 222 FTIM2_NOR_TWP(0x1c) | \ 223 FTIM2_NOR_TWPH(0x0e)) 224 #define CONFIG_SYS_NOR_FTIM3 0 225 226 #define CONFIG_FLASH_CFI_DRIVER 227 #define CONFIG_SYS_FLASH_CFI 228 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 229 #define CONFIG_SYS_FLASH_QUIET_TEST 230 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 231 232 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 233 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 234 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 235 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 236 237 #define CONFIG_SYS_FLASH_EMPTY_INFO 238 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 239 240 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 241 #define CONFIG_SYS_WRITE_SWAPPED_DATA 242 #endif 243 244 /* CPLD */ 245 246 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 247 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 248 249 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 250 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 251 CSPR_PORT_SIZE_8 | \ 252 CSPR_MSEL_GPCM | \ 253 CSPR_V) 254 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 255 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 256 CSOR_NOR_NOR_MODE_AVD_NOR | \ 257 CSOR_NOR_TRHZ_80) 258 259 /* CPLD Timing parameters for IFC GPCM */ 260 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 261 FTIM0_GPCM_TEADC(0xf) | \ 262 FTIM0_GPCM_TEAHC(0xf)) 263 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 264 FTIM1_GPCM_TRAD(0x3f)) 265 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 266 FTIM2_GPCM_TCH(0xf) | \ 267 FTIM2_GPCM_TWP(0xff)) 268 #define CONFIG_SYS_FPGA_FTIM3 0x0 269 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 270 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 271 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 272 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 273 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 274 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 275 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 276 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 277 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 278 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 279 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 280 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 281 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 282 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 283 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 284 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 285 286 /* 287 * Serial Port 288 */ 289 #ifdef CONFIG_LPUART 290 #define CONFIG_LPUART_32B_REG 291 #else 292 #define CONFIG_CONS_INDEX 1 293 #define CONFIG_SYS_NS16550_SERIAL 294 #ifndef CONFIG_DM_SERIAL 295 #define CONFIG_SYS_NS16550_REG_SIZE 1 296 #endif 297 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 298 #endif 299 300 #define CONFIG_BAUDRATE 115200 301 302 /* 303 * I2C 304 */ 305 #define CONFIG_SYS_I2C 306 #define CONFIG_SYS_I2C_MXC 307 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 308 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 309 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 310 311 /* EEPROM */ 312 #define CONFIG_ID_EEPROM 313 #define CONFIG_SYS_I2C_EEPROM_NXID 314 #define CONFIG_SYS_EEPROM_BUS_NUM 1 315 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 316 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 317 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 318 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 319 320 /* 321 * MMC 322 */ 323 #define CONFIG_MMC 324 #define CONFIG_FSL_ESDHC 325 #define CONFIG_GENERIC_MMC 326 327 #define CONFIG_DOS_PARTITION 328 329 /* SPI */ 330 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 331 /* QSPI */ 332 #define QSPI0_AMBA_BASE 0x40000000 333 #define FSL_QSPI_FLASH_SIZE (1 << 24) 334 #define FSL_QSPI_FLASH_NUM 2 335 336 /* DSPI */ 337 #endif 338 339 /* DM SPI */ 340 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 341 #define CONFIG_DM_SPI_FLASH 342 #endif 343 344 /* 345 * Video 346 */ 347 #define CONFIG_FSL_DCU_FB 348 349 #ifdef CONFIG_FSL_DCU_FB 350 #define CONFIG_VIDEO 351 #define CONFIG_CMD_BMP 352 #define CONFIG_CFB_CONSOLE 353 #define CONFIG_VGA_AS_SINGLE_DEVICE 354 #define CONFIG_VIDEO_LOGO 355 #define CONFIG_VIDEO_BMP_LOGO 356 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 357 358 #define CONFIG_FSL_DCU_SII9022A 359 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 360 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 361 #endif 362 363 /* 364 * eTSEC 365 */ 366 #define CONFIG_TSEC_ENET 367 368 #ifdef CONFIG_TSEC_ENET 369 #define CONFIG_MII 370 #define CONFIG_MII_DEFAULT_TSEC 1 371 #define CONFIG_TSEC1 1 372 #define CONFIG_TSEC1_NAME "eTSEC1" 373 #define CONFIG_TSEC2 1 374 #define CONFIG_TSEC2_NAME "eTSEC2" 375 #define CONFIG_TSEC3 1 376 #define CONFIG_TSEC3_NAME "eTSEC3" 377 378 #define TSEC1_PHY_ADDR 2 379 #define TSEC2_PHY_ADDR 0 380 #define TSEC3_PHY_ADDR 1 381 382 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 383 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 384 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 385 386 #define TSEC1_PHYIDX 0 387 #define TSEC2_PHYIDX 0 388 #define TSEC3_PHYIDX 0 389 390 #define CONFIG_ETHPRIME "eTSEC1" 391 392 #define CONFIG_PHY_GIGE 393 #define CONFIG_PHYLIB 394 #define CONFIG_PHY_ATHEROS 395 396 #define CONFIG_HAS_ETH0 397 #define CONFIG_HAS_ETH1 398 #define CONFIG_HAS_ETH2 399 #endif 400 401 /* PCIe */ 402 #define CONFIG_PCI /* Enable PCI/PCIE */ 403 #define CONFIG_PCIE1 /* PCIE controller 1 */ 404 #define CONFIG_PCIE2 /* PCIE controller 2 */ 405 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 406 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 407 408 #define CONFIG_SYS_PCI_64BIT 409 410 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 411 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 412 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 413 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 414 415 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 416 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 417 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 418 419 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 420 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 421 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 422 423 #ifdef CONFIG_PCI 424 #define CONFIG_PCI_PNP 425 #define CONFIG_PCI_SCAN_SHOW 426 #define CONFIG_CMD_PCI 427 #endif 428 429 #define CONFIG_CMDLINE_TAG 430 #define CONFIG_CMDLINE_EDITING 431 432 #define CONFIG_ARMV7_NONSEC 433 #define CONFIG_ARMV7_VIRT 434 #define CONFIG_PEN_ADDR_BIG_ENDIAN 435 #define CONFIG_LAYERSCAPE_NS_ACCESS 436 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 437 #define CONFIG_TIMER_CLK_FREQ 12500000 438 439 #define CONFIG_HWCONFIG 440 #define HWCONFIG_BUFFER_SIZE 256 441 442 #define CONFIG_FSL_DEVICE_DISABLE 443 444 445 #ifdef CONFIG_LPUART 446 #define CONFIG_EXTRA_ENV_SETTINGS \ 447 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 448 "initrd_high=0xffffffff\0" \ 449 "fdt_high=0xffffffff\0" 450 #else 451 #define CONFIG_EXTRA_ENV_SETTINGS \ 452 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 453 "initrd_high=0xffffffff\0" \ 454 "fdt_high=0xffffffff\0" 455 #endif 456 457 /* 458 * Miscellaneous configurable options 459 */ 460 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 461 #define CONFIG_AUTO_COMPLETE 462 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 463 #define CONFIG_SYS_PBSIZE \ 464 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 465 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 466 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 467 468 #define CONFIG_SYS_MEMTEST_START 0x80000000 469 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 470 471 #define CONFIG_SYS_LOAD_ADDR 0x82000000 472 473 #define CONFIG_LS102XA_STREAM_ID 474 475 /* 476 * Stack sizes 477 * The stack sizes are set up in start.S using the settings below 478 */ 479 #define CONFIG_STACKSIZE (30 * 1024) 480 481 #define CONFIG_SYS_INIT_SP_OFFSET \ 482 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 483 #define CONFIG_SYS_INIT_SP_ADDR \ 484 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 485 486 #ifdef CONFIG_SPL_BUILD 487 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 488 #else 489 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 490 #endif 491 492 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 493 494 /* 495 * Environment 496 */ 497 #define CONFIG_ENV_OVERWRITE 498 499 #if defined(CONFIG_SD_BOOT) 500 #define CONFIG_ENV_OFFSET 0x100000 501 #define CONFIG_ENV_IS_IN_MMC 502 #define CONFIG_SYS_MMC_ENV_DEV 0 503 #define CONFIG_ENV_SIZE 0x20000 504 #elif defined(CONFIG_QSPI_BOOT) 505 #define CONFIG_ENV_IS_IN_SPI_FLASH 506 #define CONFIG_ENV_SIZE 0x2000 507 #define CONFIG_ENV_OFFSET 0x100000 508 #define CONFIG_ENV_SECT_SIZE 0x10000 509 #else 510 #define CONFIG_ENV_IS_IN_FLASH 511 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 512 #define CONFIG_ENV_SIZE 0x20000 513 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 514 #endif 515 516 #define CONFIG_MISC_INIT_R 517 518 /* Hash command with SHA acceleration supported in hardware */ 519 #ifdef CONFIG_FSL_CAAM 520 #define CONFIG_CMD_HASH 521 #define CONFIG_SHA_HW_ACCEL 522 #endif 523 524 #include <asm/fsl_secure_boot.h> 525 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 526 527 #endif 528