| 2166f9f3 | 31-Mar-2026 |
Yann Gautier <yann.gautier@st.com> |
fix(st-ddr): add missing newline
Add a missing \n at the end of an ERROR trace in ST DDR driver.
Change-Id: I11e602214c96f182dcae6f109926cc1baa1c6d82
Signed-off-by: Yann Gautier <yann.gautier@st.co
fix(st-ddr): add missing newline
Add a missing \n at the end of an ERROR trace in ST DDR driver.
Change-Id: I11e602214c96f182dcae6f109926cc1baa1c6d82
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 057f4f63 | 11-Dec-2024 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
fix(st-ddr): change retention disable management
DDR reset signal can have spurious behaviors because related constraints
are no more followed. Fix the initialization sequence to restore a
full comp
fix(st-ddr): change retention disable management
DDR reset signal can have spurious behaviors because related constraints
are no more followed. Fix the initialization sequence to restore a
full compliance with recommendations around the retention (ordering and
timings).
Change-Id: I481f00e61899292b0a5abad5a0dea5a660f285b4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
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| d5788839 | 19-Nov-2025 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
fix(st-ddr): manage semaphore with CID filtering
Disabling CID filtering clears the semaphore enabling.
If semaphore was enabled before CID filtering disable/enable sequence,
semaphore must be re-en
fix(st-ddr): manage semaphore with CID filtering
Disabling CID filtering clears the semaphore enabling.
If semaphore was enabled before CID filtering disable/enable sequence,
semaphore must be re-enabled after.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I1df056b8bebe279d8d97313e0c55a563d29cc09d
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| 74887d72 | 28-Mar-2024 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
fix(st-ddr): manage CID filtering when accessing PWR_CR11
There is no inheritance between PWR_CR11 and DDR RCC resources.
Disabling/re-enabling CID filtering of resource 104 (DDRCTRL)
before/after e
fix(st-ddr): manage CID filtering when accessing PWR_CR11
There is no inheritance between PWR_CR11 and DDR RCC resources.
Disabling/re-enabling CID filtering of resource 104 (DDRCTRL)
before/after each access of PWR_CR11 (read or write) fixes
this lack.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Iea4502c9ceccd3002b0f5004f5e32d5cce57c2ed
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| 6851fd9e | 09-Jan-2025 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
fix(st-ddr): bad refresh update level toggle sequence
wait_refresh_update_done_ack() must toggle RFSHCTL3_REFRESH_UPDATE_LEVEL
bit at each call to follow the recommended procedure.
Fix action and lo
fix(st-ddr): bad refresh update level toggle sequence
wait_refresh_update_done_ack() must toggle RFSHCTL3_REFRESH_UPDATE_LEVEL
bit at each call to follow the recommended procedure.
Fix action and loop condition.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: Iacf1e92a1ddaf2ab10e4f3a873be6ad1d3576e5f
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| 5dd1d544 | 10-Oct-2024 |
Maxime Méré <maxime.mere@foss.st.com> |
fix(st-ddr): fix coverity issue in ddrphyinit
Address issue CID 445362 and CID 445361 found during coverity scan.
Change-Id: I1ab460d2e1353b81517788e32de662f203b0352f
Signed-off-by: Maxime Méré <ma
fix(st-ddr): fix coverity issue in ddrphyinit
Address issue CID 445362 and CID 445361 found during coverity scan.
Change-Id: I1ab460d2e1353b81517788e32de662f203b0352f
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
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| d596023b | 08-Mar-2022 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
refactor(st-ddr): create generic services
Disabling AXI port, enabling host interface and both enabling/disabling
software self-refresh services are already present inside the driver
source code.
Fa
refactor(st-ddr): create generic services
Disabling AXI port, enabling host interface and both enabling/disabling
software self-refresh services are already present inside the driver
source code.
Factorize by gathering them as services inside the generic part,
and adapt driver to call these new functions.
Add services to manage quasi-dynamic registers. DDRCTRL contains
quasi-dynamic registers, which are dynamic only under some conditions
defined by the user guide (with 4 groups).
In our driver, out of reset state, only groups 3 and 4 are updated.
Group 4 needs only sw_done/sw_done_ack sequence, already available.
Group 3 sequence include more conditions, that are gathered in
specific services. stm32mp_ddr_disable_host_interface() has been added
to do this.
Add dedicated generic service to toggle rfshctl3.refresh_update_level
and wait for completion.
Manage AXI ports and HIF when updating QD3 registers. Quasi-dynamic
group 3 (QD3) registers are updated when DDR is not completely
initialized, i.e. when AXI ports are not enabled and possibly when
host interface (HIF) is not enabled too.
In that case, a specific mechanism is necessary to restore the same
conditions as before accessing QD3 registers.
Static functions have been added to get AXI ports and HIF states and
are used to determine the needed conditions to set/unset.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I880f88b1cb6fc76199ad9ea33e9d63a5c469aed4
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| 1483b3c3 | 29-May-2024 |
Yann Gautier <yann.gautier@st.com> |
refactor(st-ddr): remove name from stm32mp_ddr_reg_desc
It was only used for an error trace, with little added value. This
allows some gains in DDR driver data size.
Signed-off-by: Yann Gautier <ya
refactor(st-ddr): remove name from stm32mp_ddr_reg_desc
It was only used for an error trace, with little added value. This
allows some gains in DDR driver data size.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I02e2fc75efd90ff188e62f39850b9bd4c3af1649
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| 63d21598 | 02-Mar-2021 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
refactor(st-ddr): move basic tests in a dedicated file
These basic tests are generic and should be used independently of the
driver, depending on the plaftorm characteristics.
Change-Id: I38161b659
refactor(st-ddr): move basic tests in a dedicated file
These basic tests are generic and should be used independently of the
driver, depending on the plaftorm characteristics.
Change-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
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| 88f4fb8f | 17-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.
Change-Id
feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.
Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| ba7d2e26 | 25-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
refactor(st-ddr): update parameter array initialization
Force alignment of the size of parameters array with the expected
value by the binding.
The registers dynamic structs are removed as not used
refactor(st-ddr): update parameter array initialization
Force alignment of the size of parameters array with the expected
value by the binding.
The registers dynamic structs are removed as not used in TF-A.
Change-Id: I7a41f355a435f54fbf23f468cca87c7f8f7e69e8
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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