1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/cpu_data.h> 24 #include <lib/el3_runtime/pubsub_events.h> 25 #include <lib/extensions/amu.h> 26 #include <lib/extensions/brbe.h> 27 #include <lib/extensions/debug_v8p9.h> 28 #include <lib/extensions/fgt2.h> 29 #include <lib/extensions/mpam.h> 30 #include <lib/extensions/pmuv3.h> 31 #include <lib/extensions/sme.h> 32 #include <lib/extensions/spe.h> 33 #include <lib/extensions/sve.h> 34 #include <lib/extensions/sys_reg_trace.h> 35 #include <lib/extensions/trbe.h> 36 #include <lib/extensions/trf.h> 37 #include <lib/utils.h> 38 39 #if ENABLE_FEAT_TWED 40 /* Make sure delay value fits within the range(0-15) */ 41 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 42 #endif /* ENABLE_FEAT_TWED */ 43 44 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 45 static bool has_secure_perworld_init; 46 47 static void manage_extensions_common(cpu_context_t *ctx); 48 static void manage_extensions_nonsecure(cpu_context_t *ctx); 49 static void manage_extensions_secure(cpu_context_t *ctx); 50 static void manage_extensions_secure_per_world(void); 51 52 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 53 { 54 u_register_t sctlr_elx, actlr_elx; 55 56 /* 57 * Initialise SCTLR_EL1 to the reset value corresponding to the target 58 * execution state setting all fields rather than relying on the hw. 59 * Some fields have architecturally UNKNOWN reset values and these are 60 * set to zero. 61 * 62 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 63 * 64 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 65 * required by PSCI specification) 66 */ 67 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 68 if (GET_RW(ep->spsr) == MODE_RW_64) { 69 sctlr_elx |= SCTLR_EL1_RES1; 70 } else { 71 /* 72 * If the target execution state is AArch32 then the following 73 * fields need to be set. 74 * 75 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 76 * instructions are not trapped to EL1. 77 * 78 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 79 * instructions are not trapped to EL1. 80 * 81 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 82 * CP15DMB, CP15DSB, and CP15ISB instructions. 83 */ 84 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 85 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 86 } 87 88 #if ERRATA_A75_764081 89 /* 90 * If workaround of errata 764081 for Cortex-A75 is used then set 91 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 92 */ 93 sctlr_elx |= SCTLR_IESB_BIT; 94 #endif 95 96 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 97 #if (ERRATA_SPECULATIVE_AT) 98 write_ctx_reg(get_errata_speculative_at_ctx(ctx), CTX_ERRATA_SPEC_AT_SCTLR_EL1, sctlr_elx); 99 #else 100 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), sctlr_el1, sctlr_elx); 101 #endif /* ERRATA_SPECULATIVE_AT */ 102 103 /* 104 * Base the context ACTLR_EL1 on the current value, as it is 105 * implementation defined. The context restore process will write 106 * the value from the context to the actual register and can cause 107 * problems for processor cores that don't expect certain bits to 108 * be zero. 109 */ 110 actlr_elx = read_actlr_el1(); 111 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 112 } 113 114 /****************************************************************************** 115 * This function performs initializations that are specific to SECURE state 116 * and updates the cpu context specified by 'ctx'. 117 *****************************************************************************/ 118 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 119 { 120 u_register_t scr_el3; 121 el3_state_t *state; 122 123 state = get_el3state_ctx(ctx); 124 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 125 126 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 127 /* 128 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 129 * indicated by the interrupt routing model for BL31. 130 */ 131 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 132 #endif 133 134 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 135 if (is_feat_mte2_supported()) { 136 scr_el3 |= SCR_ATA_BIT; 137 } 138 139 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 140 141 /* 142 * Initialize EL1 context registers unless SPMC is running 143 * at S-EL2. 144 */ 145 #if !SPMD_SPM_AT_SEL2 146 setup_el1_context(ctx, ep); 147 #endif 148 149 manage_extensions_secure(ctx); 150 151 /** 152 * manage_extensions_secure_per_world api has to be executed once, 153 * as the registers getting initialised, maintain constant value across 154 * all the cpus for the secure world. 155 * Henceforth, this check ensures that the registers are initialised once 156 * and avoids re-initialization from multiple cores. 157 */ 158 if (!has_secure_perworld_init) { 159 manage_extensions_secure_per_world(); 160 } 161 162 } 163 164 #if ENABLE_RME 165 /****************************************************************************** 166 * This function performs initializations that are specific to REALM state 167 * and updates the cpu context specified by 'ctx'. 168 *****************************************************************************/ 169 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 170 { 171 u_register_t scr_el3; 172 el3_state_t *state; 173 174 state = get_el3state_ctx(ctx); 175 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 176 177 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 178 179 /* CSV2 version 2 and above */ 180 if (is_feat_csv2_2_supported()) { 181 /* Enable access to the SCXTNUM_ELx registers. */ 182 scr_el3 |= SCR_EnSCXT_BIT; 183 } 184 185 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 186 } 187 #endif /* ENABLE_RME */ 188 189 /****************************************************************************** 190 * This function performs initializations that are specific to NON-SECURE state 191 * and updates the cpu context specified by 'ctx'. 192 *****************************************************************************/ 193 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 194 { 195 u_register_t scr_el3; 196 el3_state_t *state; 197 198 state = get_el3state_ctx(ctx); 199 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 200 201 /* SCR_NS: Set the NS bit */ 202 scr_el3 |= SCR_NS_BIT; 203 204 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 205 if (is_feat_mte2_supported()) { 206 scr_el3 |= SCR_ATA_BIT; 207 } 208 209 #if !CTX_INCLUDE_PAUTH_REGS 210 /* 211 * Pointer Authentication feature, if present, is always enabled by default 212 * for Non secure lower exception levels. We do not have an explicit 213 * flag to set it. 214 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 215 * exception levels of secure and realm worlds. 216 * 217 * To prevent the leakage between the worlds during world switch, 218 * we enable it only for the non-secure world. 219 * 220 * If the Secure/realm world wants to use pointer authentication, 221 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 222 * it will be enabled globally for all the contexts. 223 * 224 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 225 * other than EL3 226 * 227 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 228 * than EL3 229 */ 230 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 231 232 #endif /* CTX_INCLUDE_PAUTH_REGS */ 233 234 #if HANDLE_EA_EL3_FIRST_NS 235 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 236 scr_el3 |= SCR_EA_BIT; 237 #endif 238 239 #if RAS_TRAP_NS_ERR_REC_ACCESS 240 /* 241 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 242 * and RAS ERX registers from EL1 and EL2(from any security state) 243 * are trapped to EL3. 244 * Set here to trap only for NS EL1/EL2 245 * 246 */ 247 scr_el3 |= SCR_TERR_BIT; 248 #endif 249 250 /* CSV2 version 2 and above */ 251 if (is_feat_csv2_2_supported()) { 252 /* Enable access to the SCXTNUM_ELx registers. */ 253 scr_el3 |= SCR_EnSCXT_BIT; 254 } 255 256 #ifdef IMAGE_BL31 257 /* 258 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 259 * indicated by the interrupt routing model for BL31. 260 */ 261 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 262 #endif 263 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 264 265 /* Initialize EL1 context registers */ 266 setup_el1_context(ctx, ep); 267 268 /* Initialize EL2 context registers */ 269 #if CTX_INCLUDE_EL2_REGS 270 271 /* 272 * Initialize SCTLR_EL2 context register with reset value. 273 */ 274 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 275 276 if (is_feat_hcx_supported()) { 277 /* 278 * Initialize register HCRX_EL2 with its init value. 279 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 280 * chance that this can lead to unexpected behavior in lower 281 * ELs that have not been updated since the introduction of 282 * this feature if not properly initialized, especially when 283 * it comes to those bits that enable/disable traps. 284 */ 285 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 286 HCRX_EL2_INIT_VAL); 287 } 288 289 if (is_feat_fgt_supported()) { 290 /* 291 * Initialize HFG*_EL2 registers with a default value so legacy 292 * systems unaware of FEAT_FGT do not get trapped due to their lack 293 * of initialization for this feature. 294 */ 295 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 296 HFGITR_EL2_INIT_VAL); 297 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 298 HFGRTR_EL2_INIT_VAL); 299 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 300 HFGWTR_EL2_INIT_VAL); 301 } 302 303 #endif /* CTX_INCLUDE_EL2_REGS */ 304 305 manage_extensions_nonsecure(ctx); 306 } 307 308 /******************************************************************************* 309 * The following function performs initialization of the cpu_context 'ctx' 310 * for first use that is common to all security states, and sets the 311 * initial entrypoint state as specified by the entry_point_info structure. 312 * 313 * The EE and ST attributes are used to configure the endianness and secure 314 * timer availability for the new execution context. 315 ******************************************************************************/ 316 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 317 { 318 u_register_t scr_el3; 319 u_register_t mdcr_el3; 320 el3_state_t *state; 321 gp_regs_t *gp_regs; 322 323 state = get_el3state_ctx(ctx); 324 325 /* Clear any residual register values from the context */ 326 zeromem(ctx, sizeof(*ctx)); 327 328 /* 329 * The lower-EL context is zeroed so that no stale values leak to a world. 330 * It is assumed that an all-zero lower-EL context is good enough for it 331 * to boot correctly. However, there are very few registers where this 332 * is not true and some values need to be recreated. 333 */ 334 #if CTX_INCLUDE_EL2_REGS 335 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 336 337 /* 338 * These bits are set in the gicv3 driver. Losing them (especially the 339 * SRE bit) is problematic for all worlds. Henceforth recreate them. 340 */ 341 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 342 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 343 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 344 345 /* 346 * The actlr_el2 register can be initialized in platform's reset handler 347 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 348 */ 349 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 350 #endif /* CTX_INCLUDE_EL2_REGS */ 351 352 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 353 scr_el3 = SCR_RESET_VAL; 354 355 /* 356 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 357 * EL2, EL1 and EL0 are not trapped to EL3. 358 * 359 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 360 * EL2, EL1 and EL0 are not trapped to EL3. 361 * 362 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 363 * both Security states and both Execution states. 364 * 365 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 366 * Non-secure memory. 367 */ 368 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 369 370 scr_el3 |= SCR_SIF_BIT; 371 372 /* 373 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 374 * Exception level as specified by SPSR. 375 */ 376 if (GET_RW(ep->spsr) == MODE_RW_64) { 377 scr_el3 |= SCR_RW_BIT; 378 } 379 380 /* 381 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 382 * Secure timer registers to EL3, from AArch64 state only, if specified 383 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 384 * bit always behaves as 1 (i.e. secure physical timer register access 385 * is not trapped) 386 */ 387 if (EP_GET_ST(ep->h.attr) != 0U) { 388 scr_el3 |= SCR_ST_BIT; 389 } 390 391 /* 392 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 393 * SCR_EL3.HXEn. 394 */ 395 if (is_feat_hcx_supported()) { 396 scr_el3 |= SCR_HXEn_BIT; 397 } 398 399 /* 400 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 401 * registers are trapped to EL3. 402 */ 403 #if ENABLE_FEAT_RNG_TRAP 404 scr_el3 |= SCR_TRNDR_BIT; 405 #endif 406 407 #if FAULT_INJECTION_SUPPORT 408 /* Enable fault injection from lower ELs */ 409 scr_el3 |= SCR_FIEN_BIT; 410 #endif 411 412 #if CTX_INCLUDE_PAUTH_REGS 413 /* 414 * Enable Pointer Authentication globally for all the worlds. 415 * 416 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 417 * other than EL3 418 * 419 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 420 * than EL3 421 */ 422 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 423 #endif /* CTX_INCLUDE_PAUTH_REGS */ 424 425 /* 426 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 427 */ 428 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 429 scr_el3 |= SCR_TCR2EN_BIT; 430 } 431 432 /* 433 * SCR_EL3.PIEN: Enable permission indirection and overlay 434 * registers for AArch64 if present. 435 */ 436 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 437 scr_el3 |= SCR_PIEN_BIT; 438 } 439 440 /* 441 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 442 */ 443 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 444 scr_el3 |= SCR_GCSEn_BIT; 445 } 446 447 /* 448 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 449 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 450 * next mode is Hyp. 451 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 452 * same conditions as HVC instructions and when the processor supports 453 * ARMv8.6-FGT. 454 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 455 * CNTPOFF_EL2 register under the same conditions as HVC instructions 456 * and when the processor supports ECV. 457 */ 458 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 459 || ((GET_RW(ep->spsr) != MODE_RW_64) 460 && (GET_M32(ep->spsr) == MODE32_hyp))) { 461 scr_el3 |= SCR_HCE_BIT; 462 463 if (is_feat_fgt_supported()) { 464 scr_el3 |= SCR_FGTEN_BIT; 465 } 466 467 if (is_feat_ecv_supported()) { 468 scr_el3 |= SCR_ECVEN_BIT; 469 } 470 } 471 472 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 473 if (is_feat_twed_supported()) { 474 /* Set delay in SCR_EL3 */ 475 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 476 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 477 << SCR_TWEDEL_SHIFT); 478 479 /* Enable WFE delay */ 480 scr_el3 |= SCR_TWEDEn_BIT; 481 } 482 483 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 484 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 485 if (is_feat_sel2_supported()) { 486 scr_el3 |= SCR_EEL2_BIT; 487 } 488 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 489 490 /* 491 * Populate EL3 state so that we've the right context 492 * before doing ERET 493 */ 494 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 495 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 496 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 497 498 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 499 mdcr_el3 = MDCR_EL3_RESET_VAL; 500 501 /* --------------------------------------------------------------------- 502 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 503 * Some fields are architecturally UNKNOWN on reset. 504 * 505 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 506 * Debug exceptions, other than Breakpoint Instruction exceptions, are 507 * disabled from all ELs in Secure state. 508 * 509 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 510 * privileged debug from S-EL1. 511 * 512 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 513 * access to the powerdown debug registers do not trap to EL3. 514 * 515 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 516 * debug registers, other than those registers that are controlled by 517 * MDCR_EL3.TDOSA. 518 */ 519 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 520 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 521 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 522 523 /* 524 * Configure MDCR_EL3 register as applicable for each world 525 * (NS/Secure/Realm) context. 526 */ 527 manage_extensions_common(ctx); 528 529 /* 530 * Store the X0-X7 value from the entrypoint into the context 531 * Use memcpy as we are in control of the layout of the structures 532 */ 533 gp_regs = get_gpregs_ctx(ctx); 534 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 535 } 536 537 /******************************************************************************* 538 * Context management library initialization routine. This library is used by 539 * runtime services to share pointers to 'cpu_context' structures for secure 540 * non-secure and realm states. Management of the structures and their associated 541 * memory is not done by the context management library e.g. the PSCI service 542 * manages the cpu context used for entry from and exit to the non-secure state. 543 * The Secure payload dispatcher service manages the context(s) corresponding to 544 * the secure state. It also uses this library to get access to the non-secure 545 * state cpu context pointers. 546 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 547 * which will be used for programming an entry into a lower EL. The same context 548 * will be used to save state upon exception entry from that EL. 549 ******************************************************************************/ 550 void __init cm_init(void) 551 { 552 /* 553 * The context management library has only global data to initialize, but 554 * that will be done when the BSS is zeroed out. 555 */ 556 } 557 558 /******************************************************************************* 559 * This is the high-level function used to initialize the cpu_context 'ctx' for 560 * first use. It performs initializations that are common to all security states 561 * and initializations specific to the security state specified in 'ep' 562 ******************************************************************************/ 563 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 564 { 565 unsigned int security_state; 566 567 assert(ctx != NULL); 568 569 /* 570 * Perform initializations that are common 571 * to all security states 572 */ 573 setup_context_common(ctx, ep); 574 575 security_state = GET_SECURITY_STATE(ep->h.attr); 576 577 /* Perform security state specific initializations */ 578 switch (security_state) { 579 case SECURE: 580 setup_secure_context(ctx, ep); 581 break; 582 #if ENABLE_RME 583 case REALM: 584 setup_realm_context(ctx, ep); 585 break; 586 #endif 587 case NON_SECURE: 588 setup_ns_context(ctx, ep); 589 break; 590 default: 591 ERROR("Invalid security state\n"); 592 panic(); 593 break; 594 } 595 } 596 597 /******************************************************************************* 598 * Enable architecture extensions for EL3 execution. This function only updates 599 * registers in-place which are expected to either never change or be 600 * overwritten by el3_exit. 601 ******************************************************************************/ 602 #if IMAGE_BL31 603 void cm_manage_extensions_el3(void) 604 { 605 if (is_feat_amu_supported()) { 606 amu_init_el3(); 607 } 608 609 if (is_feat_sme_supported()) { 610 sme_init_el3(); 611 } 612 613 pmuv3_init_el3(); 614 } 615 #endif /* IMAGE_BL31 */ 616 617 /****************************************************************************** 618 * Function to initialise the registers with the RESET values in the context 619 * memory, which are maintained per world. 620 ******************************************************************************/ 621 #if IMAGE_BL31 622 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 623 { 624 /* 625 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 626 * 627 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 628 * by Advanced SIMD, floating-point or SVE instructions (if 629 * implemented) do not trap to EL3. 630 * 631 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 632 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 633 */ 634 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 635 636 per_world_ctx->ctx_cptr_el3 = cptr_el3; 637 638 /* 639 * Initialize MPAM3_EL3 to its default reset value 640 * 641 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 642 * all lower ELn MPAM3_EL3 register access to, trap to EL3 643 */ 644 645 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 646 } 647 #endif /* IMAGE_BL31 */ 648 649 /******************************************************************************* 650 * Initialise per_world_context for Non-Secure world. 651 * This function enables the architecture extensions, which have same value 652 * across the cores for the non-secure world. 653 ******************************************************************************/ 654 #if IMAGE_BL31 655 void manage_extensions_nonsecure_per_world(void) 656 { 657 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 658 659 if (is_feat_sme_supported()) { 660 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 661 } 662 663 if (is_feat_sve_supported()) { 664 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 665 } 666 667 if (is_feat_amu_supported()) { 668 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 669 } 670 671 if (is_feat_sys_reg_trace_supported()) { 672 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 673 } 674 675 if (is_feat_mpam_supported()) { 676 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 677 } 678 } 679 #endif /* IMAGE_BL31 */ 680 681 /******************************************************************************* 682 * Initialise per_world_context for Secure world. 683 * This function enables the architecture extensions, which have same value 684 * across the cores for the secure world. 685 ******************************************************************************/ 686 static void manage_extensions_secure_per_world(void) 687 { 688 #if IMAGE_BL31 689 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 690 691 if (is_feat_sme_supported()) { 692 693 if (ENABLE_SME_FOR_SWD) { 694 /* 695 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 696 * SME, SVE, and FPU/SIMD context properly managed. 697 */ 698 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 699 } else { 700 /* 701 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 702 * world can safely use the associated registers. 703 */ 704 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 705 } 706 } 707 if (is_feat_sve_supported()) { 708 if (ENABLE_SVE_FOR_SWD) { 709 /* 710 * Enable SVE and FPU in secure context, SPM must ensure 711 * that the SVE and FPU register contexts are properly managed. 712 */ 713 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 714 } else { 715 /* 716 * Disable SVE and FPU in secure context so non-secure world 717 * can safely use them. 718 */ 719 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 720 } 721 } 722 723 /* NS can access this but Secure shouldn't */ 724 if (is_feat_sys_reg_trace_supported()) { 725 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 726 } 727 728 has_secure_perworld_init = true; 729 #endif /* IMAGE_BL31 */ 730 } 731 732 /******************************************************************************* 733 * Enable architecture extensions on first entry to Non-secure world only 734 * and disable for secure world. 735 * 736 * NOTE: Arch features which have been provided with the capability of getting 737 * enabled only for non-secure world and being disabled for secure world are 738 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 739 ******************************************************************************/ 740 static void manage_extensions_common(cpu_context_t *ctx) 741 { 742 #if IMAGE_BL31 743 if (is_feat_spe_supported()) { 744 /* 745 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 746 */ 747 spe_enable(ctx); 748 } 749 750 if (is_feat_trbe_supported()) { 751 /* 752 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 753 * Realm state. 754 */ 755 trbe_enable(ctx); 756 } 757 758 if (is_feat_trf_supported()) { 759 /* 760 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 761 */ 762 trf_enable(ctx); 763 } 764 765 if (is_feat_brbe_supported()) { 766 /* 767 * Enable FEAT_BRBE for Non-Secure and prohibit for Secure state. 768 */ 769 brbe_enable(ctx); 770 } 771 #endif /* IMAGE_BL31 */ 772 } 773 774 /******************************************************************************* 775 * Enable architecture extensions on first entry to Non-secure world. 776 ******************************************************************************/ 777 static void manage_extensions_nonsecure(cpu_context_t *ctx) 778 { 779 #if IMAGE_BL31 780 if (is_feat_amu_supported()) { 781 amu_enable(ctx); 782 } 783 784 if (is_feat_sme_supported()) { 785 sme_enable(ctx); 786 } 787 788 if (is_feat_fgt2_supported()) { 789 fgt2_enable(ctx); 790 } 791 792 if (is_feat_debugv8p9_supported()) { 793 debugv8p9_extended_bp_wp_enable(ctx); 794 } 795 796 pmuv3_enable(ctx); 797 #endif /* IMAGE_BL31 */ 798 } 799 800 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 801 static __unused void enable_pauth_el2(void) 802 { 803 u_register_t hcr_el2 = read_hcr_el2(); 804 /* 805 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 806 * accessing key registers or using pointer authentication instructions 807 * from lower ELs. 808 */ 809 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 810 811 write_hcr_el2(hcr_el2); 812 } 813 814 #if INIT_UNUSED_NS_EL2 815 /******************************************************************************* 816 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 817 * world when EL2 is empty and unused. 818 ******************************************************************************/ 819 static void manage_extensions_nonsecure_el2_unused(void) 820 { 821 #if IMAGE_BL31 822 if (is_feat_spe_supported()) { 823 spe_init_el2_unused(); 824 } 825 826 if (is_feat_amu_supported()) { 827 amu_init_el2_unused(); 828 } 829 830 if (is_feat_mpam_supported()) { 831 mpam_init_el2_unused(); 832 } 833 834 if (is_feat_trbe_supported()) { 835 trbe_init_el2_unused(); 836 } 837 838 if (is_feat_sys_reg_trace_supported()) { 839 sys_reg_trace_init_el2_unused(); 840 } 841 842 if (is_feat_trf_supported()) { 843 trf_init_el2_unused(); 844 } 845 846 pmuv3_init_el2_unused(); 847 848 if (is_feat_sve_supported()) { 849 sve_init_el2_unused(); 850 } 851 852 if (is_feat_sme_supported()) { 853 sme_init_el2_unused(); 854 } 855 856 #if ENABLE_PAUTH 857 enable_pauth_el2(); 858 #endif /* ENABLE_PAUTH */ 859 #endif /* IMAGE_BL31 */ 860 } 861 #endif /* INIT_UNUSED_NS_EL2 */ 862 863 /******************************************************************************* 864 * Enable architecture extensions on first entry to Secure world. 865 ******************************************************************************/ 866 static void manage_extensions_secure(cpu_context_t *ctx) 867 { 868 #if IMAGE_BL31 869 if (is_feat_sme_supported()) { 870 if (ENABLE_SME_FOR_SWD) { 871 /* 872 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 873 * must ensure SME, SVE, and FPU/SIMD context properly managed. 874 */ 875 sme_init_el3(); 876 sme_enable(ctx); 877 } else { 878 /* 879 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 880 * world can safely use the associated registers. 881 */ 882 sme_disable(ctx); 883 } 884 } 885 #endif /* IMAGE_BL31 */ 886 } 887 888 #if !IMAGE_BL1 889 /******************************************************************************* 890 * The following function initializes the cpu_context for a CPU specified by 891 * its `cpu_idx` for first use, and sets the initial entrypoint state as 892 * specified by the entry_point_info structure. 893 ******************************************************************************/ 894 void cm_init_context_by_index(unsigned int cpu_idx, 895 const entry_point_info_t *ep) 896 { 897 cpu_context_t *ctx; 898 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 899 cm_setup_context(ctx, ep); 900 } 901 #endif /* !IMAGE_BL1 */ 902 903 /******************************************************************************* 904 * The following function initializes the cpu_context for the current CPU 905 * for first use, and sets the initial entrypoint state as specified by the 906 * entry_point_info structure. 907 ******************************************************************************/ 908 void cm_init_my_context(const entry_point_info_t *ep) 909 { 910 cpu_context_t *ctx; 911 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 912 cm_setup_context(ctx, ep); 913 } 914 915 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 916 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 917 { 918 #if INIT_UNUSED_NS_EL2 919 u_register_t hcr_el2 = HCR_RESET_VAL; 920 u_register_t mdcr_el2; 921 u_register_t scr_el3; 922 923 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 924 925 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 926 if ((scr_el3 & SCR_RW_BIT) != 0U) { 927 hcr_el2 |= HCR_RW_BIT; 928 } 929 930 write_hcr_el2(hcr_el2); 931 932 /* 933 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 934 * All fields have architecturally UNKNOWN reset values. 935 */ 936 write_cptr_el2(CPTR_EL2_RESET_VAL); 937 938 /* 939 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 940 * reset and are set to zero except for field(s) listed below. 941 * 942 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 943 * Non-secure EL0 and EL1 accesses to the physical timer registers. 944 * 945 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 946 * Non-secure EL0 and EL1 accesses to the physical counter registers. 947 */ 948 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 949 950 /* 951 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 952 * UNKNOWN value. 953 */ 954 write_cntvoff_el2(0); 955 956 /* 957 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 958 * respectively. 959 */ 960 write_vpidr_el2(read_midr_el1()); 961 write_vmpidr_el2(read_mpidr_el1()); 962 963 /* 964 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 965 * 966 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 967 * translation is disabled, cache maintenance operations depend on the 968 * VMID. 969 * 970 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 971 * disabled. 972 */ 973 write_vttbr_el2(VTTBR_RESET_VAL & 974 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 975 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 976 977 /* 978 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 979 * Some fields are architecturally UNKNOWN on reset. 980 * 981 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 982 * register accesses to the Debug ROM registers are not trapped to EL2. 983 * 984 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 985 * accesses to the powerdown debug registers are not trapped to EL2. 986 * 987 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 988 * debug registers do not trap to EL2. 989 * 990 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 991 * EL2. 992 */ 993 mdcr_el2 = MDCR_EL2_RESET_VAL & 994 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 995 MDCR_EL2_TDE_BIT); 996 997 write_mdcr_el2(mdcr_el2); 998 999 /* 1000 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1001 * 1002 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1003 * EL1 accesses to System registers do not trap to EL2. 1004 */ 1005 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1006 1007 /* 1008 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1009 * reset. 1010 * 1011 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1012 * and prevent timer interrupts. 1013 */ 1014 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1015 1016 manage_extensions_nonsecure_el2_unused(); 1017 #endif /* INIT_UNUSED_NS_EL2 */ 1018 } 1019 1020 /******************************************************************************* 1021 * Prepare the CPU system registers for first entry into realm, secure, or 1022 * normal world. 1023 * 1024 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1025 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1026 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1027 * For all entries, the EL1 registers are initialized from the cpu_context 1028 ******************************************************************************/ 1029 void cm_prepare_el3_exit(uint32_t security_state) 1030 { 1031 u_register_t sctlr_el2, scr_el3; 1032 cpu_context_t *ctx = cm_get_context(security_state); 1033 1034 assert(ctx != NULL); 1035 1036 if (security_state == NON_SECURE) { 1037 uint64_t el2_implemented = el_implemented(2); 1038 1039 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1040 CTX_SCR_EL3); 1041 1042 if (el2_implemented != EL_IMPL_NONE) { 1043 1044 /* 1045 * If context is not being used for EL2, initialize 1046 * HCRX_EL2 with its init value here. 1047 */ 1048 if (is_feat_hcx_supported()) { 1049 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1050 } 1051 1052 /* 1053 * Initialize Fine-grained trap registers introduced 1054 * by FEAT_FGT so all traps are initially disabled when 1055 * switching to EL2 or a lower EL, preventing undesired 1056 * behavior. 1057 */ 1058 if (is_feat_fgt_supported()) { 1059 /* 1060 * Initialize HFG*_EL2 registers with a default 1061 * value so legacy systems unaware of FEAT_FGT 1062 * do not get trapped due to their lack of 1063 * initialization for this feature. 1064 */ 1065 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1066 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1067 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1068 } 1069 1070 /* Condition to ensure EL2 is being used. */ 1071 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1072 /* Initialize SCTLR_EL2 register with reset value. */ 1073 sctlr_el2 = SCTLR_EL2_RES1; 1074 #if ERRATA_A75_764081 1075 /* 1076 * If workaround of errata 764081 for Cortex-A75 1077 * is used then set SCTLR_EL2.IESB to enable 1078 * Implicit Error Synchronization Barrier. 1079 */ 1080 sctlr_el2 |= SCTLR_IESB_BIT; 1081 #endif 1082 write_sctlr_el2(sctlr_el2); 1083 } else { 1084 /* 1085 * (scr_el3 & SCR_HCE_BIT==0) 1086 * EL2 implemented but unused. 1087 */ 1088 init_nonsecure_el2_unused(ctx); 1089 } 1090 } 1091 } 1092 cm_el1_sysregs_context_restore(security_state); 1093 cm_set_next_eret_context(security_state); 1094 } 1095 1096 #if CTX_INCLUDE_EL2_REGS 1097 1098 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1099 { 1100 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1101 if (is_feat_amu_supported()) { 1102 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1103 } 1104 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1105 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1106 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1107 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1108 } 1109 1110 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1111 { 1112 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1113 if (is_feat_amu_supported()) { 1114 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1115 } 1116 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1117 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1118 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1119 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1120 } 1121 1122 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1123 { 1124 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1125 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1126 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1127 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1128 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1129 } 1130 1131 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1132 { 1133 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1134 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1135 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1136 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1137 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1138 } 1139 1140 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1141 { 1142 u_register_t mpam_idr = read_mpamidr_el1(); 1143 1144 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1145 1146 /* 1147 * The context registers that we intend to save would be part of the 1148 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1149 */ 1150 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1151 return; 1152 } 1153 1154 /* 1155 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1156 * MPAMIDR_HAS_HCR_BIT == 1. 1157 */ 1158 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1159 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1160 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1161 1162 /* 1163 * The number of MPAMVPM registers is implementation defined, their 1164 * number is stored in the MPAMIDR_EL1 register. 1165 */ 1166 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1167 case 7: 1168 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1169 __fallthrough; 1170 case 6: 1171 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1172 __fallthrough; 1173 case 5: 1174 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1175 __fallthrough; 1176 case 4: 1177 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1178 __fallthrough; 1179 case 3: 1180 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1181 __fallthrough; 1182 case 2: 1183 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1184 __fallthrough; 1185 case 1: 1186 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1187 break; 1188 } 1189 } 1190 1191 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1192 { 1193 u_register_t mpam_idr = read_mpamidr_el1(); 1194 1195 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1196 1197 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1198 return; 1199 } 1200 1201 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1202 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1203 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1204 1205 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1206 case 7: 1207 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1208 __fallthrough; 1209 case 6: 1210 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1211 __fallthrough; 1212 case 5: 1213 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1214 __fallthrough; 1215 case 4: 1216 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1217 __fallthrough; 1218 case 3: 1219 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1220 __fallthrough; 1221 case 2: 1222 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1223 __fallthrough; 1224 case 1: 1225 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1226 break; 1227 } 1228 } 1229 1230 /* --------------------------------------------------------------------------- 1231 * The following registers are not added: 1232 * ICH_AP0R<n>_EL2 1233 * ICH_AP1R<n>_EL2 1234 * ICH_LR<n>_EL2 1235 * 1236 * NOTE: For a system with S-EL2 present but not enabled, accessing 1237 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1238 * SCR_EL3.NS = 1 before accessing this register. 1239 * --------------------------------------------------------------------------- 1240 */ 1241 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1242 { 1243 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1244 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1245 #else 1246 u_register_t scr_el3 = read_scr_el3(); 1247 write_scr_el3(scr_el3 | SCR_NS_BIT); 1248 isb(); 1249 1250 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1251 1252 write_scr_el3(scr_el3); 1253 isb(); 1254 #endif 1255 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1256 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1257 } 1258 1259 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1260 { 1261 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1262 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1263 #else 1264 u_register_t scr_el3 = read_scr_el3(); 1265 write_scr_el3(scr_el3 | SCR_NS_BIT); 1266 isb(); 1267 1268 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1269 1270 write_scr_el3(scr_el3); 1271 isb(); 1272 #endif 1273 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1274 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1275 } 1276 1277 /* ----------------------------------------------------- 1278 * The following registers are not added: 1279 * AMEVCNTVOFF0<n>_EL2 1280 * AMEVCNTVOFF1<n>_EL2 1281 * ----------------------------------------------------- 1282 */ 1283 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1284 { 1285 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1286 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1287 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1288 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1289 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1290 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1291 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1292 if (CTX_INCLUDE_AARCH32_REGS) { 1293 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1294 } 1295 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1296 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1297 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1298 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1299 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1300 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1301 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1302 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1303 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1304 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1305 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1306 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1307 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1308 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1309 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1310 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1311 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1312 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1313 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1314 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1315 } 1316 1317 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1318 { 1319 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1320 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1321 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1322 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1323 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1324 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1325 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1326 if (CTX_INCLUDE_AARCH32_REGS) { 1327 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1328 } 1329 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1330 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1331 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1332 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1333 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1334 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1335 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1336 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1337 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1338 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1339 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1340 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1341 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1342 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1343 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1344 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1345 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1346 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1347 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1348 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1349 } 1350 1351 /******************************************************************************* 1352 * Save EL2 sysreg context 1353 ******************************************************************************/ 1354 void cm_el2_sysregs_context_save(uint32_t security_state) 1355 { 1356 cpu_context_t *ctx; 1357 el2_sysregs_t *el2_sysregs_ctx; 1358 1359 ctx = cm_get_context(security_state); 1360 assert(ctx != NULL); 1361 1362 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1363 1364 el2_sysregs_context_save_common(el2_sysregs_ctx); 1365 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1366 1367 if (is_feat_mte2_supported()) { 1368 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1369 } 1370 1371 if (is_feat_mpam_supported()) { 1372 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1373 } 1374 1375 if (is_feat_fgt_supported()) { 1376 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1377 } 1378 1379 if (is_feat_fgt2_supported()) { 1380 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1381 } 1382 1383 if (is_feat_ecv_v2_supported()) { 1384 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1385 } 1386 1387 if (is_feat_vhe_supported()) { 1388 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1389 read_contextidr_el2()); 1390 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1391 } 1392 1393 if (is_feat_ras_supported()) { 1394 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1395 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1396 } 1397 1398 if (is_feat_nv2_supported()) { 1399 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1400 } 1401 1402 if (is_feat_trf_supported()) { 1403 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1404 } 1405 1406 if (is_feat_csv2_2_supported()) { 1407 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1408 read_scxtnum_el2()); 1409 } 1410 1411 if (is_feat_hcx_supported()) { 1412 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1413 } 1414 1415 if (is_feat_tcr2_supported()) { 1416 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1417 } 1418 1419 if (is_feat_sxpie_supported()) { 1420 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1421 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1422 } 1423 1424 if (is_feat_sxpoe_supported()) { 1425 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1426 } 1427 1428 if (is_feat_s2pie_supported()) { 1429 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1430 } 1431 1432 if (is_feat_gcs_supported()) { 1433 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1434 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1435 } 1436 } 1437 1438 /******************************************************************************* 1439 * Restore EL2 sysreg context 1440 ******************************************************************************/ 1441 void cm_el2_sysregs_context_restore(uint32_t security_state) 1442 { 1443 cpu_context_t *ctx; 1444 el2_sysregs_t *el2_sysregs_ctx; 1445 1446 ctx = cm_get_context(security_state); 1447 assert(ctx != NULL); 1448 1449 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1450 1451 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1452 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1453 1454 if (is_feat_mte2_supported()) { 1455 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1456 } 1457 1458 if (is_feat_mpam_supported()) { 1459 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1460 } 1461 1462 if (is_feat_fgt_supported()) { 1463 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1464 } 1465 1466 if (is_feat_fgt2_supported()) { 1467 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1468 } 1469 1470 if (is_feat_ecv_v2_supported()) { 1471 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1472 } 1473 1474 if (is_feat_vhe_supported()) { 1475 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1476 contextidr_el2)); 1477 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1478 } 1479 1480 if (is_feat_ras_supported()) { 1481 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1482 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1483 } 1484 1485 if (is_feat_nv2_supported()) { 1486 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1487 } 1488 1489 if (is_feat_trf_supported()) { 1490 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1491 } 1492 1493 if (is_feat_csv2_2_supported()) { 1494 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1495 scxtnum_el2)); 1496 } 1497 1498 if (is_feat_hcx_supported()) { 1499 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1500 } 1501 1502 if (is_feat_tcr2_supported()) { 1503 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1504 } 1505 1506 if (is_feat_sxpie_supported()) { 1507 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1508 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1509 } 1510 1511 if (is_feat_sxpoe_supported()) { 1512 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1513 } 1514 1515 if (is_feat_s2pie_supported()) { 1516 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1517 } 1518 1519 if (is_feat_gcs_supported()) { 1520 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1521 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1522 } 1523 } 1524 #endif /* CTX_INCLUDE_EL2_REGS */ 1525 1526 /******************************************************************************* 1527 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1528 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1529 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1530 * cm_prepare_el3_exit function. 1531 ******************************************************************************/ 1532 void cm_prepare_el3_exit_ns(void) 1533 { 1534 #if CTX_INCLUDE_EL2_REGS 1535 #if ENABLE_ASSERTIONS 1536 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1537 assert(ctx != NULL); 1538 1539 /* Assert that EL2 is used. */ 1540 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1541 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1542 (el_implemented(2U) != EL_IMPL_NONE)); 1543 #endif /* ENABLE_ASSERTIONS */ 1544 1545 /* Restore EL2 and EL1 sysreg contexts */ 1546 cm_el2_sysregs_context_restore(NON_SECURE); 1547 cm_el1_sysregs_context_restore(NON_SECURE); 1548 cm_set_next_eret_context(NON_SECURE); 1549 #else 1550 cm_prepare_el3_exit(NON_SECURE); 1551 #endif /* CTX_INCLUDE_EL2_REGS */ 1552 } 1553 1554 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1555 { 1556 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1557 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1558 1559 #if (!ERRATA_SPECULATIVE_AT) 1560 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1561 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1562 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1563 1564 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1565 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1566 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1567 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1568 write_el1_ctx_common(ctx, ttbr0_el1, read_ttbr0_el1()); 1569 write_el1_ctx_common(ctx, ttbr1_el1, read_ttbr1_el1()); 1570 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1571 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1572 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1573 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1574 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1575 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1576 write_el1_ctx_common(ctx, par_el1, read_par_el1()); 1577 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1578 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1579 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1580 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1581 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1582 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1583 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1584 1585 if (CTX_INCLUDE_AARCH32_REGS) { 1586 /* Save Aarch32 registers */ 1587 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1588 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1589 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1590 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1591 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1592 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1593 } 1594 1595 if (NS_TIMER_SWITCH) { 1596 /* Save NS Timer registers */ 1597 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1598 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1599 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1600 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1601 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1602 } 1603 1604 if (is_feat_mte2_supported()) { 1605 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1606 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1607 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1608 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1609 } 1610 1611 if (is_feat_ras_supported()) { 1612 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1613 } 1614 1615 if (is_feat_s1pie_supported()) { 1616 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1617 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1618 } 1619 1620 if (is_feat_s1poe_supported()) { 1621 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1622 } 1623 1624 if (is_feat_s2poe_supported()) { 1625 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1626 } 1627 1628 if (is_feat_tcr2_supported()) { 1629 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1630 } 1631 1632 if (is_feat_trf_supported()) { 1633 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1634 } 1635 1636 if (is_feat_csv2_2_supported()) { 1637 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1638 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1639 } 1640 1641 if (is_feat_gcs_supported()) { 1642 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1643 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1644 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1645 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1646 } 1647 } 1648 1649 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1650 { 1651 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1652 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1653 1654 #if (!ERRATA_SPECULATIVE_AT) 1655 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1656 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1657 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1658 1659 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1660 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1661 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1662 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1663 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1664 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1665 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1666 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1667 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1668 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1669 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1670 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1671 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1672 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1673 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1674 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1675 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1676 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1677 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1678 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1679 1680 if (CTX_INCLUDE_AARCH32_REGS) { 1681 /* Restore Aarch32 registers */ 1682 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1683 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1684 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1685 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1686 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1687 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1688 } 1689 1690 if (NS_TIMER_SWITCH) { 1691 /* Restore NS Timer registers */ 1692 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1693 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1694 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1695 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1696 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1697 } 1698 1699 if (is_feat_mte2_supported()) { 1700 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1701 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1702 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1703 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1704 } 1705 1706 if (is_feat_ras_supported()) { 1707 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1708 } 1709 1710 if (is_feat_s1pie_supported()) { 1711 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1712 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1713 } 1714 1715 if (is_feat_s1poe_supported()) { 1716 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1717 } 1718 1719 if (is_feat_s2poe_supported()) { 1720 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1721 } 1722 1723 if (is_feat_tcr2_supported()) { 1724 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1725 } 1726 1727 if (is_feat_trf_supported()) { 1728 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1729 } 1730 1731 if (is_feat_csv2_2_supported()) { 1732 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1733 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1734 } 1735 1736 if (is_feat_gcs_supported()) { 1737 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1738 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1739 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1740 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1741 } 1742 } 1743 1744 /******************************************************************************* 1745 * The next four functions are used by runtime services to save and restore 1746 * EL1 context on the 'cpu_context' structure for the specified security 1747 * state. 1748 ******************************************************************************/ 1749 void cm_el1_sysregs_context_save(uint32_t security_state) 1750 { 1751 cpu_context_t *ctx; 1752 1753 ctx = cm_get_context(security_state); 1754 assert(ctx != NULL); 1755 1756 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1757 1758 #if IMAGE_BL31 1759 if (security_state == SECURE) 1760 PUBLISH_EVENT(cm_exited_secure_world); 1761 else 1762 PUBLISH_EVENT(cm_exited_normal_world); 1763 #endif 1764 } 1765 1766 void cm_el1_sysregs_context_restore(uint32_t security_state) 1767 { 1768 cpu_context_t *ctx; 1769 1770 ctx = cm_get_context(security_state); 1771 assert(ctx != NULL); 1772 1773 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1774 1775 #if IMAGE_BL31 1776 if (security_state == SECURE) 1777 PUBLISH_EVENT(cm_entering_secure_world); 1778 else 1779 PUBLISH_EVENT(cm_entering_normal_world); 1780 #endif 1781 } 1782 1783 /******************************************************************************* 1784 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1785 * given security state with the given entrypoint 1786 ******************************************************************************/ 1787 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1788 { 1789 cpu_context_t *ctx; 1790 el3_state_t *state; 1791 1792 ctx = cm_get_context(security_state); 1793 assert(ctx != NULL); 1794 1795 /* Populate EL3 state so that ERET jumps to the correct entry */ 1796 state = get_el3state_ctx(ctx); 1797 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1798 } 1799 1800 /******************************************************************************* 1801 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1802 * pertaining to the given security state 1803 ******************************************************************************/ 1804 void cm_set_elr_spsr_el3(uint32_t security_state, 1805 uintptr_t entrypoint, uint32_t spsr) 1806 { 1807 cpu_context_t *ctx; 1808 el3_state_t *state; 1809 1810 ctx = cm_get_context(security_state); 1811 assert(ctx != NULL); 1812 1813 /* Populate EL3 state so that ERET jumps to the correct entry */ 1814 state = get_el3state_ctx(ctx); 1815 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1816 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1817 } 1818 1819 /******************************************************************************* 1820 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1821 * pertaining to the given security state using the value and bit position 1822 * specified in the parameters. It preserves all other bits. 1823 ******************************************************************************/ 1824 void cm_write_scr_el3_bit(uint32_t security_state, 1825 uint32_t bit_pos, 1826 uint32_t value) 1827 { 1828 cpu_context_t *ctx; 1829 el3_state_t *state; 1830 u_register_t scr_el3; 1831 1832 ctx = cm_get_context(security_state); 1833 assert(ctx != NULL); 1834 1835 /* Ensure that the bit position is a valid one */ 1836 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1837 1838 /* Ensure that the 'value' is only a bit wide */ 1839 assert(value <= 1U); 1840 1841 /* 1842 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1843 * and set it to its new value. 1844 */ 1845 state = get_el3state_ctx(ctx); 1846 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1847 scr_el3 &= ~(1UL << bit_pos); 1848 scr_el3 |= (u_register_t)value << bit_pos; 1849 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1850 } 1851 1852 /******************************************************************************* 1853 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1854 * given security state. 1855 ******************************************************************************/ 1856 u_register_t cm_get_scr_el3(uint32_t security_state) 1857 { 1858 cpu_context_t *ctx; 1859 el3_state_t *state; 1860 1861 ctx = cm_get_context(security_state); 1862 assert(ctx != NULL); 1863 1864 /* Populate EL3 state so that ERET jumps to the correct entry */ 1865 state = get_el3state_ctx(ctx); 1866 return read_ctx_reg(state, CTX_SCR_EL3); 1867 } 1868 1869 /******************************************************************************* 1870 * This function is used to program the context that's used for exception 1871 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1872 * the required security state 1873 ******************************************************************************/ 1874 void cm_set_next_eret_context(uint32_t security_state) 1875 { 1876 cpu_context_t *ctx; 1877 1878 ctx = cm_get_context(security_state); 1879 assert(ctx != NULL); 1880 1881 cm_set_next_context(ctx); 1882 } 1883