1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define LIT_CAPACITY 239 14#define MID_CAPACITY 686 15#define BIG_CAPACITY 1024 16 17#define MHU_TX_ADDR 46040000 /* hex */ 18#define MHU_TX_COMPAT "arm,mhuv3" 19#define MHU_TX_INT_NAME "" 20 21#define MHU_RX_ADDR 46140000 /* hex */ 22#define MHU_RX_COMPAT "arm,mhuv3" 23#define MHU_OFFSET 0x10000 24#define MHU_MBOX_CELLS 3 25#define MHU_RX_INT_NUM 300 26#define MHU_RX_INT_NAME "combined-mbx" 27 28#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu" 29#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu" 30#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu" 31 32#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ 33#define UARTCLK_FREQ 3750000 34 35#if TARGET_FLAVOUR_FVP 36#define DPU_ADDR 4000000000 37#define DPU_IRQ 579 38#elif TARGET_FLAVOUR_FPGA 39#define DPU_ADDR 2cc00000 40#define DPU_IRQ 69 41#endif 42 43#include "tc-common.dtsi" 44#if TARGET_FLAVOUR_FVP 45#include "tc-fvp.dtsi" 46#else 47#include "tc-fpga.dtsi" 48#endif /* TARGET_FLAVOUR_FVP */ 49#include "tc-base.dtsi" 50 51/ { 52 cpus { 53 CPU2:cpu@200 { 54 clocks = <&scmi_dvfs 1>; 55 capacity-dmips-mhz = <MID_CAPACITY>; 56 }; 57 58 CPU3:cpu@300 { 59 clocks = <&scmi_dvfs 1>; 60 capacity-dmips-mhz = <MID_CAPACITY>; 61 }; 62 63 CPU6:cpu@600 { 64 clocks = <&scmi_dvfs 2>; 65 capacity-dmips-mhz = <BIG_CAPACITY>; 66 }; 67 68 CPU7:cpu@700 { 69 clocks = <&scmi_dvfs 2>; 70 capacity-dmips-mhz = <BIG_CAPACITY>; 71 }; 72 }; 73 74 cs-pmu@0 { 75 compatible = "arm,coresight-pmu"; 76 reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>; 77 }; 78 79 cs-pmu@1 { 80 compatible = "arm,coresight-pmu"; 81 reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>; 82 }; 83 84 cs-pmu@2 { 85 compatible = "arm,coresight-pmu"; 86 reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>; 87 }; 88 89 cs-pmu@3 { 90 compatible = "arm,coresight-pmu"; 91 reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>; 92 }; 93 94 spe-pmu-mid { 95 status = "okay"; 96 }; 97 98 spe-pmu-big { 99 status = "okay"; 100 }; 101 102 dsu-pmu { 103 compatible = "arm,dsu-pmu"; 104 cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; 105 }; 106 107 ni-pmu { 108 compatible = "arm,ni-tower"; 109 reg = <0x0 0x4f000000 0x0 0x4000000>; 110 }; 111 112 sram: sram@6000000 { 113 cpu_scp_scmi_p2a: scp-shmem@80 { 114 compatible = "arm,scmi-shmem"; 115 reg = <0x80 0x80>; 116 }; 117 }; 118 119 firmware { 120 scmi { 121 mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>; 122 shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>; 123 }; 124 }; 125 126 gic: interrupt-controller@GIC_CTRL_ADDR { 127 ppi-partitions { 128 ppi_partition_little: interrupt-partition-0 { 129 affinity = <&CPU0>, <&CPU1>; 130 }; 131 132 ppi_partition_mid: interrupt-partition-1 { 133 affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>; 134 }; 135 136 ppi_partition_big: interrupt-partition-2 { 137 affinity = <&CPU6>, <&CPU7>; 138 }; 139 }; 140 }; 141 142#if TARGET_FLAVOUR_FVP 143 smmu_700: iommu@3f000000 { 144 status = "okay"; 145 }; 146 147 smmu_700_dpu: iommu@4002a00000 { 148 status = "okay"; 149 }; 150#else 151 smmu_600: smmu@2ce00000 { 152 status = "okay"; 153 }; 154#endif 155 156 dp0: display@DPU_ADDR { 157#if TARGET_FLAVOUR_FVP 158 iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, 159 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; 160#else /* TARGET_FLAVOUR_FPGA */ 161 iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>, 162 <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>, 163 <&smmu_600 8>, <&smmu_600 9>; 164#endif 165 }; 166 167 gpu: gpu@2d000000 { 168#if TARGET_FLAVOUR_FVP 169 iommus = <&smmu_700 0x200>; 170#endif 171 }; 172}; 173