1# Copyright (c) 2021-2025, Arm Limited. All rights reserved. 2# 3# SPDX-License-Identifier: BSD-3-Clause 4# 5 6include common/fdt_wrappers.mk 7 8TARGET_FLAVOUR := fvp 9# DPU with SCMI may not necessarily work, so allow its independence 10TC_DPU_USE_SCMI_CLK := 1 11# SCMI power domain control enable 12TC_SCMI_PD_CTRL_EN := 1 13 14# System setup 15CSS_USE_SCMI_SDS_DRIVER := 1 16HW_ASSISTED_COHERENCY := 1 17USE_COHERENT_MEM := 0 18USE_GIC_DRIVER := 3 19GIC_ENABLE_V4_EXTN := 1 20GICV3_SUPPORT_GIC600 := 1 21override NEED_BL2U := no 22override ARM_PLAT_MT := 1 23 24# CPU setup 25ARM_ARCH_MINOR := 7 26BRANCH_PROTECTION := 1 27ENABLE_FEAT_MPAM := 1 # default is 2, optimise 28ENABLE_SVE_FOR_NS := 2 # to show we use it 29ENABLE_SVE_FOR_SWD := 1 30ENABLE_SME_FOR_NS := 2 31ENABLE_SME2_FOR_NS := 2 32ENABLE_SME_FOR_SWD := 1 33ENABLE_TRBE_FOR_NS := 1 34ENABLE_SYS_REG_TRACE_FOR_NS := 1 35ENABLE_FEAT_AMU := 1 36ENABLE_AMU_AUXILIARY_COUNTERS := 1 37ENABLE_MPMM := 1 38ENABLE_FEAT_MTE2 := 2 39ENABLE_SPE_FOR_NS := 2 40ENABLE_FEAT_TCR2 := 2 41 42ifneq ($(filter ${TARGET_PLATFORM}, 3),) 43ENABLE_FEAT_RNG_TRAP := 0 44else 45ENABLE_FEAT_RNG_TRAP := 1 46endif 47 48CTX_INCLUDE_AARCH32_REGS := 0 49 50ifeq (${SPD},spmd) 51 SPMD_SPM_AT_SEL2 := 1 52 CTX_INCLUDE_PAUTH_REGS := 1 53endif 54 55TRNG_SUPPORT := 1 56 57# TC RESOLUTION - LIST OF VALID OPTIONS (this impacts only FVP) 58TC_RESOLUTION_OPTIONS := 640x480p60 \ 59 1920x1080p60 60# Set default to the 640x480p60 resolution mode 61TC_RESOLUTION ?= $(firstword $(TC_RESOLUTION_OPTIONS)) 62 63# Check resolution option for FVP 64ifneq ($(filter ${TARGET_FLAVOUR}, fvp),) 65ifeq ($(filter ${TC_RESOLUTION}, ${TC_RESOLUTION_OPTIONS}),) 66 $(error TC_RESOLUTION is ${TC_RESOLUTION}, it must be: ${TC_RESOLUTION_OPTIONS}) 67endif 68endif 69 70ifneq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0) 71 $(error Platform ${PLAT}$(TARGET_PLATFORM) is no longer available.) 72endif 73 74ifeq ($(shell expr $(TARGET_PLATFORM) \<= 4), 0) 75 $(error TARGET_PLATFORM must be less than or equal to 4) 76endif 77 78ifeq ($(filter ${TARGET_FLAVOUR}, fvp fpga),) 79 $(error TARGET_FLAVOUR must be fvp or fpga) 80endif 81 82# Support for loading FS Image to DRAM 83TC_FPGA_FS_IMG_IN_RAM := 0 84 85# Support Loading of FIP image to DRAM 86TC_FPGA_FIP_IMG_IN_RAM := 0 87 88# Use simple panel instead of vencoder with DPU 89TC_DPU_USE_SIMPLE_PANEL := 0 90 91$(eval $(call add_defines, \ 92 TARGET_PLATFORM \ 93 TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \ 94 TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \ 95 TC_DPU_USE_SCMI_CLK \ 96 TC_SCMI_PD_CTRL_EN \ 97 TC_FPGA_FS_IMG_IN_RAM \ 98 TC_FPGA_FIP_IMG_IN_RAM \ 99 TC_DPU_USE_SIMPLE_PANEL \ 100)) 101 102CSS_LOAD_SCP_IMAGES := 1 103 104# Save DSU PMU registers on cluster off and restore them on cluster on 105PRESERVE_DSU_PMU_REGS := 1 106 107PLAT_MHU := MHUv3 108 109TC_BASE = plat/arm/board/tc 110 111PLAT_INCLUDES += -I${TC_BASE}/include/ \ 112 -I${TC_BASE}/fdts/ 113 114# CPU libraries for TARGET_PLATFORM=3 115ifeq (${TARGET_PLATFORM}, 3) 116ERRATA_A520_2938996 := 1 117 118TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \ 119 lib/cpus/aarch64/cortex_a725.S \ 120 lib/cpus/aarch64/cortex_x925.S 121endif 122 123# CPU libraries for TARGET_PLATFORM=4 124ifeq (${TARGET_PLATFORM}, 4) 125FEAT_PABANDON := 1 126# prevent CME related wakups 127ERRATA_SME_POWER_DOWN := 1 128TC_CPU_SOURCES += lib/cpus/aarch64/cortex_gelas.S \ 129 lib/cpus/aarch64/nevis.S \ 130 lib/cpus/aarch64/travis.S 131endif 132 133INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c \ 134 plat/arm/common/arm_ni.c 135 136PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \ 137 ${TC_BASE}/include/tc_helpers.S 138 139 140ifneq (${ENABLE_STACK_PROTECTOR},0) 141PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_stack_protector.c 142endif 143 144BL1_SOURCES += ${INTERCONNECT_SOURCES} \ 145 ${TC_CPU_SOURCES} \ 146 ${TC_BASE}/tc_trusted_boot.c \ 147 ${TC_BASE}/tc_bl1_setup.c \ 148 ${TC_BASE}/tc_err.c \ 149 drivers/arm/sbsa/sbsa.c 150 151BL2_SOURCES += ${TC_BASE}/tc_security.c \ 152 ${TC_BASE}/tc_err.c \ 153 ${TC_BASE}/tc_trusted_boot.c \ 154 ${TC_BASE}/tc_bl2_setup.c \ 155 lib/utils/mem_region.c \ 156 drivers/arm/tzc/tzc400.c \ 157 plat/arm/common/arm_nor_psci_mem_protect.c 158 159BL31_SOURCES += ${INTERCONNECT_SOURCES} \ 160 ${TC_CPU_SOURCES} \ 161 ${TC_BASE}/tc_bl31_setup.c \ 162 ${TC_BASE}/tc_topology.c \ 163 lib/fconf/fconf.c \ 164 lib/fconf/fconf_dyn_cfg_getter.c \ 165 drivers/arm/css/dsu/dsu.c \ 166 drivers/cfi/v2m/v2m_flash.c \ 167 lib/utils/mem_region.c \ 168 plat/arm/common/arm_nor_psci_mem_protect.c \ 169 drivers/arm/sbsa/sbsa.c 170 171BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 172 173# Add the FDT_SOURCES and options for Dynamic Config 174FDT_SOURCES += ${TC_BASE}/fdts/${PLAT}_fw_config.dts \ 175 ${TC_BASE}/fdts/${PLAT}_tb_fw_config.dts \ 176 ${TC_BASE}/fdts/${PLAT}_nt_fw_config.dts 177FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 178TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 179FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 180 181# Add the FW_CONFIG to FIP and specify the same to certtool 182$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 183# Add the TB_FW_CONFIG to FIP and specify the same to certtool 184$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 185# Add the NT_FW_CONFIG to FIP and specify the same to certtool 186$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 187 188ifeq (${SPD},spmd) 189ifeq ($(ARM_SPMC_MANIFEST_DTS),) 190ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_test_manifest.dts 191endif 192 193FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 194TC_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 195 196# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 197$(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_CONFIG})) 198endif 199 200#Device tree 201TC_HW_CONFIG_DTS := fdts/${PLAT}${TARGET_PLATFORM}.dts 202TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 203FDT_SOURCES += ${TC_HW_CONFIG_DTS} 204$(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS))) 205 206# Add the HW_CONFIG to FIP and specify the same to certtool 207$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG})) 208 209$(info Including rse_comms.mk) 210include drivers/arm/rse/rse_comms.mk 211 212BL1_SOURCES += ${RSE_COMMS_SOURCES} \ 213 plat/arm/board/tc/tc_rse_comms.c 214BL2_SOURCES += ${RSE_COMMS_SOURCES} \ 215 plat/arm/board/tc/tc_rse_comms.c 216BL31_SOURCES += ${RSE_COMMS_SOURCES} \ 217 plat/arm/board/tc/tc_rse_comms.c \ 218 lib/psa/rse_platform.c 219 220# Include Measured Boot makefile before any Crypto library makefile. 221# Crypto library makefile may need default definitions of Measured Boot build 222# flags present in Measured Boot makefile. 223ifeq (${MEASURED_BOOT},1) 224 ifeq (${DICE_PROTECTION_ENVIRONMENT},1) 225 $(info Including qcbor.mk) 226 include drivers/measured_boot/rse/qcbor.mk 227 $(info Including dice_prot_env.mk) 228 include drivers/measured_boot/rse/dice_prot_env.mk 229 230 BL1_SOURCES += ${QCBOR_SOURCES} \ 231 ${DPE_SOURCES} \ 232 plat/arm/board/tc/tc_common_dpe.c \ 233 plat/arm/board/tc/tc_bl1_dpe.c \ 234 lib/psa/dice_protection_environment.c \ 235 drivers/arm/css/sds/sds.c \ 236 drivers/delay_timer/delay_timer.c \ 237 drivers/delay_timer/generic_delay_timer.c 238 239 BL2_SOURCES += ${QCBOR_SOURCES} \ 240 ${DPE_SOURCES} \ 241 plat/arm/board/tc/tc_common_dpe.c \ 242 plat/arm/board/tc/tc_bl2_dpe.c \ 243 lib/psa/dice_protection_environment.c 244 245 PLAT_INCLUDES += -I${QCBOR_INCLUDES} \ 246 -Iinclude/lib/dice 247 else 248 $(info Including rse_measured_boot.mk) 249 include drivers/measured_boot/rse/rse_measured_boot.mk 250 251 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} \ 252 plat/arm/board/tc/tc_common_measured_boot.c \ 253 plat/arm/board/tc/tc_bl1_measured_boot.c \ 254 lib/psa/measured_boot.c 255 256 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} \ 257 plat/arm/board/tc/tc_common_measured_boot.c \ 258 plat/arm/board/tc/tc_bl2_measured_boot.c \ 259 lib/psa/measured_boot.c 260 endif 261endif 262 263BL31_SOURCES += plat/arm/board/tc/tc_trng.c 264 265ifneq (${ENABLE_FEAT_RNG_TRAP},0) 266 BL31_SOURCES += plat/arm/board/tc/tc_rng_trap.c 267endif 268 269ifneq (${PLATFORM_TEST},) 270 # Add this include as first, before arm_common.mk. This is necessary 271 # because arm_common.mk builds Mbed TLS, and platform_test.mk can 272 # change the list of Mbed TLS files that are to be compiled 273 # (LIBMBEDTLS_SRCS). 274 include plat/arm/board/tc/platform_test.mk 275endif 276 277 278include plat/arm/common/arm_common.mk 279include plat/arm/css/common/css_common.mk 280include plat/arm/board/common/board_common.mk 281