1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 103 ``fip`` target in case TF-A BL2 is used. 104 105- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 106 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 107 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 108 109- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 110 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 111 If enabled, it is needed to use a compiler that supports the option 112 ``-mbranch-protection``. Selects the branch protection features to use: 113- 0: Default value turns off all types of branch protection 114- 1: Enables all types of branch protection features 115- 2: Return address signing to its standard level 116- 3: Extend the signing to include leaf functions 117- 4: Turn on branch target identification mechanism 118 119 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 120 and resulting PAuth/BTI features. 121 122 +-------+--------------+-------+-----+ 123 | Value | GCC option | PAuth | BTI | 124 +=======+==============+=======+=====+ 125 | 0 | none | N | N | 126 +-------+--------------+-------+-----+ 127 | 1 | standard | Y | Y | 128 +-------+--------------+-------+-----+ 129 | 2 | pac-ret | Y | N | 130 +-------+--------------+-------+-----+ 131 | 3 | pac-ret+leaf | Y | N | 132 +-------+--------------+-------+-----+ 133 | 4 | bti | N | Y | 134 +-------+--------------+-------+-----+ 135 136 This option defaults to 0. 137 Note that Pointer Authentication is enabled for Non-secure world 138 irrespective of the value of this option if the CPU supports it. 139 140- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 141 compilation of each build. It must be set to a C string (including quotes 142 where applicable). Defaults to a string that contains the time and date of 143 the compilation. 144 145- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 146 build to be uniquely identified. Defaults to the current git commit id. 147 148- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 149 150- ``CFLAGS``: Extra user options appended on the compiler's command line in 151 addition to the options set by the build system. 152 153- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 154 release several CPUs out of reset. It can take either 0 (several CPUs may be 155 brought up) or 1 (only one CPU will ever be brought up during cold reset). 156 Default is 0. If the platform always brings up a single CPU, there is no 157 need to distinguish between primary and secondary CPUs and the boot path can 158 be optimised. The ``plat_is_my_cpu_primary()`` and 159 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 160 to be implemented in this case. 161 162- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 163 Defaults to ``tbbr``. 164 165- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 166 register state when an unexpected exception occurs during execution of 167 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 168 this is only enabled for a debug build of the firmware. 169 170- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 171 certificate generation tool to create new keys in case no valid keys are 172 present or specified. Allowed options are '0' or '1'. Default is '1'. 173 174- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 175 the AArch32 system registers to be included when saving and restoring the 176 CPU context. The option must be set to 0 for AArch64-only platforms (that 177 is on hardware that does not implement AArch32, or at least not at EL1 and 178 higher ELs). Default value is 1. 179 180- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 181 registers to be included when saving and restoring the CPU context. Default 182 is 0. 183 184- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 185 Memory System Resource Partitioning and Monitoring (MPAM) 186 registers to be included when saving and restoring the CPU context. 187 Default is '0'. 188 189- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 190 registers to be saved/restored when entering/exiting an EL2 execution 191 context. This flag can take values 0 to 2, to align with the 192 ``ENABLE_FEAT`` mechanism. Default value is 0. 193 194- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 195 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 196 to be included when saving and restoring the CPU context as part of world 197 switch. This flag can take values 0 to 2, to align with ``ENABLE_FEAT`` 198 mechanism. Default value is 0. 199 200 Note that Pointer Authentication is enabled for Non-secure world irrespective 201 of the value of this flag if the CPU supports it. 202 203- ``DEBUG``: Chooses between a debug and release build. It can take either 0 204 (release) or 1 (debug) as values. 0 is the default. 205 206- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 207 authenticated decryption algorithm to be used to decrypt firmware/s during 208 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 209 this flag is ``none`` to disable firmware decryption which is an optional 210 feature as per TBBR. 211 212- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 213 of the binary image. If set to 1, then only the ELF image is built. 214 0 is the default. 215 216- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 217 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 218 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 219 mechanism. Default is ``0``. 220 221- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 222 Board Boot authentication at runtime. This option is meant to be enabled only 223 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 224 flag has to be enabled. 0 is the default. 225 226- ``E``: Boolean option to make warnings into errors. Default is 1. 227 228 When specifying higher warnings levels (``W=1`` and higher), this option 229 defaults to 0. This is done to encourage contributors to use them, as they 230 are expected to produce warnings that would otherwise fail the build. New 231 contributions are still expected to build with ``W=0`` and ``E=1`` (the 232 default). 233 234- ``EARLY_CONSOLE``: This option is used to enable early traces before default 235 console is properly setup. It introduces EARLY_* traces macros, that will 236 use the non-EARLY traces macros if the flag is enabled, or do nothing 237 otherwise. To use this feature, platforms will have to create the function 238 plat_setup_early_console(). 239 Default is 0 (disabled) 240 241- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 242 the normal boot flow. It must specify the entry point address of the EL3 243 payload. Please refer to the "Booting an EL3 payload" section for more 244 details. 245 246- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 247 (also known as group 1 counters). These are implementation-defined counters, 248 and as such require additional platform configuration. Default is 0. 249 250- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 251 allows platforms with auxiliary counters to describe them via the 252 ``HW_CONFIG`` device tree blob. Default is 0. 253 254- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 255 are compiled out. For debug builds, this option defaults to 1, and calls to 256 ``assert()`` are left in place. For release builds, this option defaults to 0 257 and calls to ``assert()`` function are compiled out. This option can be set 258 independently of ``DEBUG``. It can also be used to hide any auxiliary code 259 that is only required for the assertion and does not fit in the assertion 260 itself. 261 262- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 263 dumps or not. It is supported in both AArch64 and AArch32. However, in 264 AArch32 the format of the frame records are not defined in the AAPCS and they 265 are defined by the implementation. This implementation of backtrace only 266 supports the format used by GCC when T32 interworking is disabled. For this 267 reason enabling this option in AArch32 will force the compiler to only 268 generate A32 code. This option is enabled by default only in AArch64 debug 269 builds, but this behaviour can be overridden in each platform's Makefile or 270 in the build command line. 271 272- ``ENABLE_FEAT`` 273 The Arm architecture defines several architecture extension features, 274 named FEAT_xxx in the architecure manual. Some of those features require 275 setup code in higher exception levels, other features might be used by TF-A 276 code itself. 277 Most of the feature flags defined in the TF-A build system permit to take 278 the values 0, 1 or 2, with the following meaning: 279 280 :: 281 282 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 283 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 284 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 285 286 When setting the flag to 0, the feature is disabled during compilation, 287 and the compiler's optimisation stage and the linker will try to remove 288 as much of this code as possible. 289 If it is defined to 1, the code will use the feature unconditionally, so the 290 CPU is expected to support that feature. The FEATURE_DETECTION debug 291 feature, if enabled, will verify this. 292 If the feature flag is set to 2, support for the feature will be compiled 293 in, but its existence will be checked at runtime, so it works on CPUs with 294 or without the feature. This is mostly useful for platforms which either 295 support multiple different CPUs, or where the CPU is configured at runtime, 296 like in emulators. 297 298- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 299 extensions. This flag can take the values 0 to 2, to align with the 300 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 301 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 302 and this option can be used to enable this feature on those systems as well. 303 This flag can take the values 0 to 2, the default is 0. 304 305- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 306 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 307 onwards. This flag can take the values 0 to 2, to align with the 308 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 309 310- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 311 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 312 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 313 optional feature available on Arm v8.0 onwards. This flag can take values 314 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 315 Default value is ``0``. 316 317- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 318 extension. This feature is supported in AArch64 state only and is an optional 319 feature available in Arm v8.0 implementations. 320 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 321 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 322 mechanism. Default value is ``0``. 323 324- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 325 extension which allows the ability to implement more than 16 breakpoints 326 and/or watchpoints. This feature is mandatory from v8.9 and is optional 327 from v8.8. This flag can take the values of 0 to 2, to align with the 328 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 329 330- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 331 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 332 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 333 and upwards. This flag can take the values 0 to 2, to align with the 334 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 335 336- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 337 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 338 Physical Offset register) during EL2 to EL3 context save/restore operations. 339 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 340 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 341 mechanism. Default value is ``0``. 342 343- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 344 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 345 Read Trap Register) during EL2 to EL3 context save/restore operations. 346 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 347 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 348 mechanism. Default value is ``0``. 349 350- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 351 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 352 during EL2 to EL3 context save/restore operations. 353 Its an optional architectural feature and is available from v8.8 and upwards. 354 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 355 mechanism. Default value is ``0``. 356 357- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 358 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 359 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 360 mandatory architectural feature and is enabled from v8.7 and upwards. This 361 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 362 mechanism. Default value is ``0``. 363 364- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 365 if the platform wants to use this feature and MTE2 is enabled at ELX. 366 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 367 mechanism. Default value is ``0``. 368 369- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 370 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 371 permission fault for any privileged data access from EL1/EL2 to virtual 372 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 373 mandatory architectural feature and is enabled from v8.1 and upwards. This 374 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 375 mechanism. Default value is ``0``. 376 377- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 378 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 379 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 380 mechanism. Default value is ``0``. 381 382- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 383 extension. This feature is only supported in AArch64 state. This flag can 384 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 385 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 386 Armv8.5 onwards. 387 388- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 389 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 390 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 391 later CPUs. It is enabled from v8.5 and upwards and if needed can be 392 overidden from platforms explicitly. 393 394- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 395 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 396 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 397 mechanism. Default is ``0``. 398 399- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 400 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 401 available on Arm v8.6. This flag can take values 0 to 2, to align with the 402 ``ENABLE_FEAT`` mechanism. Default is ``0``. 403 404 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 405 delayed by the amount of value in ``TWED_DELAY``. 406 407- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 408 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 409 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 410 architectural feature and is enabled from v8.1 and upwards. It can take 411 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 412 Default value is ``0``. 413 414- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 415 allow access to TCR2_EL2 (extended translation control) from EL2 as 416 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 417 mandatory architectural feature and is enabled from v8.9 and upwards. This 418 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 419 mechanism. Default value is ``0``. 420 421- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 422 at EL2 and below, and context switch relevant registers. This flag 423 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 424 mechanism. Default value is ``0``. 425 426- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 427 at EL2 and below, and context switch relevant registers. This flag 428 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 429 mechanism. Default value is ``0``. 430 431- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 432 at EL2 and below, and context switch relevant registers. This flag 433 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 434 mechanism. Default value is ``0``. 435 436- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 437 at EL2 and below, and context switch relevant registers. This flag 438 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 439 mechanism. Default value is ``0``. 440 441- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 442 allow use of Guarded Control Stack from EL2 as well as adding the GCS 443 registers to the EL2 context save/restore operations. This flag can take 444 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 445 Default value is ``0``. 446 447- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 448 support in GCC for TF-A. This option is currently only supported for 449 AArch64. Default is 0. 450 451- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 452 feature. MPAM is an optional Armv8.4 extension that enables various memory 453 system components and resources to define partitions; software running at 454 various ELs can assign themselves to desired partition to control their 455 performance aspects. 456 457 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 458 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 459 access their own MPAM registers without trapping into EL3. This option 460 doesn't make use of partitioning in EL3, however. Platform initialisation 461 code should configure and use partitions in EL3 as required. This option 462 defaults to ``2`` since MPAM is enabled by default for NS world only. 463 The flag is automatically disabled when the target 464 architecture is AArch32. 465 466- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 467 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 468 firmware to detect and limit high activity events to assist in SoC processor 469 power domain dynamic power budgeting and limit the triggering of whole-rail 470 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 471 472- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 473 allows platforms with cores supporting MPMM to describe them via the 474 ``HW_CONFIG`` device tree blob. Default is 0. 475 476- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 477 support within generic code in TF-A. This option is currently only supported 478 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 479 in BL32 (SP_min) for AARCH32. Default is 0. 480 481- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 482 Measurement Framework(PMF). Default is 0. 483 484- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 485 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 486 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 487 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 488 software. 489 490- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 491 instrumentation which injects timestamp collection points into TF-A to 492 allow runtime performance to be measured. Currently, only PSCI is 493 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 494 as well. Default is 0. 495 496- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 497 extensions. This is an optional architectural feature for AArch64. 498 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 499 mechanism. The default is 2 but is automatically disabled when the target 500 architecture is AArch32. 501 502- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 503 (SVE) for the Non-secure world only. SVE is an optional architectural feature 504 for AArch64. Note that when SVE is enabled for the Non-secure world, access 505 to SIMD and floating-point functionality from the Secure world is disabled by 506 default and controlled with ENABLE_SVE_FOR_SWD. 507 This is to avoid corruption of the Non-secure world data in the Z-registers 508 which are aliased by the SIMD and FP registers. The build option is not 509 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 510 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 511 enabled. This flag can take the values 0 to 2, to align with the 512 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be 513 used on systems that have SPM_MM enabled. The default is 1. 514 515- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 516 SVE is an optional architectural feature for AArch64. Note that this option 517 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 518 automatically disabled when the target architecture is AArch32. 519 520- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 521 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 522 default value is set to "none". "strong" is the recommended stack protection 523 level if this feature is desired. "none" disables the stack protection. For 524 all values other than "none", the ``plat_get_stack_protector_canary()`` 525 platform hook needs to be implemented. The value is passed as the last 526 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 527 528- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 529 flag depends on ``DECRYPTION_SUPPORT`` build flag. 530 531- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 532 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 533 534- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 535 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 536 on ``DECRYPTION_SUPPORT`` build flag. 537 538- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 539 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 540 build flag. 541 542- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 543 deprecated platform APIs, helper functions or drivers within Trusted 544 Firmware as error. It can take the value 1 (flag the use of deprecated 545 APIs as error) or 0. The default is 0. 546 547- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 548 configure an Arm® Ethos™-N NPU. To use this service the target platform's 549 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 550 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 551 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 552 553- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 554 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 555 ``TRUSTED_BOARD_BOOT`` to be enabled. 556 557- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 558 (```ethosn.bin```). This firmware image will be included in the FIP and 559 loaded at runtime. 560 561- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 562 targeted at EL3. When set ``0`` (default), no exceptions are expected or 563 handled at EL3, and a panic will result. The exception to this rule is when 564 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 565 occuring during normal world execution, are trapped to EL3. Any exception 566 trapped during secure world execution are trapped to the SPMC. This is 567 supported only for AArch64 builds. 568 569- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 570 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 571 Default value is 40 (LOG_LEVEL_INFO). 572 573- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 574 injection from lower ELs, and this build option enables lower ELs to use 575 Error Records accessed via System Registers to inject faults. This is 576 applicable only to AArch64 builds. 577 578 This feature is intended for testing purposes only, and is advisable to keep 579 disabled for production images. 580 581- ``FIP_NAME``: This is an optional build option which specifies the FIP 582 filename for the ``fip`` target. Default is ``fip.bin``. 583 584- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 585 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 586 587- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 588 589 :: 590 591 0: Encryption is done with Secret Symmetric Key (SSK) which is common 592 for a class of devices. 593 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 594 unique per device. 595 596 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 597 598- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 599 tool to create certificates as per the Chain of Trust described in 600 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 601 include the certificates in the FIP and FWU_FIP. Default value is '0'. 602 603 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 604 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 605 the corresponding certificates, and to include those certificates in the 606 FIP and FWU_FIP. 607 608 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 609 images will not include support for Trusted Board Boot. The FIP will still 610 include the corresponding certificates. This FIP can be used to verify the 611 Chain of Trust on the host machine through other mechanisms. 612 613 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 614 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 615 will not include the corresponding certificates, causing a boot failure. 616 617- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 618 inherent support for specific EL3 type interrupts. Setting this build option 619 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 620 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 621 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 622 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 623 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 624 the Secure Payload interrupts needs to be synchronously handed over to Secure 625 EL1 for handling. The default value of this option is ``0``, which means the 626 Group 0 interrupts are assumed to be handled by Secure EL1. 627 628- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 629 Interrupts, resulting from errors in NS world, will be always trapped in 630 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 631 will be trapped in the current exception level (or in EL1 if the current 632 exception level is EL0). 633 634- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 635 software operations are required for CPUs to enter and exit coherency. 636 However, newer systems exist where CPUs' entry to and exit from coherency 637 is managed in hardware. Such systems require software to only initiate these 638 operations, and the rest is managed in hardware, minimizing active software 639 management. In such systems, this boolean option enables TF-A to carry out 640 build and run-time optimizations during boot and power management operations. 641 This option defaults to 0 and if it is enabled, then it implies 642 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 643 644 If this flag is disabled while the platform which TF-A is compiled for 645 includes cores that manage coherency in hardware, then a compilation error is 646 generated. This is based on the fact that a system cannot have, at the same 647 time, cores that manage coherency in hardware and cores that don't. In other 648 words, a platform cannot have, at the same time, cores that require 649 ``HW_ASSISTED_COHERENCY=1`` and cores that require 650 ``HW_ASSISTED_COHERENCY=0``. 651 652 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 653 translation library (xlat tables v2) must be used; version 1 of translation 654 library is not supported. 655 656- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 657 implementation defined system register accesses from lower ELs. Default 658 value is ``0``. 659 660- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 661 bottom, higher addresses at the top. This build flag can be set to '1' to 662 invert this behavior. Lower addresses will be printed at the top and higher 663 addresses at the bottom. 664 665- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 666 used for generating the PKCS keys and subsequent signing of the certificate. 667 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 668 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 669 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 670 compatibility. The default value of this flag is ``rsa`` which is the TBBR 671 compliant PKCS#1 RSA 2.1 scheme. 672 673- ``KEY_SIZE``: This build flag enables the user to select the key size for 674 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 675 depend on the chosen algorithm and the cryptographic module. 676 677 +---------------------------+------------------------------------+ 678 | KEY_ALG | Possible key sizes | 679 +===========================+====================================+ 680 | rsa | 1024 , 2048 (default), 3072, 4096 | 681 +---------------------------+------------------------------------+ 682 | ecdsa | 256 (default), 384 | 683 +---------------------------+------------------------------------+ 684 | ecdsa-brainpool-regular | unavailable | 685 +---------------------------+------------------------------------+ 686 | ecdsa-brainpool-twisted | unavailable | 687 +---------------------------+------------------------------------+ 688 689- ``HASH_ALG``: This build flag enables the user to select the secure hash 690 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 691 The default value of this flag is ``sha256``. 692 693- ``LDFLAGS``: Extra user options appended to the linkers' command line in 694 addition to the one set by the build system. 695 696- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 697 output compiled into the build. This should be one of the following: 698 699 :: 700 701 0 (LOG_LEVEL_NONE) 702 10 (LOG_LEVEL_ERROR) 703 20 (LOG_LEVEL_NOTICE) 704 30 (LOG_LEVEL_WARNING) 705 40 (LOG_LEVEL_INFO) 706 50 (LOG_LEVEL_VERBOSE) 707 708 All log output up to and including the selected log level is compiled into 709 the build. The default value is 40 in debug builds and 20 in release builds. 710 711- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 712 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 713 provide trust that the code taking the measurements and recording them has 714 not been tampered with. 715 716 This option defaults to 0. 717 718- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 719 options to the compiler. An example usage: 720 721 .. code:: make 722 723 MARCH_DIRECTIVE := -march=armv8.5-a 724 725- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 726 options to the compiler currently supporting only of the options. 727 GCC documentation: 728 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 729 730 An example usage: 731 732 .. code:: make 733 734 HARDEN_SLS := 1 735 736 This option defaults to 0. 737 738- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 739 specifies a file that contains the Non-Trusted World private key in PEM 740 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 741 will be used to save the key. 742 743- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 744 optional. It is only needed if the platform makefile specifies that it 745 is required in order to build the ``fwu_fip`` target. 746 747- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 748 contents upon world switch. It can take either 0 (don't save and restore) or 749 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 750 wants the timer registers to be saved and restored. 751 752- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 753 for the BL image. It can be either 0 (include) or 1 (remove). The default 754 value is 0. 755 756- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 757 the underlying hardware is not a full PL011 UART but a minimally compliant 758 generic UART, which is a subset of the PL011. The driver will not access 759 any register that is not part of the SBSA generic UART specification. 760 Default value is 0 (a full PL011 compliant UART is present). 761 762- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 763 must be subdirectory of any depth under ``plat/``, and must contain a 764 platform makefile named ``platform.mk``. For example, to build TF-A for the 765 Arm Juno board, select PLAT=juno. 766 767- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 768 each core as well as the global context. The data includes the memory used 769 by each world and each privileged exception level. This build option is 770 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 771 772- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 773 instead of the normal boot flow. When defined, it must specify the entry 774 point address for the preloaded BL33 image. This option is incompatible with 775 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 776 over ``PRELOADED_BL33_BASE``. 777 778- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 779 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 780 registers when the cluster goes through a power cycle. This is disabled by 781 default and platforms that require this feature have to enable them. 782 783- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 784 vector address can be programmed or is fixed on the platform. It can take 785 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 786 programmable reset address, it is expected that a CPU will start executing 787 code directly at the right address, both on a cold and warm reset. In this 788 case, there is no need to identify the entrypoint on boot and the boot path 789 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 790 does not need to be implemented in this case. 791 792- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 793 possible for the PSCI power-state parameter: original and extended State-ID 794 formats. This flag if set to 1, configures the generic PSCI layer to use the 795 extended format. The default value of this flag is 0, which means by default 796 the original power-state format is used by the PSCI implementation. This flag 797 should be specified by the platform makefile and it governs the return value 798 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 799 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 800 set to 1 as well. 801 802- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 803 OS-initiated mode. This option defaults to 0. 804 805- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 806 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 807 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 808 NOTE: This flag enables use of IESB capability to reduce entry latency into 809 EL3 even when RAS error handling is not performed on the platform. Hence this 810 flag is recommended to be turned on Armv8.2 and later CPUs. 811 812- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 813 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 814 entrypoint) or 1 (CPU reset to BL31 entrypoint). 815 The default value is 0. 816 817- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 818 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 819 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 820 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 821 822- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 823- blocks) covered by a single bit of the bitlock structure during RME GPT 824- operations. The lower the block size, the better opportunity for 825- parallelising GPT operations but at the cost of more bits being needed 826- for the bitlock structure. This numeric parameter can take the values 827- from 0 to 512 and must be a power of 2. The value of 0 is special and 828- and it chooses a single spinlock for all GPT L1 table entries. Default 829- value is 1 which corresponds to block size of 512MB per bit of bitlock 830- structure. 831 832- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 833 supported contiguous blocks in GPT Library. This parameter can take the 834 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 835 descriptors. Default value is 2. 836 837- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 838 file that contains the ROT private key in PEM format or a PKCS11 URI and 839 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 840 accepted and it will be used to save the key. 841 842- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 843 certificate generation tool to save the keys used to establish the Chain of 844 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 845 846- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 847 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 848 target. 849 850- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 851 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 852 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 853 854- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 855 optional. It is only needed if the platform makefile specifies that it 856 is required in order to build the ``fwu_fip`` target. 857 858- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 859 Delegated Exception Interface to BL31 image. This defaults to ``0``. 860 861 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 862 set to ``1``. 863 864- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 865 isolated on separate memory pages. This is a trade-off between security and 866 memory usage. See "Isolating code and read-only data on separate memory 867 pages" section in :ref:`Firmware Design`. This flag is disabled by default 868 and affects all BL images. 869 870- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 871 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 872 allocated in RAM discontiguous from the loaded firmware image. When set, the 873 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 874 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 875 sections are placed in RAM immediately following the loaded firmware image. 876 877- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 878 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 879 discontiguous from loaded firmware images. When set, the platform need to 880 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 881 flag is disabled by default and NOLOAD sections are placed in RAM immediately 882 following the loaded firmware image. 883 884- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 885 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 886 UEFI+ACPI this can provide a certain amount of OS forward compatibility 887 with newer platforms that aren't ECAM compliant. 888 889- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 890 This build option is only valid if ``ARCH=aarch64``. The value should be 891 the path to the directory containing the SPD source, relative to 892 ``services/spd/``; the directory is expected to contain a makefile called 893 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 894 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 895 cannot be enabled when the ``SPM_MM`` option is enabled. 896 897- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 898 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 899 execution in BL1 just before handing over to BL31. At this point, all 900 firmware images have been loaded in memory, and the MMU and caches are 901 turned off. Refer to the "Debugging options" section for more details. 902 903- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 904 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 905 component runs at the EL3 exception level. The default value is ``0`` ( 906 disabled). This configuration supports pre-Armv8.4 platforms (aka not 907 implementing the ``FEAT_SEL2`` extension). 908 909- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 910 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 911 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 912 913- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 914 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 915 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 916 mechanism should be used. 917 918- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 919 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 920 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 921 extension. This is the default when enabling the SPM Dispatcher. When 922 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 923 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 924 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 925 extension). 926 927- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 928 Partition Manager (SPM) implementation. The default value is ``0`` 929 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 930 enabled (``SPD=spmd``). 931 932- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 933 description of secure partitions. The build system will parse this file and 934 package all secure partition blobs into the FIP. This file is not 935 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 936 937- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 938 secure interrupts (caught through the FIQ line). Platforms can enable 939 this directive if they need to handle such interruption. When enabled, 940 the FIQ are handled in monitor mode and non secure world is not allowed 941 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 942 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 943 944- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 945 Platforms can configure this if they need to lower the hardware 946 limit, for example due to asymmetric configuration or limitations of 947 software run at lower ELs. The default is the architectural maximum 948 of 2048 which should be suitable for most configurations, the 949 hardware will limit the effective VL to the maximum physically supported 950 VL. 951 952- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 953 Random Number Generator Interface to BL31 image. This defaults to ``0``. 954 955- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 956 Boot feature. When set to '1', BL1 and BL2 images include support to load 957 and verify the certificates and images in a FIP, and BL1 includes support 958 for the Firmware Update. The default value is '0'. Generation and inclusion 959 of certificates in the FIP and FWU_FIP depends upon the value of the 960 ``GENERATE_COT`` option. 961 962 .. warning:: 963 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 964 already exist in disk, they will be overwritten without further notice. 965 966- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 967 specifies a file that contains the Trusted World private key in PEM 968 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 969 it will be used to save the key. 970 971- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 972 synchronous, (see "Initializing a BL32 Image" section in 973 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 974 synchronous method) or 1 (BL32 is initialized using asynchronous method). 975 Default is 0. 976 977- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 978 routing model which routes non-secure interrupts asynchronously from TSP 979 to EL3 causing immediate preemption of TSP. The EL3 is responsible 980 for saving and restoring the TSP context in this routing model. The 981 default routing model (when the value is 0) is to route non-secure 982 interrupts to TSP allowing it to save its context and hand over 983 synchronously to EL3 via an SMC. 984 985 .. note:: 986 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 987 must also be set to ``1``. 988 989- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 990 internal-trusted-storage) as SP in tb_fw_config device tree. 991 992- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 993 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 994 this delay. It can take values in the range (0-15). Default value is ``0`` 995 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 996 Platforms need to explicitly update this value based on their requirements. 997 998- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 999 linker. When the ``LINKER`` build variable points to the armlink linker, 1000 this flag is enabled automatically. To enable support for armlink, platforms 1001 will have to provide a scatter file for the BL image. Currently, Tegra 1002 platforms use the armlink support to compile BL3-1 images. 1003 1004- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1005 memory region in the BL memory map or not (see "Use of Coherent memory in 1006 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1007 (Coherent memory region is included) or 0 (Coherent memory region is 1008 excluded). Default is 1. 1009 1010- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1011 firmware configuration framework. This will move the io_policies into a 1012 configuration device tree, instead of static structure in the code base. 1013 1014- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1015 at runtime using fconf. If this flag is enabled, COT descriptors are 1016 statically captured in tb_fw_config file in the form of device tree nodes 1017 and properties. Currently, COT descriptors used by BL2 are moved to the 1018 device tree and COT descriptors used by BL1 are retained in the code 1019 base statically. 1020 1021- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1022 runtime using firmware configuration framework. The platform specific SDEI 1023 shared and private events configuration is retrieved from device tree rather 1024 than static C structures at compile time. This is only supported if 1025 SDEI_SUPPORT build flag is enabled. 1026 1027- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1028 and Group1 secure interrupts using the firmware configuration framework. The 1029 platform specific secure interrupt property descriptor is retrieved from 1030 device tree in runtime rather than depending on static C structure at compile 1031 time. 1032 1033- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1034 This feature creates a library of functions to be placed in ROM and thus 1035 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1036 is 0. 1037 1038- ``V``: Verbose build. If assigned anything other than 0, the build commands 1039 are printed. Default is 0. 1040 1041- ``VERSION_STRING``: String used in the log output for each TF-A image. 1042 Defaults to a string formed by concatenating the version number, build type 1043 and build string. 1044 1045- ``W``: Warning level. Some compiler warning options of interest have been 1046 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1047 each level enabling more warning options. Default is 0. 1048 1049 This option is closely related to the ``E`` option, which enables 1050 ``-Werror``. 1051 1052 - ``W=0`` (default) 1053 1054 Enables a wide assortment of warnings, most notably ``-Wall`` and 1055 ``-Wextra``, as well as various bad practices and things that are likely to 1056 result in errors. Includes some compiler specific flags. No warnings are 1057 expected at this level for any build. 1058 1059 - ``W=1`` 1060 1061 Enables warnings we want the generic build to include but are too time 1062 consuming to fix at the moment. It re-enables warnings taken out for 1063 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1064 to eventually be merged into ``W=0``. Some warnings are expected on some 1065 builds, but new contributions should not introduce new ones. 1066 1067 - ``W=2`` (recommended) 1068 1069 Enables warnings we want the generic build to include but cannot be enabled 1070 due to external libraries. This level is expected to eventually be merged 1071 into ``W=0``. Lots of warnings are expected, primarily from external 1072 libraries like zlib and compiler-rt, but new controbutions should not 1073 introduce new ones. 1074 1075 - ``W=3`` 1076 1077 Enables warnings that are informative but not necessary and generally too 1078 verbose and frequently ignored. A very large number of warnings are 1079 expected. 1080 1081 The exact set of warning flags depends on the compiler and TF-A warning 1082 level, however they are all succinctly set in the top-level Makefile. Please 1083 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1084 individual flags. 1085 1086- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1087 the CPU after warm boot. This is applicable for platforms which do not 1088 require interconnect programming to enable cache coherency (eg: single 1089 cluster platforms). If this option is enabled, then warm boot path 1090 enables D-caches immediately after enabling MMU. This option defaults to 0. 1091 1092- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1093 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1094 default value of this flag is ``no``. Note this option must be enabled only 1095 for ARM architecture greater than Armv8.5-A. 1096 1097- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1098 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1099 The default value of this flag is ``0``. 1100 1101 ``AT`` speculative errata workaround disables stage1 page table walk for 1102 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1103 produces either the correct result or failure without TLB allocation. 1104 1105 This boolean option enables errata for all below CPUs. 1106 1107 +---------+--------------+-------------------------+ 1108 | Errata | CPU | Workaround Define | 1109 +=========+==============+=========================+ 1110 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1111 +---------+--------------+-------------------------+ 1112 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1113 +---------+--------------+-------------------------+ 1114 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1115 +---------+--------------+-------------------------+ 1116 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1117 +---------+--------------+-------------------------+ 1118 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1119 +---------+--------------+-------------------------+ 1120 1121 .. note:: 1122 This option is enabled by build only if platform sets any of above defines 1123 mentioned in ’Workaround Define' column in the table. 1124 If this option is enabled for the EL3 software then EL2 software also must 1125 implement this workaround due to the behaviour of the errata mentioned 1126 in new SDEN document which will get published soon. 1127 1128- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1129 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1130 This flag is disabled by default. 1131 1132- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1133 host machine where a custom installation of OpenSSL is located, which is used 1134 to build the certificate generation, firmware encryption and FIP tools. If 1135 this option is not set, the default OS installation will be used. 1136 1137- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1138 functions that wait for an arbitrary time length (udelay and mdelay). The 1139 default value is 0. 1140 1141- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1142 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1143 optional architectural feature for AArch64. This flag can take the values 1144 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1145 and it is automatically disabled when the target architecture is AArch32. 1146 1147- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1148 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1149 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1150 feature for AArch64. This flag can take the values 0 to 2, to align with the 1151 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1152 disabled when the target architecture is AArch32. 1153 1154- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1155 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1156 but unused). This feature is available if trace unit such as ETMv4.x, and 1157 ETE(extending ETM feature) is implemented. This flag can take the values 1158 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1159 1160- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1161 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1162 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1163 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1164 1165- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1166 ``plat_can_cmo`` which will return zero if cache management operations should 1167 be skipped and non-zero otherwise. By default, this option is disabled which 1168 means platform hook won't be checked and CMOs will always be performed when 1169 related functions are called. 1170 1171- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1172 firmware interface for the BL31 image. By default its disabled (``0``). 1173 1174- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1175 errata mitigation for platforms with a non-arm interconnect using the errata 1176 ABI. By default its disabled (``0``). 1177 1178- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1179 driver(s). By default it is disabled (``0``) because it constitutes an attack 1180 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1181 This option should only be enabled on a need basis if there is a use case for 1182 reading characters from the console. 1183 1184GICv3 driver options 1185-------------------- 1186 1187GICv3 driver files are included using directive: 1188 1189``include drivers/arm/gic/v3/gicv3.mk`` 1190 1191The driver can be configured with the following options set in the platform 1192makefile: 1193 1194- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1195 Enabling this option will add runtime detection support for the 1196 GIC-600, so is safe to select even for a GIC500 implementation. 1197 This option defaults to 0. 1198 1199- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1200 for GIC-600 AE. Enabling this option will introduce support to initialize 1201 the FMU. Platforms should call the init function during boot to enable the 1202 FMU and its safety mechanisms. This option defaults to 0. 1203 1204- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1205 functionality. This option defaults to 0 1206 1207- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1208 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1209 functions. This is required for FVP platform which need to simulate GIC save 1210 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1211 1212- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1213 This option defaults to 0. 1214 1215- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1216 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1217 1218Debugging options 1219----------------- 1220 1221To compile a debug version and make the build more verbose use 1222 1223.. code:: shell 1224 1225 make PLAT=<platform> DEBUG=1 V=1 all 1226 1227AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1228(for example Arm-DS) might not support this and may need an older version of 1229DWARF symbols to be emitted by GCC. This can be achieved by using the 1230``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1231the version to 4 is recommended for Arm-DS. 1232 1233When debugging logic problems it might also be useful to disable all compiler 1234optimizations by using ``-O0``. 1235 1236.. warning:: 1237 Using ``-O0`` could cause output images to be larger and base addresses 1238 might need to be recalculated (see the **Memory layout on Arm development 1239 platforms** section in the :ref:`Firmware Design`). 1240 1241Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1242``LDFLAGS``: 1243 1244.. code:: shell 1245 1246 CFLAGS='-O0 -gdwarf-2' \ 1247 make PLAT=<platform> DEBUG=1 V=1 all 1248 1249Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1250ignored as the linker is called directly. 1251 1252It is also possible to introduce an infinite loop to help in debugging the 1253post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1254``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1255section. In this case, the developer may take control of the target using a 1256debugger when indicated by the console output. When using Arm-DS, the following 1257commands can be used: 1258 1259:: 1260 1261 # Stop target execution 1262 interrupt 1263 1264 # 1265 # Prepare your debugging environment, e.g. set breakpoints 1266 # 1267 1268 # Jump over the debug loop 1269 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1270 1271 # Resume execution 1272 continue 1273 1274.. _build_options_experimental: 1275 1276Experimental build options 1277--------------------------- 1278 1279Common build options 1280~~~~~~~~~~~~~~~~~~~~ 1281 1282- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1283 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1284 set to ``1`` then measurements and additional metadata collected during the 1285 measured boot process are sent to the DICE Protection Environment for storage 1286 and processing. A certificate chain, which represents the boot state of the 1287 device, can be queried from the DPE. 1288 1289- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1290 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1291 the measurements and recording them as per `PSA DRTM specification`_. For 1292 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1293 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1294 should have mechanism to authenticate BL31. This option defaults to 0. 1295 1296- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1297 Management Extension. This flag can take the values 0 to 2, to align with 1298 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1299 1300- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1301 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1302 registers so are enabled together. Using this option without 1303 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1304 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1305 superset of SVE. SME is an optional architectural feature for AArch64. 1306 At this time, this build option cannot be used on systems that have 1307 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1308 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1309 mechanism. Default is 0. 1310 1311- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1312 version 2 (SME2) for the non-secure world only. SME2 is an optional 1313 architectural feature for AArch64. 1314 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1315 accesses will still be trapped. This flag can take the values 0 to 2, to 1316 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1317 1318- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1319 Extension for secure world. Used along with SVE and FPU/SIMD. 1320 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1321 Default is 0. 1322 1323- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1324 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1325 for logical partitions in EL3, managed by the SPMD as defined in the 1326 FF-A v1.2 specification. This flag is disabled by default. This flag 1327 must not be used if ``SPMC_AT_EL3`` is enabled. 1328 1329- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1330 verification mechanism. This is a debug feature that compares the 1331 architectural features enabled through the feature specific build flags 1332 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1333 and reports any discrepancies. 1334 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1335 1336 It is expected that this feature is only used for flexible platforms like 1337 software emulators, or for hardware platforms at bringup time, to verify 1338 that the configured feature set matches the CPU. 1339 The ``FEATURE_DETECTION`` macro is disabled by default. 1340 1341- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1342 The platform will use PSA compliant Crypto APIs during authentication and 1343 image measurement process by enabling this option. It uses APIs defined as 1344 per the `PSA Crypto API specification`_. This feature is only supported if 1345 using MbedTLS 3.x version. It is disabled (``0``) by default. 1346 1347- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1348 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1349 This defaults to ``0``. Current implementation follows the Firmware Handoff 1350 specification v0.9. 1351 1352- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1353 interface through BL31 as a SiP SMC function. 1354 Default is disabled (0). 1355 1356Firmware update options 1357~~~~~~~~~~~~~~~~~~~~~~~ 1358 1359- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1360 `PSA FW update specification`_. The default value is 0. 1361 PSA firmware update implementation has few limitations, such as: 1362 1363 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1364 be updated, then it should be done through another platform-defined 1365 mechanism. 1366 1367 - It assumes the platform's hardware supports CRC32 instructions. 1368 1369- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1370 in defining the firmware update metadata structure. This flag is by default 1371 set to '2'. 1372 1373- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1374 firmware bank. Each firmware bank must have the same number of images as per 1375 the `PSA FW update specification`_. 1376 This flag is used in defining the firmware update metadata structure. This 1377 flag is by default set to '1'. 1378 1379- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1380 metadata contains image description. The default value is 1. 1381 1382 The version 2 of the FWU metadata allows for an opaque metadata 1383 structure where a platform can choose to not include the firmware 1384 store description in the metadata structure. This option indicates 1385 if the firmware store description, which provides information on 1386 the updatable images is part of the structure. 1387 1388-------------- 1389 1390*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 1391 1392.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1393.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1394.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1395.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1396.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1397.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1398.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1399