1 /* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <cortex_a520.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/board_css_def.h> 14 #include <plat/arm/board/common/v2m_def.h> 15 #include <plat/arm/common/arm_def.h> 16 #include <plat/arm/common/arm_spm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 #include <plat/common/common_def.h> 20 21 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 22 23 /* 24 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 25 * its base is ARM_AP_TZC_DRAM1_BASE. 26 * 27 * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: 28 * - BL32_BASE when SPD_spmd is enabled 29 * - Region to load secure partitions 30 * 31 * 32 * 0x8000_0000 ------------------ TC_NS_DRAM1_BASE 33 * | DTB | 34 * | (32K) | 35 * 0x8000_8000 ------------------ 36 * | NT_FW_CONFIG | 37 * | (4KB) | 38 * 0x8000_9000 ------------------ 39 * | ... | 40 * 0xf8a0_0000 ------------------ TC_NS_FWU_BASE 41 * | FWU shmem | 42 * | (4MB) | 43 * 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE 44 * | OP-TEE shmem | 45 * | (2MB) | 46 * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE 47 * | | 48 * | SPMC | 49 * | SP | 50 * | (96MB) | 51 * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE 52 * | AP | 53 * | EL3 Monitor | 54 * | SCP | 55 * | (16MB) | 56 * 0xFFFF_FFFF ------------------ 57 * 58 * 59 */ 60 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 61 TC_TZC_DRAM1_SIZE) 62 #define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */ 63 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 64 TC_TZC_DRAM1_SIZE - 1) 65 66 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 67 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 68 ARM_TZC_DRAM1_SIZE - \ 69 TC_TZC_DRAM1_SIZE) 70 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1) 71 72 #define TC_NS_OPTEE_SIZE (2 * SZ_1M) 73 #define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE) 74 #define TC_NS_FWU_SIZE (4 * SZ_1M) 75 #define TC_NS_FWU_BASE (TC_NS_OPTEE_BASE - TC_NS_FWU_SIZE) 76 77 /* 78 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 79 */ 80 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 81 TC_NS_DRAM1_BASE, \ 82 TC_NS_DRAM1_SIZE, \ 83 MT_MEMORY | MT_RW | MT_NS) 84 85 86 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 87 TC_TZC_DRAM1_BASE, \ 88 TC_TZC_DRAM1_SIZE, \ 89 MT_MEMORY | MT_RW | MT_SECURE) 90 91 #define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE 92 #define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000) 93 94 #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ 95 PLAT_HW_CONFIG_DTB_BASE, \ 96 PLAT_ARM_HW_CONFIG_SIZE, \ 97 MT_MEMORY | MT_RO | MT_NS) 98 /* 99 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 100 * max size of BL32 image. 101 */ 102 #if defined(SPD_spmd) 103 #define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) 104 105 #define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR 106 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 107 #endif 108 109 /* 110 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 111 * plat_arm_mmap array defined for each BL stage. 112 */ 113 #if defined(IMAGE_BL31) 114 # if SPM_MM 115 # define PLAT_ARM_MMAP_ENTRIES 9 116 # define MAX_XLAT_TABLES 7 117 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 118 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 119 # else 120 # define PLAT_ARM_MMAP_ENTRIES 8 121 # define MAX_XLAT_TABLES 8 122 # endif 123 #elif defined(IMAGE_BL32) 124 # define PLAT_ARM_MMAP_ENTRIES 8 125 # define MAX_XLAT_TABLES 5 126 #elif !USE_ROMLIB 127 # define PLAT_ARM_MMAP_ENTRIES 11 128 # define MAX_XLAT_TABLES 7 129 #else 130 # define PLAT_ARM_MMAP_ENTRIES 12 131 # define MAX_XLAT_TABLES 6 132 #endif 133 134 /* 135 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 136 * plus a little space for growth. 137 */ 138 #define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000 139 140 /* 141 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 142 */ 143 144 #if USE_ROMLIB 145 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 146 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 147 #else 148 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 149 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 150 #endif 151 152 /* 153 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 154 * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT 155 * and MEASURED_BOOT is enabled. 156 */ 157 # define PLAT_ARM_MAX_BL2_SIZE 0x29000 158 159 160 /* 161 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 162 * calculated using the current BL31 PROGBITS debug size plus the sizes of 163 * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and 164 * MEASURED_BOOT is enabled. 165 */ 166 #define PLAT_ARM_MAX_BL31_SIZE 0x60000 167 168 /* 169 * Size of cacheable stacks 170 */ 171 #if defined(IMAGE_BL1) 172 # define PLATFORM_STACK_SIZE 0x1000 173 #elif defined(IMAGE_BL2) 174 # define PLATFORM_STACK_SIZE 0x1000 175 #elif defined(IMAGE_BL2U) 176 # define PLATFORM_STACK_SIZE 0x400 177 #elif defined(IMAGE_BL31) 178 # if SPM_MM 179 # define PLATFORM_STACK_SIZE 0x500 180 # else 181 # define PLATFORM_STACK_SIZE 0xa00 182 # endif 183 #elif defined(IMAGE_BL32) 184 # define PLATFORM_STACK_SIZE 0x440 185 #endif 186 187 /* 188 * In the current implementation the RoT Service request that requires the 189 * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 190 * maximum required buffer size is calculated based on the platform-specific 191 * needs of this request. 192 */ 193 #define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE 0x500 194 195 #define TC_DEVICE_BASE 0x21000000 196 #define TC_DEVICE_SIZE 0x5f000000 197 198 #if defined(TARGET_FLAVOUR_FPGA) 199 #undef V2M_FLASH0_BASE 200 #undef V2M_FLASH0_SIZE 201 #define V2M_FLASH0_BASE UL(0x0C000000) 202 #define V2M_FLASH0_SIZE UL(0x02000000) 203 #endif 204 205 // TC_MAP_DEVICE covers different peripherals 206 // available to the platform 207 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 208 TC_DEVICE_BASE, \ 209 TC_DEVICE_SIZE, \ 210 MT_DEVICE | MT_RW | MT_SECURE) 211 212 213 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 214 V2M_FLASH0_SIZE, \ 215 MT_DEVICE | MT_RO | MT_SECURE) 216 217 #define PLAT_ARM_NSTIMER_FRAME_ID 0 218 219 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 220 221 /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ 222 #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) 223 224 #define PLAT_ARM_NSRAM_BASE 0x06000000 225 #if TARGET_FLAVOUR_FVP 226 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 227 #else /* TARGET_FLAVOUR_FPGA */ 228 #define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */ 229 #endif /* TARGET_FLAVOUR_FPGA */ 230 231 #if TARGET_PLATFORM <= 2 232 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 233 #elif TARGET_PLATFORM == 3 234 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 235 #endif /* TARGET_PLATFORM == 3 */ 236 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 237 #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) 238 239 #define TC_NS_MTE_SIZE (256 * SZ_1M) 240 /* the SCP puts the carveout at the end of DRAM2 */ 241 #define TC_NS_DRAM2_SIZE (PLAT_ARM_DRAM2_SIZE - TC_NS_MTE_SIZE) 242 243 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) 244 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ 245 INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ 246 GIC_HIGHEST_SEC_PRIORITY, grp, \ 247 GIC_INTR_CFG_LEVEL) 248 249 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 250 PLAT_SP_IMAGE_NS_BUF_SIZE) 251 252 #define PLAT_ARM_SP_MAX_SIZE U(0x2000000) 253 254 /******************************************************************************* 255 * Memprotect definitions 256 ******************************************************************************/ 257 /* PSCI memory protect definitions: 258 * This variable is stored in a non-secure flash because some ARM reference 259 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 260 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 261 */ 262 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 263 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 264 265 /* Secure Watchdog Constants */ 266 #define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) 267 #define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) 268 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 269 #define SBSA_SECURE_WDOG_INTID 86 270 271 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 272 273 /* Index of SDS region used in the communication with SCP */ 274 #define SDS_SCP_AP_REGION_ID U(0) 275 /* Index of SDS region used in the communication with RSE */ 276 #define SDS_RSE_AP_REGION_ID U(1) 277 /* 278 * Memory region for RSE's shared data storage (SDS) 279 * It is placed right after the SCMI payload area. 280 */ 281 #define PLAT_ARM_RSE_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \ 282 CSS_SCMI_PAYLOAD_SIZE_MAX) 283 284 #define PLAT_ARM_CLUSTER_COUNT U(1) 285 #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 286 #define PLAT_MAX_CPUS_PER_CLUSTER U(14) 287 #else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 288 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 289 #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 290 #define PLAT_MAX_PE_PER_CPU U(1) 291 292 #define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT) 293 294 /* Message Handling Unit (MHU) base addresses */ 295 #if TARGET_PLATFORM <= 2 296 #define PLAT_CSS_MHU_BASE UL(0x45400000) 297 #elif TARGET_PLATFORM == 3 298 #define PLAT_CSS_MHU_BASE UL(0x46000000) 299 #endif /* TARGET_PLATFORM == 3 */ 300 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 301 302 /* AP<->RSS MHUs */ 303 #if TARGET_PLATFORM <= 2 304 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x2A840000) 305 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x2A850000) 306 #elif TARGET_PLATFORM == 3 307 #define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000) 308 #define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000) 309 #endif 310 311 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 312 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 313 314 /* 315 * Physical and virtual address space limits for MMU in AARCH64 316 */ 317 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 318 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 319 320 /* GIC related constants */ 321 #define PLAT_ARM_GICD_BASE UL(0x30000000) 322 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 323 #define PLAT_ARM_GICR_BASE UL(0x30080000) 324 325 /* 326 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 327 * SCP_BL2 size plus a little space for growth. 328 */ 329 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000 330 331 /* 332 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 333 * SCP_BL2U size plus a little space for growth. 334 */ 335 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000 336 337 #if TARGET_PLATFORM <= 2 338 /* TZC Related Constants */ 339 #define PLAT_ARM_TZC_BASE UL(0x25000000) 340 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 341 342 #define TZC400_OFFSET UL(0x1000000) 343 #define TZC400_COUNT 4 344 345 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 346 (n * TZC400_OFFSET)) 347 348 #define TZC_NSAID_DEFAULT U(0) 349 350 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 351 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) 352 353 /* 354 * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to 355 * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as 356 * secure. The second and third regions gives non secure access to rest of DRAM. 357 */ 358 #define TC_TZC_REGIONS_DEF \ 359 {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ 360 TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 361 {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 362 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 363 {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \ 364 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 365 #endif 366 367 /* virtual address used by dynamic mem_protect for chunk_base */ 368 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 369 370 #if ARM_GPT_SUPPORT 371 /* 372 * This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h. 373 * Offset of the FIP in the GPT image. BL1 component uses this option 374 * as it does not load the partition table to get the FIP base 375 * address. At sector 48 for TC to align with ATU page size boundaries (8KiB) 376 * (i.e. after reserved sectors 0-47). 377 * Offset = 48 * 512 = 0x6000 378 */ 379 #undef PLAT_ARM_FIP_OFFSET_IN_GPT 380 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000 381 #endif /* ARM_GPT_SUPPORT */ 382 383 /* UART related constants */ 384 385 #define TC_UART0 0x2a400000 386 #define TC_UART1 0x2a410000 387 388 /* 389 * TODO: if any more undefs are needed, it's better to consider dropping the 390 * board_css_def.h include above 391 */ 392 #undef PLAT_ARM_BOOT_UART_BASE 393 #undef PLAT_ARM_RUN_UART_BASE 394 395 #undef PLAT_ARM_CRASH_UART_BASE 396 #undef PLAT_ARM_BOOT_UART_CLK_IN_HZ 397 #undef PLAT_ARM_RUN_UART_CLK_IN_HZ 398 399 #if TARGET_FLAVOUR_FVP 400 #define PLAT_ARM_BOOT_UART_BASE TC_UART1 401 #define TC_UARTCLK 7372800 402 #else /* TARGET_FLAVOUR_FPGA */ 403 #define PLAT_ARM_BOOT_UART_BASE TC_UART0 404 #if TARGET_PLATFORM <= 2 405 #define TC_UARTCLK 5000000 406 #elif TARGET_PLATFORM >= 3 407 #define TC_UARTCLK 3750000 408 #endif /* TARGET_PLATFORM >= 3 */ 409 #undef ARM_CONSOLE_BAUDRATE 410 #define ARM_CONSOLE_BAUDRATE 38400 411 #endif /* TARGET_FLAVOUR_FPGA */ 412 413 #define PLAT_ARM_RUN_UART_BASE TC_UART0 414 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 415 416 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK 417 #define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK 418 419 #if TARGET_PLATFORM == 3 420 #define NCI_BASE_ADDR UL(0x4F000000) 421 #ifdef TARGET_FLAVOUR_FPGA 422 #define MCN_ADDRESS_SPACE_SIZE 0x00120000 423 #else 424 #define MCN_ADDRESS_SPACE_SIZE 0x00130000 425 #endif /* TARGET_FLAVOUR_FPGA */ 426 #define MCN_OFFSET_IN_NCI 0x00C90000 427 #define MCN_BASE_ADDR (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI) 428 #define MCN_PMU_OFFSET 0x000C4000 429 #define MCN_MICROARCH_OFFSET 0x000E4000 430 #define MCN_MICROARCH_BASE_ADDR (MCN_BASE_ADDR + MCN_MICROARCH_OFFSET) 431 #define MCN_SCR_OFFSET 0x4 432 #define MCN_SCR_PMU_BIT 10 433 #define MCN_INSTANCES 4 434 #define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \ 435 (n * MCN_ADDRESS_SPACE_SIZE) + \ 436 MCN_PMU_OFFSET) 437 #define MCN_MPAM_NS_OFFSET 0x000D0000 438 #define MCN_MPAM_NS_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_NS_OFFSET) 439 #define MCN_MPAM_S_OFFSET 0x000D4000 440 #define MCN_MPAM_S_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_S_OFFSET) 441 #define MPAM_SLCCFG_CTL_OFFSET 0x00003018 442 #define SLC_RDALLOCMODE_SHIFT 8 443 #define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT) 444 #define SLC_WRALLOCMODE_SHIFT 12 445 #define SLC_WRALLOCMODE_MASK (3 << SLC_WRALLOCMODE_SHIFT) 446 447 #define SLC_DONT_ALLOC 0 448 #define SLC_ALWAYS_ALLOC 1 449 #define SLC_ALLOC_BUS_SIGNAL_ATTR 2 450 451 #define MCN_CONFIG_OFFSET 0x204 452 #define MCN_CONFIG_ADDR (MCN_BASE_ADDR + MCN_CONFIG_OFFSET) 453 #define MCN_CONFIG_SLC_PRESENT_BIT 3 454 455 /* 456 * TC3 CPUs have the same definitions for: 457 * CORTEX_{A520|A725|X925}_CPUECTLR_EL1 458 * CORTEX_{A520|A725|X925}_CPUECTLR_EL1_EXTLLC_BIT 459 * Define the common macros for easier using. 460 */ 461 #define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1 462 #define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT 463 #endif /* TARGET_PLATFORM == 3 */ 464 465 #define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12) 466 467 #endif /* PLATFORM_DEF_H */ 468