1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/partition/partition.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <lib/gpt_rme/gpt_rme.h> 22 #if TRANSFER_LIST 23 #include <lib/transfer_list.h> 24 #endif 25 #ifdef SPD_opteed 26 #include <lib/optee_utils.h> 27 #endif 28 #include <lib/utils.h> 29 #include <plat/arm/common/plat_arm.h> 30 #include <plat/common/platform.h> 31 32 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 33 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 34 35 /* Base address of fw_config received from BL1 */ 36 static uintptr_t config_base __unused; 37 38 /* 39 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 40 * for `meminfo_t` data structure and fw_configs passed from BL1. 41 */ 42 #if TRANSFER_LIST 43 CASSERT(BL2_BASE >= PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE, 44 assert_bl2_base_overflows); 45 #else 46 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 47 #endif /* TRANSFER_LIST */ 48 49 /* Weak definitions may be overridden in specific ARM standard platform */ 50 #pragma weak bl2_early_platform_setup2 51 #pragma weak bl2_platform_setup 52 #pragma weak bl2_plat_arch_setup 53 #pragma weak bl2_plat_sec_mem_layout 54 55 #if ENABLE_RME 56 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 57 bl2_tzram_layout.total_base, \ 58 bl2_tzram_layout.total_size, \ 59 MT_MEMORY | MT_RW | MT_ROOT) 60 #else 61 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 62 bl2_tzram_layout.total_base, \ 63 bl2_tzram_layout.total_size, \ 64 MT_MEMORY | MT_RW | MT_SECURE) 65 #endif /* ENABLE_RME */ 66 67 #pragma weak arm_bl2_plat_handle_post_image_load 68 69 static struct transfer_list_header *secure_tl __unused; 70 static struct transfer_list_header *ns_tl __unused; 71 72 /******************************************************************************* 73 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 74 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 75 * Copy it to a safe location before its reclaimed by later BL2 functionality. 76 ******************************************************************************/ 77 void arm_bl2_early_platform_setup(uintptr_t fw_config, 78 struct meminfo *mem_layout) 79 { 80 struct transfer_list_entry *te __unused; 81 int __maybe_unused ret; 82 83 /* Initialize the console to provide early debug support */ 84 arm_console_boot_init(); 85 86 #if TRANSFER_LIST 87 // TODO: modify the prototype of this function fw_config != bl2_tl 88 secure_tl = (struct transfer_list_header *)fw_config; 89 90 te = transfer_list_find(secure_tl, TL_TAG_SRAM_LAYOUT64); 91 assert(te != NULL); 92 93 bl2_tzram_layout = *(meminfo_t *)transfer_list_entry_data(te); 94 transfer_list_rem(secure_tl, te); 95 #else 96 config_base = fw_config; 97 98 /* Setup the BL2 memory layout */ 99 bl2_tzram_layout = *mem_layout; 100 #endif 101 102 /* Initialise the IO layer and register platform IO devices */ 103 plat_arm_io_setup(); 104 105 /* Load partition table */ 106 #if ARM_GPT_SUPPORT 107 ret = gpt_partition_init(); 108 if (ret != 0) { 109 ERROR("GPT partition initialisation failed!\n"); 110 panic(); 111 } 112 113 #endif /* ARM_GPT_SUPPORT */ 114 } 115 116 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 117 { 118 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 119 120 generic_delay_timer_init(); 121 } 122 123 /* 124 * Perform BL2 preload setup. Currently we initialise the dynamic 125 * configuration here. 126 */ 127 void bl2_plat_preload_setup(void) 128 { 129 #if TRANSFER_LIST 130 /* Assume the secure TL hasn't been initialised if BL2 is running at EL3. */ 131 #if RESET_TO_BL2 132 secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE, 133 PLAT_ARM_FW_HANDOFF_SIZE); 134 135 if (secure_tl == NULL) { 136 ERROR("Secure transfer list initialisation failed!\n"); 137 panic(); 138 } 139 #endif 140 141 arm_transfer_list_dyn_cfg_init(secure_tl); 142 #else 143 arm_bl2_dyn_cfg_init(); 144 #endif 145 146 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 147 /* Always use the FIP from bank 0 */ 148 arm_set_fip_addr(0U); 149 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 150 } 151 152 /* 153 * Perform ARM standard platform setup. 154 */ 155 void arm_bl2_platform_setup(void) 156 { 157 #if !ENABLE_RME 158 /* Initialize the secure environment */ 159 plat_arm_security_setup(); 160 #endif 161 162 #if defined(PLAT_ARM_MEM_PROT_ADDR) 163 arm_nor_psci_do_static_mem_protect(); 164 #endif 165 } 166 167 void bl2_platform_setup(void) 168 { 169 arm_bl2_platform_setup(); 170 } 171 172 /******************************************************************************* 173 * Perform the very early platform specific architectural setup here. 174 * When RME is enabled the secure environment is initialised before 175 * initialising and enabling Granule Protection. 176 * This function initialises the MMU in a quick and dirty way. 177 ******************************************************************************/ 178 void arm_bl2_plat_arch_setup(void) 179 { 180 #if USE_COHERENT_MEM 181 /* Ensure ARM platforms don't use coherent memory in BL2. */ 182 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 183 #endif 184 185 const mmap_region_t bl_regions[] = { 186 MAP_BL2_TOTAL, 187 ARM_MAP_BL_RO, 188 #if USE_ROMLIB 189 ARM_MAP_ROMLIB_CODE, 190 ARM_MAP_ROMLIB_DATA, 191 #endif 192 #if !TRANSFER_LIST 193 ARM_MAP_BL_CONFIG_REGION, 194 #endif /* TRANSFER_LIST */ 195 #if ENABLE_RME 196 ARM_MAP_L0_GPT_REGION, 197 #endif 198 { 0 } 199 }; 200 201 #if ENABLE_RME 202 /* Initialise the secure environment */ 203 plat_arm_security_setup(); 204 #endif 205 setup_page_tables(bl_regions, plat_arm_get_mmap()); 206 207 #ifdef __aarch64__ 208 #if ENABLE_RME 209 /* BL2 runs in EL3 when RME enabled. */ 210 assert(is_feat_rme_present()); 211 enable_mmu_el3(0); 212 213 /* Initialise and enable granule protection after MMU. */ 214 arm_gpt_setup(); 215 #else 216 enable_mmu_el1(0); 217 #endif 218 #else 219 enable_mmu_svc_mon(0); 220 #endif 221 222 arm_setup_romlib(); 223 } 224 225 void bl2_plat_arch_setup(void) 226 { 227 const struct dyn_cfg_dtb_info_t *tb_fw_config_info __unused; 228 struct transfer_list_entry *te __unused; 229 arm_bl2_plat_arch_setup(); 230 231 #if TRANSFER_LIST 232 te = transfer_list_find(secure_tl, TL_TAG_TB_FW_CONFIG); 233 assert(te != NULL); 234 235 fconf_populate("TB_FW", (uintptr_t)transfer_list_entry_data(te)); 236 transfer_list_rem(secure_tl, te); 237 #else 238 /* Fill the properties struct with the info from the config dtb */ 239 fconf_populate("FW_CONFIG", config_base); 240 241 /* TB_FW_CONFIG was also loaded by BL1 */ 242 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 243 assert(tb_fw_config_info != NULL); 244 245 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 246 #endif 247 } 248 249 int arm_bl2_handle_post_image_load(unsigned int image_id) 250 { 251 int err = 0; 252 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 253 #ifdef SPD_opteed 254 bl_mem_params_node_t *pager_mem_params = NULL; 255 bl_mem_params_node_t *paged_mem_params = NULL; 256 #endif 257 assert(bl_mem_params != NULL); 258 259 switch (image_id) { 260 #ifdef __aarch64__ 261 case BL32_IMAGE_ID: 262 #ifdef SPD_opteed 263 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 264 assert(pager_mem_params); 265 266 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 267 assert(paged_mem_params); 268 269 err = parse_optee_header(&bl_mem_params->ep_info, 270 &pager_mem_params->image_info, 271 &paged_mem_params->image_info); 272 if (err != 0) { 273 WARN("OPTEE header parse error.\n"); 274 } 275 #endif 276 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 277 break; 278 #endif 279 280 case BL33_IMAGE_ID: 281 /* BL33 expects to receive the primary CPU MPID (through r0) */ 282 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 283 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 284 break; 285 286 #ifdef SCP_BL2_BASE 287 case SCP_BL2_IMAGE_ID: 288 /* The subsequent handling of SCP_BL2 is platform specific */ 289 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 290 if (err) { 291 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 292 } 293 break; 294 #endif 295 default: 296 /* Do nothing in default case */ 297 break; 298 } 299 300 return err; 301 } 302 303 /******************************************************************************* 304 * This function can be used by the platforms to update/use image 305 * information for given `image_id`. 306 ******************************************************************************/ 307 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 308 { 309 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 310 /* For Secure Partitions we don't need post processing */ 311 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 312 (image_id < MAX_NUMBER_IDS)) { 313 return 0; 314 } 315 #endif 316 317 #if TRANSFER_LIST 318 if (image_id == HW_CONFIG_ID) { 319 /* Refresh the now stale checksum following loading of HW_CONFIG into the TL. */ 320 transfer_list_update_checksum(secure_tl); 321 } 322 #endif /* TRANSFER_LIST */ 323 324 return arm_bl2_handle_post_image_load(image_id); 325 } 326 327 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node) 328 { 329 entry_point_info_t *ep __unused; 330 ep = transfer_list_set_handoff_args(secure_tl, 331 &next_param_node->ep_info); 332 assert(ep != NULL); 333 334 arm_transfer_list_populate_ep_info(next_param_node, secure_tl); 335 } 336