1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #define PLAT_PRIMARY_CPU (0x0) 12 13 #define MT_GIC_BASE (0x0C000000) 14 #define MCUCFG_BASE (0x0C530000) 15 #define IO_PHYS (0x10000000) 16 17 /* Aggregate of all devices for MMU mapping */ 18 #define MTK_DEV_RNG0_BASE IO_PHYS 19 #define MTK_DEV_RNG0_SIZE (0x10000000) 20 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 21 #define MTK_DEV_RNG2_SIZE (0x600000) 22 #define MTK_MCDI_SRAM_BASE (0x11B000) 23 #define MTK_MCDI_SRAM_MAP_SIZE (0x1000) 24 25 #define TOPCKGEN_BASE (IO_PHYS + 0x00000000) 26 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 27 #define SPM_BASE (IO_PHYS + 0x00006000) 28 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 29 #define SSPM_MBOX_BASE (IO_PHYS + 0x00480000) 30 #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) 31 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 32 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 33 #define VDOSYS0_BASE (IO_PHYS + 0x0C01A000) 34 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 35 36 /******************************************************************************* 37 * GPIO related constants 38 ******************************************************************************/ 39 #define TOPCKGEN_BASE (IO_PHYS + 0x00000000) 40 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 41 #define GPIO_BASE (IO_PHYS + 0x00005000) 42 #define SPM_BASE (IO_PHYS + 0x00006000) 43 #define IOCFG_LT_BASE (IO_PHYS + 0x00002000) 44 #define IOCFG_LM_BASE (IO_PHYS + 0x00002200) 45 #define IOCFG_LB_BASE (IO_PHYS + 0x00002400) 46 #define IOCFG_BL_BASE (IO_PHYS + 0x00002600) 47 #define IOCFG_RB_BASE (IO_PHYS + 0x00002A00) 48 #define IOCFG_RT_BASE (IO_PHYS + 0x00002C00) 49 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 50 #define DVFSRC_BASE (IO_PHYS + 0x00012000) 51 #define MMSYS_BASE (IO_PHYS + 0x04000000) 52 #define MDPSYS_BASE (IO_PHYS + 0x0B000000) 53 54 /******************************************************************************* 55 * UART related constants 56 ******************************************************************************/ 57 #define UART0_BASE (IO_PHYS + 0x01002000) 58 #define UART1_BASE (IO_PHYS + 0x01003000) 59 60 #define UART_BAUDRATE (115200) 61 62 /******************************************************************************* 63 * PWRAP related constants 64 ******************************************************************************/ 65 #define PMIC_WRAP_BASE (IO_PHYS + 0x0000D000) 66 67 /******************************************************************************* 68 * EMI MPU related constants 69 ******************************************************************************/ 70 #define EMI_MPU_BASE (IO_PHYS + 0x0021B000) 71 72 /******************************************************************************* 73 * GIC-600 & interrupt handling related constants 74 ******************************************************************************/ 75 /* Base MTK_platform compatible GIC memory map */ 76 #define BASE_GICD_BASE MT_GIC_BASE 77 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 78 79 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 80 #define CIRQ_REG_NUM (11) 81 #define CIRQ_IRQ_NUM (326) 82 #define CIRQ_SPI_START (64) 83 #define MD_WDT_IRQ_BIT_ID (107) 84 /******************************************************************************* 85 * System counter frequency related constants 86 ******************************************************************************/ 87 #define SYS_COUNTER_FREQ_IN_TICKS (13000000) 88 #define SYS_COUNTER_FREQ_IN_MHZ (13) 89 90 /******************************************************************************* 91 * Platform binary types for linking 92 ******************************************************************************/ 93 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 94 #define PLATFORM_LINKER_ARCH aarch64 95 96 /******************************************************************************* 97 * Generic platform constants 98 ******************************************************************************/ 99 #define PLATFORM_STACK_SIZE 0x800 100 101 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 102 103 #define PLAT_MAX_PWR_LVL U(3) 104 #define PLAT_MAX_RET_STATE U(1) 105 #define PLAT_MAX_OFF_STATE U(9) 106 107 #define PLATFORM_SYSTEM_COUNT U(1) 108 #define PLATFORM_MCUSYS_COUNT U(1) 109 #define PLATFORM_CLUSTER_COUNT U(1) 110 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 111 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 112 113 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 114 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 115 116 #define SOC_CHIP_ID U(0x8186) 117 118 /******************************************************************************* 119 * Platform memory map related constants 120 ******************************************************************************/ 121 #define TZRAM_BASE (0x54600000) 122 #define TZRAM_SIZE (0x00030000) 123 124 /******************************************************************************* 125 * BL31 specific defines. 126 ******************************************************************************/ 127 /* 128 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 129 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 130 * little space for growth. 131 */ 132 #define BL31_BASE (TZRAM_BASE + 0x1000) 133 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 134 135 /******************************************************************************* 136 * Platform specific page table and MMU setup constants 137 ******************************************************************************/ 138 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 139 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 140 #define MAX_XLAT_TABLES (16) 141 #define MAX_MMAP_REGIONS (16) 142 143 /******************************************************************************* 144 * Declarations and constants to access the mailboxes safely. Each mailbox is 145 * aligned on the biggest cache line size in the platform. This is known only 146 * to the platform as it might have a combination of integrated and external 147 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 148 * line at any cache level. They could belong to different cpus/clusters & 149 * get written while being protected by different locks causing corruption of 150 * a valid mailbox address. 151 ******************************************************************************/ 152 #define CACHE_WRITEBACK_SHIFT (6) 153 #define CACHE_WRITEBACK_GRANULE BIT(CACHE_WRITEBACK_SHIFT) 154 #endif /* PLATFORM_DEF_H */ 155