1 /* 2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_DEF_H 10 #define VERSAL_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define PLATFORM_MASK GENMASK(27U, 24U) 16 #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 17 18 /* number of interrupt handlers. increase as required */ 19 #define MAX_INTR_EL3 2 20 /* List all consoles */ 21 #define VERSAL_CONSOLE_ID_pl011 1 22 #define VERSAL_CONSOLE_ID_pl011_0 1 23 #define VERSAL_CONSOLE_ID_pl011_1 2 24 #define VERSAL_CONSOLE_ID_dcc 3 25 26 #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 27 28 /* List of platforms */ 29 #define VERSAL_SILICON U(0) 30 #define VERSAL_SPP U(1) 31 #define VERSAL_EMU U(2) 32 #define VERSAL_QEMU U(3) 33 34 /* Firmware Image Package */ 35 #define VERSAL_PRIMARY_CPU 0 36 37 /******************************************************************************* 38 * memory map related constants 39 ******************************************************************************/ 40 #define DEVICE0_BASE 0xFF000000 41 #define DEVICE0_SIZE 0x00E00000 42 #define DEVICE1_BASE 0xF9000000 43 #define DEVICE1_SIZE 0x00800000 44 45 /******************************************************************************* 46 * IRQ constants 47 ******************************************************************************/ 48 #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 49 #define ARM_IRQ_SEC_PHY_TIMER 29 50 51 /******************************************************************************* 52 * CCI-400 related constants 53 ******************************************************************************/ 54 #define PLAT_ARM_CCI_BASE 0xFD000000 55 #define PLAT_ARM_CCI_SIZE 0x00100000 56 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 57 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 58 59 /******************************************************************************* 60 * UART related constants 61 ******************************************************************************/ 62 #define VERSAL_UART0_BASE 0xFF000000 63 #define VERSAL_UART1_BASE 0xFF010000 64 65 #if CONSOLE_IS(pl011) || CONSOLE_IS(dcc) 66 # define UART_BASE VERSAL_UART0_BASE 67 #elif CONSOLE_IS(pl011_1) 68 # define UART_BASE VERSAL_UART1_BASE 69 #else 70 # error "invalid VERSAL_CONSOLE" 71 #endif 72 73 /******************************************************************************* 74 * Platform related constants 75 ******************************************************************************/ 76 #define UART_BAUDRATE 115200 77 78 /* Access control register defines */ 79 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 80 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 81 82 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 83 #define CRF_BASE 0xFD1A0000 84 #define CRF_SIZE 0x00600000 85 86 /* CRF registers and bitfields */ 87 #define CRF_RST_APU (CRF_BASE + 0X00000300) 88 89 #define CRF_RST_APU_ACPU_RESET (1 << 0) 90 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 91 92 /* IOU SCNTRS */ 93 #define IOU_SCNTRS_BASE U(0xFF140000) 94 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 95 96 /* APU registers and bitfields */ 97 #define FPD_APU_BASE 0xFD5C0000U 98 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 99 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 100 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 101 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 102 103 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 104 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 105 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 106 107 /* PMC registers and bitfields */ 108 #define PMC_GLOBAL_BASE 0xF1110000U 109 #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 110 111 #endif /* VERSAL_DEF_H */ 112