1/* 2 * Copyright (c) 2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a510.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240 25 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ 26 sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \ 27 CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH 28workaround_reset_end cortex_a510, ERRATUM(1922240) 29 30check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0) 31 32workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909 33 /* Apply workaround */ 34 mov x0, xzr 35 msr S3_6_C15_C4_0, x0 36 isb 37 38 mov x0, #0x8500000 39 msr S3_6_C15_C4_2, x0 40 41 mov x0, #0x1F700000 42 movk x0, #0x8, lsl #32 43 msr S3_6_C15_C4_3, x0 44 45 mov x0, #0x3F1 46 movk x0, #0x110, lsl #16 47 msr S3_6_C15_C4_1, x0 48workaround_reset_end cortex_a510, ERRATUM(2041909) 49 50check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2) 51 52workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739 53 /* Apply the workaround by disabling ReadPreferUnique. */ 54 sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \ 55 CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH 56workaround_reset_end cortex_a510, ERRATUM(2042739) 57 58check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2) 59 60workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148 61 /* 62 * Force L2 allocation of transient lines by setting 63 * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01. 64 */ 65 mrs x0, CORTEX_A510_CPUECTLR_EL1 66 mov x1, #1 67 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2 68 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2 69 msr CORTEX_A510_CPUECTLR_EL1, x0 70workaround_reset_end cortex_a510, ERRATUM(2172148) 71 72check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0) 73 74workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950 75 /* Set bit 18 in CPUACTLR_EL1 */ 76 sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ 77 CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH 78 79 /* Set bit 25 in CMPXACTLR_EL1 */ 80 sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ 81 CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH 82 83workaround_reset_end cortex_a510, ERRATUM(2218950) 84 85check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0) 86 87 /* -------------------------------------------------- 88 * This workaround is not a typical errata fix. MPMM 89 * is disabled here, but this conflicts with the BL31 90 * MPMM support. So in addition to simply disabling 91 * the feature, a flag is set in the MPMM library 92 * indicating that it should not be enabled even if 93 * ENABLE_MPMM=1. 94 * -------------------------------------------------- 95 */ 96workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311 97 /* Disable MPMM */ 98 mrs x0, CPUMPMMCR_EL3 99 bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ 100 msr CPUMPMMCR_EL3, x0 101 102#if ENABLE_MPMM && IMAGE_BL31 103 /* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */ 104 bl mpmm_errata_disable 105#endif 106workaround_reset_end cortex_a510, ERRATUM(2250311) 107 108check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0) 109 110workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014 111 /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ 112 sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \ 113 CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH 114workaround_reset_end cortex_a510, ERRATUM(2288014) 115 116check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0) 117 118workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730 119 /* 120 * Set CPUACTLR_EL1[17] to 1'b1, which disables 121 * specific microarchitectural clock gating 122 * behaviour. 123 */ 124 sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17 125workaround_reset_end cortex_a510, ERRATUM(2347730) 126 127check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1) 128 129workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937 130 /* 131 * Cacheable atomic operations can be forced 132 * to be executed near by setting 133 * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found 134 * in [40:38] of CPUECTLR_EL1. 135 */ 136 sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \ 137 CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH 138workaround_reset_end cortex_a510, ERRATUM(2371937) 139 140check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1) 141 142workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669 143 sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38 144workaround_reset_end cortex_a510, ERRATUM(2666669) 145 146check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1) 147 148.global erratum_cortex_a510_2684597_wa 149workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR 150 /* 151 * Many assemblers do not yet understand the "tsb csync" mnemonic, 152 * so use the equivalent hint instruction. 153 */ 154 hint #18 /* tsb csync */ 155workaround_runtime_end cortex_a510, ERRATUM(2684597) 156 157check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2) 158 159/* 160 * ERRATA_DSU_2313941 : 161 * The errata is defined in dsu_helpers.S but applies to cortex_a510 162 * as well. Henceforth creating symbolic names to the already existing errata 163 * workaround functions to get them registered under the Errata Framework. 164 */ 165.equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941 166.equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa 167add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 168 169 /* ---------------------------------------------------- 170 * HW will do the cache maintenance while powering down 171 * ---------------------------------------------------- 172 */ 173func cortex_a510_core_pwr_dwn 174 /* --------------------------------------------------- 175 * Enable CPU power down bit in power control register 176 * --------------------------------------------------- 177 */ 178 sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 179 isb 180 ret 181endfunc cortex_a510_core_pwr_dwn 182 183errata_report_shim cortex_a510 184 185cpu_reset_func_start cortex_a510 186 /* Disable speculative loads */ 187 msr SSBS, xzr 188cpu_reset_func_end cortex_a510 189 190 /* --------------------------------------------- 191 * This function provides Cortex-A510 specific 192 * register information for crash reporting. 193 * It needs to return with x6 pointing to 194 * a list of register names in ascii and 195 * x8 - x15 having values of registers to be 196 * reported. 197 * --------------------------------------------- 198 */ 199.section .rodata.cortex_a510_regs, "aS" 200cortex_a510_regs: /* The ascii list of register names to be reported */ 201 .asciz "cpuectlr_el1", "" 202 203func cortex_a510_cpu_reg_dump 204 adr x6, cortex_a510_regs 205 mrs x8, CORTEX_A510_CPUECTLR_EL1 206 ret 207endfunc cortex_a510_cpu_reg_dump 208 209declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ 210 cortex_a510_reset_func, \ 211 cortex_a510_core_pwr_dwn 212