1/* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <drivers/arm/gicv3.h> 12 13#include <platform_def.h> 14 15 .globl plat_secondary_cold_boot_setup 16 .globl plat_is_my_cpu_primary 17 .globl platform_mem_init 18 .globl plat_my_core_pos 19 .globl plat_crash_console_init 20 .globl plat_crash_console_putc 21 .globl plat_crash_console_flush 22 23 /* ----------------------------------------------------- 24 * void plat_secondary_cold_boot_setup (void); 25 * 26 * This function performs any platform specific actions 27 * needed for a secondary cpu after a cold reset e.g 28 * mark the cpu's presence, mechanism to place it in a 29 * holding pen etc. 30 * TODO: Should we read the PSYS register to make sure 31 * that the request has gone through. 32 * ----------------------------------------------------- 33 */ 34func plat_secondary_cold_boot_setup 35 mrs x0, mpidr_el1 36 37 /* 38 * There is no sane reason to come out of this wfi. This 39 * cpu will be powered on and reset by the cpu_on pm api 40 */ 41 dsb sy 42 bl plat_panic_handler 43endfunc plat_secondary_cold_boot_setup 44 45func plat_is_my_cpu_primary 46 mov x9, x30 47 bl plat_my_core_pos 48 cmp x0, #VERSAL_NET_PRIMARY_CPU 49 cset x0, eq 50 ret x9 51endfunc plat_is_my_cpu_primary 52 53 /* ----------------------------------------------------- 54 * unsigned int plat_my_core_pos(void) 55 * This function uses the plat_core_pos_by_mpidr() 56 * definition to get the index of the calling CPU. 57 * ----------------------------------------------------- 58 */ 59func plat_my_core_pos 60 mrs x0, mpidr_el1 61 b plat_core_pos_by_mpidr 62endfunc plat_my_core_pos 63 64 /* --------------------------------------------------------------------- 65 * We don't need to carry out any memory initialization on Versal NET 66 * platform. The Secure RAM is accessible straight away. 67 * --------------------------------------------------------------------- 68 */ 69func platform_mem_init 70 ret 71endfunc platform_mem_init 72 73 74 /* --------------------------------------------- 75 * int plat_crash_console_init(void) 76 * Function to initialize the crash console 77 * without a C Runtime to print crash report. 78 * Clobber list : x0, x1, x2 79 * --------------------------------------------- 80 */ 81func plat_crash_console_init 82/* mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE 83 mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ 84 mov_imm x2, VERSAL_NET_CONSOLE_BAUDRATE 85 b console_pl011_core_init */ 86endfunc plat_crash_console_init 87 88 /* --------------------------------------------- 89 * int plat_crash_console_putc(int c) 90 * Function to print a character on the crash 91 * console without a C Runtime. 92 * Clobber list : x1, x2 93 * --------------------------------------------- 94 */ 95func plat_crash_console_putc 96 mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_BASE 97 b console_pl011_core_putc 98endfunc plat_crash_console_putc 99 100 /* --------------------------------------------- 101 * void plat_crash_console_flush() 102 * Function to force a write of all buffered 103 * data that hasn't been output. 104 * Out : void. 105 * Clobber list : x0, x1 106 * --------------------------------------------- 107 */ 108func plat_crash_console_flush 109 mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE 110 b console_pl011_core_flush 111endfunc plat_crash_console_flush 112