1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_EL2_H 8 #define CONTEXT_EL2_H 9 10 #ifndef __ASSEMBLER__ 11 /******************************************************************************* 12 * EL2 Registers: 13 * AArch64 EL2 system register context structure for preserving the 14 * architectural state during world switches. 15 ******************************************************************************/ 16 #if CTX_INCLUDE_EL2_REGS 17 typedef struct el2_common_regs { 18 uint64_t actlr_el2; 19 uint64_t afsr0_el2; 20 uint64_t afsr1_el2; 21 uint64_t amair_el2; 22 uint64_t cnthctl_el2; 23 uint64_t cntvoff_el2; 24 uint64_t cptr_el2; 25 uint64_t dbgvcr32_el2; 26 uint64_t elr_el2; 27 uint64_t esr_el2; 28 uint64_t far_el2; 29 uint64_t hacr_el2; 30 uint64_t hcr_el2; 31 uint64_t hpfar_el2; 32 uint64_t hstr_el2; 33 uint64_t icc_sre_el2; 34 uint64_t ich_hcr_el2; 35 uint64_t ich_vmcr_el2; 36 uint64_t mair_el2; 37 uint64_t mdcr_el2; 38 uint64_t pmscr_el2; 39 uint64_t sctlr_el2; 40 uint64_t spsr_el2; 41 uint64_t sp_el2; 42 uint64_t tcr_el2; 43 uint64_t tpidr_el2; 44 uint64_t ttbr0_el2; 45 uint64_t vbar_el2; 46 uint64_t vmpidr_el2; 47 uint64_t vpidr_el2; 48 uint64_t vtcr_el2; 49 uint64_t vttbr_el2; 50 } el2_common_regs_t; 51 52 typedef struct el2_mte2_regs { 53 uint64_t tfsr_el2; 54 } el2_mte2_regs_t; 55 56 typedef struct el2_fgt_regs { 57 uint64_t hdfgrtr_el2; 58 uint64_t hafgrtr_el2; 59 uint64_t hdfgwtr_el2; 60 uint64_t hfgitr_el2; 61 uint64_t hfgrtr_el2; 62 uint64_t hfgwtr_el2; 63 } el2_fgt_regs_t; 64 65 typedef struct el2_fgt2_regs { 66 uint64_t hdfgrtr2_el2; 67 uint64_t hdfgwtr2_el2; 68 uint64_t hfgitr2_el2; 69 uint64_t hfgrtr2_el2; 70 uint64_t hfgwtr2_el2; 71 } el2_fgt2_regs_t; 72 73 typedef struct el2_ecv_regs { 74 uint64_t cntpoff_el2; 75 } el2_ecv_regs_t; 76 77 typedef struct el2_vhe_regs { 78 uint64_t contextidr_el2; 79 uint64_t ttbr1_el2; 80 } el2_vhe_regs_t; 81 82 typedef struct el2_ras_regs { 83 uint64_t vdisr_el2; 84 uint64_t vsesr_el2; 85 } el2_ras_regs_t; 86 87 typedef struct el2_neve_regs { 88 uint64_t vncr_el2; 89 } el2_neve_regs_t; 90 91 typedef struct el2_trf_regs { 92 uint64_t trfcr_el2; 93 } el2_trf_regs_t; 94 95 typedef struct el2_csv2_regs { 96 uint64_t scxtnum_el2; 97 } el2_csv2_regs_t; 98 99 typedef struct el2_hcx_regs { 100 uint64_t hcrx_el2; 101 } el2_hcx_regs_t; 102 103 typedef struct el2_tcr2_regs { 104 uint64_t tcr2_el2; 105 } el2_tcr2_regs_t; 106 107 typedef struct el2_sxpoe_regs { 108 uint64_t por_el2; 109 } el2_sxpoe_regs_t; 110 111 typedef struct el2_sxpie_regs { 112 uint64_t pire0_el2; 113 uint64_t pir_el2; 114 } el2_sxpie_regs_t; 115 116 typedef struct el2_s2pie_regs { 117 uint64_t s2pir_el2; 118 } el2_s2pie_regs_t; 119 120 typedef struct el2_gcs_regs { 121 uint64_t gcscr_el2; 122 uint64_t gcspr_el2; 123 } el2_gcs_regs_t; 124 125 typedef struct el2_mpam_regs { 126 uint64_t mpam2_el2; 127 uint64_t mpamhcr_el2; 128 uint64_t mpamvpm0_el2; 129 uint64_t mpamvpm1_el2; 130 uint64_t mpamvpm2_el2; 131 uint64_t mpamvpm3_el2; 132 uint64_t mpamvpm4_el2; 133 uint64_t mpamvpm5_el2; 134 uint64_t mpamvpm6_el2; 135 uint64_t mpamvpm7_el2; 136 uint64_t mpamvpmv_el2; 137 } el2_mpam_regs_t; 138 139 typedef struct el2_sysregs { 140 141 el2_common_regs_t common; 142 143 #if ENABLE_FEAT_MTE2 144 el2_mte2_regs_t mte2; 145 #endif 146 147 #if ENABLE_FEAT_FGT 148 el2_fgt_regs_t fgt; 149 #endif 150 151 #if ENABLE_FEAT_FGT2 152 el2_fgt2_regs_t fgt2; 153 #endif 154 155 #if ENABLE_FEAT_ECV 156 el2_ecv_regs_t ecv; 157 #endif 158 159 #if ENABLE_FEAT_VHE 160 el2_vhe_regs_t vhe; 161 #endif 162 163 #if ENABLE_FEAT_RAS 164 el2_ras_regs_t ras; 165 #endif 166 167 #if CTX_INCLUDE_NEVE_REGS 168 el2_neve_regs_t neve; 169 #endif 170 171 #if ENABLE_TRF_FOR_NS 172 el2_trf_regs_t trf; 173 #endif 174 175 #if ENABLE_FEAT_CSV2_2 176 el2_csv2_regs_t csv2; 177 #endif 178 179 #if ENABLE_FEAT_HCX 180 el2_hcx_regs_t hcx; 181 #endif 182 183 #if ENABLE_FEAT_TCR2 184 el2_tcr2_regs_t tcr2; 185 #endif 186 187 #if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) 188 el2_sxpoe_regs_t sxpoe; 189 #endif 190 191 #if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) 192 el2_sxpie_regs_t sxpie; 193 #endif 194 195 #if ENABLE_FEAT_S2PIE 196 el2_s2pie_regs_t s2pie; 197 #endif 198 199 #if ENABLE_FEAT_GCS 200 el2_gcs_regs_t gcs; 201 #endif 202 203 #if CTX_INCLUDE_MPAM_REGS 204 el2_mpam_regs_t mpam; 205 #endif 206 207 } el2_sysregs_t; 208 209 /* 210 * Macros to access members related to individual features of the el2_sysregs_t 211 * structures. 212 */ 213 #define read_el2_ctx_common(ctx, reg) (((ctx)->common).reg) 214 215 #define write_el2_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ 216 = (uint64_t) (val)) 217 218 #if ENABLE_FEAT_MTE2 219 #define read_el2_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) 220 #define write_el2_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ 221 = (uint64_t) (val)) 222 #else 223 #define read_el2_ctx_mte2(ctx, reg) ULL(0) 224 #define write_el2_ctx_mte2(ctx, reg, val) 225 #endif /* ENABLE_FEAT_MTE2 */ 226 227 #if ENABLE_FEAT_FGT 228 #define read_el2_ctx_fgt(ctx, reg) (((ctx)->fgt).reg) 229 #define write_el2_ctx_fgt(ctx, reg, val) ((((ctx)->fgt).reg) \ 230 = (uint64_t) (val)) 231 #else 232 #define read_el2_ctx_fgt(ctx, reg) ULL(0) 233 #define write_el2_ctx_fgt(ctx, reg, val) 234 #endif /* ENABLE_FEAT_FGT */ 235 236 #if ENABLE_FEAT_FGT2 237 #define read_el2_ctx_fgt2(ctx, reg) (((ctx)->fgt2).reg) 238 #define write_el2_ctx_fgt2(ctx, reg, val) ((((ctx)->fgt2).reg) \ 239 = (uint64_t) (val)) 240 #else 241 #define read_el2_ctx_fgt2(ctx, reg) ULL(0) 242 #define write_el2_ctx_fgt2(ctx, reg, val) 243 #endif /* ENABLE_FEAT_FGT */ 244 245 #if ENABLE_FEAT_ECV 246 #define read_el2_ctx_ecv(ctx, reg) (((ctx)->ecv).reg) 247 #define write_el2_ctx_ecv(ctx, reg, val) ((((ctx)->ecv).reg) \ 248 = (uint64_t) (val)) 249 #else 250 #define read_el2_ctx_ecv(ctx, reg) ULL(0) 251 #define write_el2_ctx_ecv(ctx, reg, val) 252 #endif /* ENABLE_FEAT_ECV */ 253 254 #if ENABLE_FEAT_VHE 255 #define read_el2_ctx_vhe(ctx, reg) (((ctx)->vhe).reg) 256 #define write_el2_ctx_vhe(ctx, reg, val) ((((ctx)->vhe).reg) \ 257 = (uint64_t) (val)) 258 #else 259 #define read_el2_ctx_vhe(ctx, reg) ULL(0) 260 #define write_el2_ctx_vhe(ctx, reg, val) 261 #endif /* ENABLE_FEAT_VHE */ 262 263 #if ENABLE_FEAT_RAS 264 #define read_el2_ctx_ras(ctx, reg) (((ctx)->ras).reg) 265 #define write_el2_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ 266 = (uint64_t) (val)) 267 #else 268 #define read_el2_ctx_ras(ctx, reg) ULL(0) 269 #define write_el2_ctx_ras(ctx, reg, val) 270 #endif /* ENABLE_FEAT_RAS */ 271 272 #if CTX_INCLUDE_NEVE_REGS 273 #define read_el2_ctx_neve(ctx, reg) (((ctx)->neve).reg) 274 #define write_el2_ctx_neve(ctx, reg, val) ((((ctx)->neve).reg) \ 275 = (uint64_t) (val)) 276 #else 277 #define read_el2_ctx_neve(ctx, reg) ULL(0) 278 #define write_el2_ctx_neve(ctx, reg, val) 279 #endif /* CTX_INCLUDE_NEVE_REGS */ 280 281 #if ENABLE_TRF_FOR_NS 282 #define read_el2_ctx_trf(ctx, reg) (((ctx)->trf).reg) 283 #define write_el2_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ 284 = (uint64_t) (val)) 285 #else 286 #define read_el2_ctx_trf(ctx, reg) ULL(0) 287 #define write_el2_ctx_trf(ctx, reg, val) 288 #endif /* ENABLE_TRF_FOR_NS */ 289 290 #if ENABLE_FEAT_CSV2_2 291 #define read_el2_ctx_csv2_2(ctx, reg) (((ctx)->csv2).reg) 292 #define write_el2_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2).reg) \ 293 = (uint64_t) (val)) 294 #else 295 #define read_el2_ctx_csv2_2(ctx, reg) ULL(0) 296 #define write_el2_ctx_csv2_2(ctx, reg, val) 297 #endif /* ENABLE_FEAT_CSV2_2 */ 298 299 #if ENABLE_FEAT_HCX 300 #define read_el2_ctx_hcx(ctx, reg) (((ctx)->hcx).reg) 301 #define write_el2_ctx_hcx(ctx, reg, val) ((((ctx)->hcx).reg) \ 302 = (uint64_t) (val)) 303 #else 304 #define read_el2_ctx_hcx(ctx, reg) ULL(0) 305 #define write_el2_ctx_hcx(ctx, reg, val) 306 #endif /* ENABLE_FEAT_HCX */ 307 308 #if ENABLE_FEAT_TCR2 309 #define read_el2_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) 310 #define write_el2_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ 311 = (uint64_t) (val)) 312 #else 313 #define read_el2_ctx_tcr2(ctx, reg) ULL(0) 314 #define write_el2_ctx_tcr2(ctx, reg, val) 315 #endif /* ENABLE_FEAT_TCR2 */ 316 317 #if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) 318 #define read_el2_ctx_sxpoe(ctx, reg) (((ctx)->sxpoe).reg) 319 #define write_el2_ctx_sxpoe(ctx, reg, val) ((((ctx)->sxpoe).reg) \ 320 = (uint64_t) (val)) 321 #else 322 #define read_el2_ctx_sxpoe(ctx, reg) ULL(0) 323 #define write_el2_ctx_sxpoe(ctx, reg, val) 324 #endif /*(ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) */ 325 326 #if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) 327 #define read_el2_ctx_sxpie(ctx, reg) (((ctx)->sxpie).reg) 328 #define write_el2_ctx_sxpie(ctx, reg, val) ((((ctx)->sxpie).reg) \ 329 = (uint64_t) (val)) 330 #else 331 #define read_el2_ctx_sxpie(ctx, reg) ULL(0) 332 #define write_el2_ctx_sxpie(ctx, reg, val) 333 #endif /*(ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) */ 334 335 #if ENABLE_FEAT_S2PIE 336 #define read_el2_ctx_s2pie(ctx, reg) (((ctx)->s2pie).reg) 337 #define write_el2_ctx_s2pie(ctx, reg, val) ((((ctx)->s2pie).reg) \ 338 = (uint64_t) (val)) 339 #else 340 #define read_el2_ctx_s2pie(ctx, reg) ULL(0) 341 #define write_el2_ctx_s2pie(ctx, reg, val) 342 #endif /* ENABLE_FEAT_S2PIE */ 343 344 #if ENABLE_FEAT_GCS 345 #define read_el2_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) 346 #define write_el2_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ 347 = (uint64_t) (val)) 348 #else 349 #define read_el2_ctx_gcs(ctx, reg) ULL(0) 350 #define write_el2_ctx_gcs(ctx, reg, val) 351 #endif /* ENABLE_FEAT_GCS */ 352 353 #if CTX_INCLUDE_MPAM_REGS 354 #define read_el2_ctx_mpam(ctx, reg) (((ctx)->mpam).reg) 355 #define write_el2_ctx_mpam(ctx, reg, val) ((((ctx)->mpam).reg) \ 356 = (uint64_t) (val)) 357 #else 358 #define read_el2_ctx_mpam(ctx, reg) ULL(0) 359 #define write_el2_ctx_mpam(ctx, reg, val) 360 #endif /* CTX_INCLUDE_MPAM_REGS */ 361 362 #endif /* CTX_INCLUDE_EL2_REGS */ 363 /******************************************************************************/ 364 365 #endif /* __ASSEMBLER__ */ 366 367 #endif /* CONTEXT_EL2_H */ 368