1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <lib/mmio.h> 13 #include <tools_share/uuid.h> 14 15 #include "socfpga_fcs.h" 16 #include "socfpga_mailbox.h" 17 #include "socfpga_plat_def.h" 18 #include "socfpga_reset_manager.h" 19 #include "socfpga_sip_svc.h" 20 #include "socfpga_system_manager.h" 21 22 /* Total buffer the driver can hold */ 23 #define FPGA_CONFIG_BUFFER_SIZE 4 24 25 static config_type request_type = NO_REQUEST; 26 static int current_block, current_buffer; 27 static int read_block, max_blocks; 28 static uint32_t send_id, rcv_id; 29 static uint32_t bytes_per_block, blocks_submitted; 30 static bool bridge_disable; 31 32 /* RSU static variables */ 33 static uint32_t rsu_dcmf_ver[4] = {0}; 34 static uint16_t rsu_dcmf_stat[4] = {0}; 35 static uint32_t rsu_max_retry; 36 37 /* SiP Service UUID */ 38 DEFINE_SVC_UUID2(intl_svc_uid, 39 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 40 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 41 42 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 43 uint64_t x1, 44 uint64_t x2, 45 uint64_t x3, 46 uint64_t x4, 47 void *cookie, 48 void *handle, 49 uint64_t flags) 50 { 51 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 52 SMC_RET1(handle, SMC_UNK); 53 } 54 55 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 56 57 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 58 { 59 uint32_t args[3]; 60 61 while (max_blocks > 0 && buffer->size > buffer->size_written) { 62 args[0] = (1<<8); 63 args[1] = buffer->addr + buffer->size_written; 64 if (buffer->size - buffer->size_written <= bytes_per_block) { 65 args[2] = buffer->size - buffer->size_written; 66 current_buffer++; 67 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 68 } else { 69 args[2] = bytes_per_block; 70 } 71 72 buffer->size_written += args[2]; 73 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 74 3U, CMD_INDIRECT); 75 76 buffer->subblocks_sent++; 77 max_blocks--; 78 } 79 80 return !max_blocks; 81 } 82 83 static int intel_fpga_sdm_write_all(void) 84 { 85 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 86 if (intel_fpga_sdm_write_buffer( 87 &fpga_config_buffers[current_buffer])) { 88 break; 89 } 90 } 91 return 0; 92 } 93 94 static uint32_t intel_mailbox_fpga_config_isdone(void) 95 { 96 uint32_t ret; 97 98 switch (request_type) { 99 case RECONFIGURATION: 100 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 101 true); 102 break; 103 case BITSTREAM_AUTH: 104 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 105 false); 106 break; 107 default: 108 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 109 false); 110 break; 111 } 112 113 if (ret != 0U) { 114 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 115 return INTEL_SIP_SMC_STATUS_BUSY; 116 } else { 117 request_type = NO_REQUEST; 118 return INTEL_SIP_SMC_STATUS_ERROR; 119 } 120 } 121 122 if (bridge_disable != 0U) { 123 socfpga_bridges_enable(~0); /* Enable bridge */ 124 bridge_disable = false; 125 } 126 request_type = NO_REQUEST; 127 128 return INTEL_SIP_SMC_STATUS_OK; 129 } 130 131 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 132 { 133 int i; 134 135 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 136 if (fpga_config_buffers[i].block_number == current_block) { 137 fpga_config_buffers[i].subblocks_sent--; 138 if (fpga_config_buffers[i].subblocks_sent == 0 139 && fpga_config_buffers[i].size <= 140 fpga_config_buffers[i].size_written) { 141 fpga_config_buffers[i].write_requested = 0; 142 current_block++; 143 *buffer_addr_completed = 144 fpga_config_buffers[i].addr; 145 return 0; 146 } 147 } 148 } 149 150 return -1; 151 } 152 153 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 154 uint32_t *count, uint32_t *job_id) 155 { 156 uint32_t resp[5]; 157 unsigned int resp_len = ARRAY_SIZE(resp); 158 int status = INTEL_SIP_SMC_STATUS_OK; 159 int all_completed = 1; 160 *count = 0; 161 162 while (*count < 3) { 163 164 status = mailbox_read_response(job_id, 165 resp, &resp_len); 166 167 if (status < 0) { 168 break; 169 } 170 171 max_blocks++; 172 173 if (mark_last_buffer_xfer_completed( 174 &completed_addr[*count]) == 0) { 175 *count = *count + 1; 176 } else { 177 break; 178 } 179 } 180 181 if (*count <= 0) { 182 if (status != MBOX_NO_RESPONSE && 183 status != MBOX_TIMEOUT && resp_len != 0) { 184 mailbox_clear_response(); 185 request_type = NO_REQUEST; 186 return INTEL_SIP_SMC_STATUS_ERROR; 187 } 188 189 *count = 0; 190 } 191 192 intel_fpga_sdm_write_all(); 193 194 if (*count > 0) { 195 status = INTEL_SIP_SMC_STATUS_OK; 196 } else if (*count == 0) { 197 status = INTEL_SIP_SMC_STATUS_BUSY; 198 } 199 200 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 201 if (fpga_config_buffers[i].write_requested != 0) { 202 all_completed = 0; 203 break; 204 } 205 } 206 207 if (all_completed == 1) { 208 return INTEL_SIP_SMC_STATUS_OK; 209 } 210 211 return status; 212 } 213 214 static int intel_fpga_config_start(uint32_t flag) 215 { 216 uint32_t argument = 0x1; 217 uint32_t response[3]; 218 int status = 0; 219 unsigned int size = 0; 220 unsigned int resp_len = ARRAY_SIZE(response); 221 222 request_type = RECONFIGURATION; 223 224 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 225 bridge_disable = true; 226 } 227 228 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 229 size = 1; 230 bridge_disable = false; 231 request_type = BITSTREAM_AUTH; 232 } 233 234 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 235 intel_smmu_hps_remapper_init(0U); 236 #endif 237 238 mailbox_clear_response(); 239 240 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 241 CMD_CASUAL, NULL, NULL); 242 243 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 244 CMD_CASUAL, response, &resp_len); 245 246 if (status < 0) { 247 bridge_disable = false; 248 request_type = NO_REQUEST; 249 return INTEL_SIP_SMC_STATUS_ERROR; 250 } 251 252 max_blocks = response[0]; 253 bytes_per_block = response[1]; 254 255 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 256 fpga_config_buffers[i].size = 0; 257 fpga_config_buffers[i].size_written = 0; 258 fpga_config_buffers[i].addr = 0; 259 fpga_config_buffers[i].write_requested = 0; 260 fpga_config_buffers[i].block_number = 0; 261 fpga_config_buffers[i].subblocks_sent = 0; 262 } 263 264 blocks_submitted = 0; 265 current_block = 0; 266 read_block = 0; 267 current_buffer = 0; 268 269 /* Disable bridge on full reconfiguration */ 270 if (bridge_disable) { 271 socfpga_bridges_disable(~0); 272 } 273 274 return INTEL_SIP_SMC_STATUS_OK; 275 } 276 277 static bool is_fpga_config_buffer_full(void) 278 { 279 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 280 if (!fpga_config_buffers[i].write_requested) { 281 return false; 282 } 283 } 284 return true; 285 } 286 287 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 288 { 289 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 290 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 291 292 if (!addr && !size) { 293 return true; 294 } 295 if (size > (UINT64_MAX - addr)) { 296 return false; 297 } 298 if (addr < BL31_LIMIT) { 299 return false; 300 } 301 if (dram_region_end > dram_max_sz) { 302 return false; 303 } 304 305 return true; 306 } 307 308 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 309 { 310 int i; 311 312 intel_fpga_sdm_write_all(); 313 314 if (!is_address_in_ddr_range(mem, size) || 315 is_fpga_config_buffer_full()) { 316 return INTEL_SIP_SMC_STATUS_REJECTED; 317 } 318 319 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 320 intel_smmu_hps_remapper_init(&mem); 321 #endif 322 323 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 324 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 325 326 if (!fpga_config_buffers[j].write_requested) { 327 fpga_config_buffers[j].addr = mem; 328 fpga_config_buffers[j].size = size; 329 fpga_config_buffers[j].size_written = 0; 330 fpga_config_buffers[j].write_requested = 1; 331 fpga_config_buffers[j].block_number = 332 blocks_submitted++; 333 fpga_config_buffers[j].subblocks_sent = 0; 334 break; 335 } 336 } 337 338 if (is_fpga_config_buffer_full()) { 339 return INTEL_SIP_SMC_STATUS_BUSY; 340 } 341 342 return INTEL_SIP_SMC_STATUS_OK; 343 } 344 345 static int is_out_of_sec_range(uint64_t reg_addr) 346 { 347 #if DEBUG 348 return 0; 349 #endif 350 351 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 352 switch (reg_addr) { 353 case(0xF8011100): /* ECCCTRL1 */ 354 case(0xF8011104): /* ECCCTRL2 */ 355 case(0xF8011110): /* ERRINTEN */ 356 case(0xF8011114): /* ERRINTENS */ 357 case(0xF8011118): /* ERRINTENR */ 358 case(0xF801111C): /* INTMODE */ 359 case(0xF8011120): /* INTSTAT */ 360 case(0xF8011124): /* DIAGINTTEST */ 361 case(0xF801112C): /* DERRADDRA */ 362 case(0xFA000000): /* SMMU SCR0 */ 363 case(0xFA000004): /* SMMU SCR1 */ 364 case(0xFA000400): /* SMMU NSCR0 */ 365 case(0xFA004000): /* SMMU SSD0_REG */ 366 case(0xFA000820): /* SMMU SMR8 */ 367 case(0xFA000c20): /* SMMU SCR8 */ 368 case(0xFA028000): /* SMMU CB8_SCTRL */ 369 case(0xFA001020): /* SMMU CBAR8 */ 370 case(0xFA028030): /* SMMU TCR_LPAE */ 371 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 372 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 373 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 374 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 375 case(0xFA028010): /* SMMU_CB8)TCR2 */ 376 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 377 case(0xFA001820): /* SMMU_CBA2R8 */ 378 case(0xFA000074): /* SMMU_STLBGSTATUS */ 379 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 380 case(0xFA000060): /* SMMU_STLBIALL */ 381 case(0xFA000070): /* SMMU_STLBGSYNC */ 382 case(0xFA028618): /* CB8_TLBALL */ 383 case(0xFA0287F0): /* CB8_TLBSYNC */ 384 case(0xFFD12028): /* SDMMCGRP_CTRL */ 385 case(0xFFD12044): /* EMAC0 */ 386 case(0xFFD12048): /* EMAC1 */ 387 case(0xFFD1204C): /* EMAC2 */ 388 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 389 case(0xFFD12094): /* ECC_INT_MASK_SET */ 390 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 391 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 392 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 393 case(0xFFD120C0): /* NOC_TIMEOUT */ 394 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 395 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 396 case(0xFFD120D0): /* NOC_IDLEACK */ 397 case(0xFFD120D4): /* NOC_IDLESTATUS */ 398 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 399 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 400 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 401 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 402 return 0; 403 #else 404 switch (reg_addr) { 405 406 case(0xF8011104): /* ECCCTRL2 */ 407 case(0xFFD12028): /* SDMMCGRP_CTRL */ 408 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 409 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 410 case(0xFFD120D0): /* NOC_IDLEACK */ 411 412 413 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 414 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 415 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 416 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 417 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 418 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 419 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 420 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 421 422 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 423 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 424 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 425 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 426 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 427 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 428 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 429 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 430 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 431 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 432 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 433 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 434 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 435 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 436 #endif 437 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 438 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 439 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 440 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 441 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 442 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 443 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 444 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 445 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 446 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 447 return 0; 448 449 default: 450 break; 451 } 452 453 return -1; 454 } 455 456 /* Secure register access */ 457 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 458 { 459 if (is_out_of_sec_range(reg_addr)) { 460 return INTEL_SIP_SMC_STATUS_ERROR; 461 } 462 463 *retval = mmio_read_32(reg_addr); 464 465 return INTEL_SIP_SMC_STATUS_OK; 466 } 467 468 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 469 uint32_t *retval) 470 { 471 if (is_out_of_sec_range(reg_addr)) { 472 return INTEL_SIP_SMC_STATUS_ERROR; 473 } 474 475 switch (reg_addr) { 476 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 477 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 478 mmio_write_16(reg_addr, val); 479 break; 480 default: 481 mmio_write_32(reg_addr, val); 482 break; 483 } 484 485 return intel_secure_reg_read(reg_addr, retval); 486 } 487 488 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 489 uint32_t val, uint32_t *retval) 490 { 491 if (!intel_secure_reg_read(reg_addr, retval)) { 492 *retval &= ~mask; 493 *retval |= val & mask; 494 return intel_secure_reg_write(reg_addr, *retval, retval); 495 } 496 497 return INTEL_SIP_SMC_STATUS_ERROR; 498 } 499 500 /* Intel Remote System Update (RSU) services */ 501 uint64_t intel_rsu_update_address; 502 503 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 504 { 505 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 506 return INTEL_SIP_SMC_RSU_ERROR; 507 } 508 509 return INTEL_SIP_SMC_STATUS_OK; 510 } 511 512 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 513 unsigned int respbuf_sz) 514 { 515 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 516 return INTEL_SIP_SMC_RSU_ERROR; 517 } 518 519 return INTEL_SIP_SMC_STATUS_OK; 520 } 521 522 uint32_t intel_rsu_update(uint64_t update_address) 523 { 524 if (update_address > SIZE_MAX) { 525 return INTEL_SIP_SMC_STATUS_REJECTED; 526 } 527 528 intel_rsu_update_address = update_address; 529 return INTEL_SIP_SMC_STATUS_OK; 530 } 531 532 static uint32_t intel_rsu_notify(uint32_t execution_stage) 533 { 534 if (mailbox_hps_stage_notify(execution_stage) < 0) { 535 return INTEL_SIP_SMC_RSU_ERROR; 536 } 537 538 return INTEL_SIP_SMC_STATUS_OK; 539 } 540 541 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 542 uint32_t *ret_stat) 543 { 544 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 545 return INTEL_SIP_SMC_RSU_ERROR; 546 } 547 548 *ret_stat = respbuf[8]; 549 return INTEL_SIP_SMC_STATUS_OK; 550 } 551 552 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 553 uint64_t dcmf_ver_3_2) 554 { 555 rsu_dcmf_ver[0] = dcmf_ver_1_0; 556 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 557 rsu_dcmf_ver[2] = dcmf_ver_3_2; 558 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 559 560 return INTEL_SIP_SMC_STATUS_OK; 561 } 562 563 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 564 { 565 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 566 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 567 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 568 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 569 570 return INTEL_SIP_SMC_STATUS_OK; 571 } 572 573 /* Intel HWMON services */ 574 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 575 { 576 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 577 return INTEL_SIP_SMC_STATUS_ERROR; 578 } 579 580 return INTEL_SIP_SMC_STATUS_OK; 581 } 582 583 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 584 { 585 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 586 return INTEL_SIP_SMC_STATUS_ERROR; 587 } 588 589 return INTEL_SIP_SMC_STATUS_OK; 590 } 591 592 /* Mailbox services */ 593 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 594 { 595 int status; 596 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 597 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 598 599 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 600 CMD_CASUAL, resp_data, &resp_len); 601 602 if (status < 0) { 603 return INTEL_SIP_SMC_STATUS_ERROR; 604 } 605 606 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 607 return INTEL_SIP_SMC_STATUS_ERROR; 608 } 609 610 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 611 612 return INTEL_SIP_SMC_STATUS_OK; 613 } 614 615 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 616 unsigned int len, uint32_t urgent, uint64_t response, 617 unsigned int resp_len, int *mbox_status, 618 unsigned int *len_in_resp) 619 { 620 *len_in_resp = 0; 621 *mbox_status = GENERIC_RESPONSE_ERROR; 622 623 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 624 return INTEL_SIP_SMC_STATUS_REJECTED; 625 } 626 627 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 628 (uint32_t *) response, &resp_len); 629 630 if (status < 0) { 631 *mbox_status = -status; 632 return INTEL_SIP_SMC_STATUS_ERROR; 633 } 634 635 *mbox_status = 0; 636 *len_in_resp = resp_len; 637 638 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 639 640 return INTEL_SIP_SMC_STATUS_OK; 641 } 642 643 static int intel_smc_get_usercode(uint32_t *user_code) 644 { 645 int status; 646 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 647 648 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 649 0U, CMD_CASUAL, user_code, &resp_len); 650 651 if (status < 0) { 652 return INTEL_SIP_SMC_STATUS_ERROR; 653 } 654 655 return INTEL_SIP_SMC_STATUS_OK; 656 } 657 658 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 659 uint32_t mode, uint32_t *job_id, 660 uint32_t *ret_size, uint32_t *mbox_error) 661 { 662 int status = 0; 663 uint32_t resp_len = size / MBOX_WORD_BYTE; 664 665 if (resp_len > MBOX_DATA_MAX_LEN) { 666 return INTEL_SIP_SMC_STATUS_REJECTED; 667 } 668 669 if (!is_address_in_ddr_range(addr, size)) { 670 return INTEL_SIP_SMC_STATUS_REJECTED; 671 } 672 673 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 674 status = mailbox_read_response_async(job_id, 675 NULL, (uint32_t *) addr, &resp_len, 0); 676 } else { 677 status = mailbox_read_response(job_id, 678 (uint32_t *) addr, &resp_len); 679 680 if (status == MBOX_NO_RESPONSE) { 681 status = MBOX_BUSY; 682 } 683 } 684 685 if (status == MBOX_NO_RESPONSE) { 686 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 687 } 688 689 if (status == MBOX_BUSY) { 690 return INTEL_SIP_SMC_STATUS_BUSY; 691 } 692 693 *ret_size = resp_len * MBOX_WORD_BYTE; 694 flush_dcache_range(addr, *ret_size); 695 696 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 697 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 698 *mbox_error = -status; 699 } else if (status != MBOX_RET_OK) { 700 *mbox_error = -status; 701 return INTEL_SIP_SMC_STATUS_ERROR; 702 } 703 704 return INTEL_SIP_SMC_STATUS_OK; 705 } 706 707 /* Miscellaneous HPS services */ 708 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 709 { 710 int status = 0; 711 712 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 713 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 714 status = socfpga_bridges_enable((uint32_t)mask); 715 } else { 716 status = socfpga_bridges_enable(~0); 717 } 718 } else { 719 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 720 status = socfpga_bridges_disable((uint32_t)mask); 721 } else { 722 status = socfpga_bridges_disable(~0); 723 } 724 } 725 726 if (status < 0) { 727 return INTEL_SIP_SMC_STATUS_ERROR; 728 } 729 730 return INTEL_SIP_SMC_STATUS_OK; 731 } 732 733 /* SDM SEU Error services */ 734 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 735 { 736 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 737 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 738 } 739 740 return INTEL_SIP_SMC_STATUS_OK; 741 } 742 743 /* SDM SAFE SEU Error inject services */ 744 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 745 { 746 if (mailbox_safe_inject_seu_err(command, len) < 0) { 747 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 748 } 749 750 return INTEL_SIP_SMC_STATUS_OK; 751 } 752 753 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 754 /* SMMU HPS Remapper */ 755 void intel_smmu_hps_remapper_init(uint64_t *mem) 756 { 757 /* Read out Bit 1 value */ 758 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 759 760 if (remap == 0x00) { 761 /* Update DRAM Base address for SDM SMMU */ 762 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 763 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 764 *mem = *mem - DRAM_BASE; 765 } else { 766 *mem = *mem - DRAM_BASE; 767 } 768 } 769 #endif 770 771 /* 772 * This function is responsible for handling all SiP calls from the NS world 773 */ 774 775 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 776 u_register_t x1, 777 u_register_t x2, 778 u_register_t x3, 779 u_register_t x4, 780 void *cookie, 781 void *handle, 782 u_register_t flags) 783 { 784 uint32_t retval = 0, completed_addr[3]; 785 uint32_t retval2 = 0; 786 uint32_t mbox_error = 0; 787 uint64_t retval64, rsu_respbuf[9]; 788 uint32_t seu_respbuf[3]; 789 int status = INTEL_SIP_SMC_STATUS_OK; 790 int mbox_status; 791 unsigned int len_in_resp; 792 u_register_t x5, x6, x7; 793 794 switch (smc_fid) { 795 case SIP_SVC_UID: 796 /* Return UID to the caller */ 797 SMC_UUID_RET(handle, intl_svc_uid); 798 799 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 800 status = intel_mailbox_fpga_config_isdone(); 801 SMC_RET4(handle, status, 0, 0, 0); 802 803 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 804 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 805 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 806 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 807 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 808 809 case INTEL_SIP_SMC_FPGA_CONFIG_START: 810 status = intel_fpga_config_start(x1); 811 SMC_RET4(handle, status, 0, 0, 0); 812 813 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 814 status = intel_fpga_config_write(x1, x2); 815 SMC_RET4(handle, status, 0, 0, 0); 816 817 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 818 status = intel_fpga_config_completed_write(completed_addr, 819 &retval, &rcv_id); 820 switch (retval) { 821 case 1: 822 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 823 completed_addr[0], 0, 0); 824 825 case 2: 826 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 827 completed_addr[0], 828 completed_addr[1], 0); 829 830 case 3: 831 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 832 completed_addr[0], 833 completed_addr[1], 834 completed_addr[2]); 835 836 case 0: 837 SMC_RET4(handle, status, 0, 0, 0); 838 839 default: 840 mailbox_clear_response(); 841 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 842 } 843 844 case INTEL_SIP_SMC_REG_READ: 845 status = intel_secure_reg_read(x1, &retval); 846 SMC_RET3(handle, status, retval, x1); 847 848 case INTEL_SIP_SMC_REG_WRITE: 849 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 850 SMC_RET3(handle, status, retval, x1); 851 852 case INTEL_SIP_SMC_REG_UPDATE: 853 status = intel_secure_reg_update(x1, (uint32_t)x2, 854 (uint32_t)x3, &retval); 855 SMC_RET3(handle, status, retval, x1); 856 857 case INTEL_SIP_SMC_RSU_STATUS: 858 status = intel_rsu_status(rsu_respbuf, 859 ARRAY_SIZE(rsu_respbuf)); 860 if (status) { 861 SMC_RET1(handle, status); 862 } else { 863 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 864 rsu_respbuf[2], rsu_respbuf[3]); 865 } 866 867 case INTEL_SIP_SMC_RSU_UPDATE: 868 status = intel_rsu_update(x1); 869 SMC_RET1(handle, status); 870 871 case INTEL_SIP_SMC_RSU_NOTIFY: 872 status = intel_rsu_notify(x1); 873 SMC_RET1(handle, status); 874 875 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 876 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 877 ARRAY_SIZE(rsu_respbuf), &retval); 878 if (status) { 879 SMC_RET1(handle, status); 880 } else { 881 SMC_RET2(handle, status, retval); 882 } 883 884 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 885 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 886 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 887 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 888 889 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 890 status = intel_rsu_copy_dcmf_version(x1, x2); 891 SMC_RET1(handle, status); 892 893 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 894 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 895 ARRAY_SIZE(rsu_respbuf)); 896 if (status) { 897 SMC_RET1(handle, status); 898 } else { 899 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 900 rsu_respbuf[2], rsu_respbuf[3]); 901 } 902 903 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 904 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 905 ((uint64_t)rsu_dcmf_stat[3] << 48) | 906 ((uint64_t)rsu_dcmf_stat[2] << 32) | 907 ((uint64_t)rsu_dcmf_stat[1] << 16) | 908 rsu_dcmf_stat[0]); 909 910 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 911 status = intel_rsu_copy_dcmf_status(x1); 912 SMC_RET1(handle, status); 913 914 case INTEL_SIP_SMC_RSU_MAX_RETRY: 915 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 916 917 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 918 rsu_max_retry = x1; 919 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 920 921 case INTEL_SIP_SMC_ECC_DBE: 922 status = intel_ecc_dbe_notification(x1); 923 SMC_RET1(handle, status); 924 925 case INTEL_SIP_SMC_SERVICE_COMPLETED: 926 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 927 &len_in_resp, &mbox_error); 928 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 929 930 case INTEL_SIP_SMC_FIRMWARE_VERSION: 931 status = intel_smc_fw_version(&retval); 932 SMC_RET2(handle, status, retval); 933 934 case INTEL_SIP_SMC_MBOX_SEND_CMD: 935 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 936 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 937 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 938 &mbox_status, &len_in_resp); 939 SMC_RET3(handle, status, mbox_status, len_in_resp); 940 941 case INTEL_SIP_SMC_GET_USERCODE: 942 status = intel_smc_get_usercode(&retval); 943 SMC_RET2(handle, status, retval); 944 945 case INTEL_SIP_SMC_FCS_CRYPTION: 946 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 947 948 if (x1 == FCS_MODE_DECRYPT) { 949 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 950 } else if (x1 == FCS_MODE_ENCRYPT) { 951 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 952 } else { 953 status = INTEL_SIP_SMC_STATUS_REJECTED; 954 } 955 956 SMC_RET3(handle, status, x4, x5); 957 958 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 959 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 960 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 961 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 962 963 if (x3 == FCS_MODE_DECRYPT) { 964 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 965 (uint32_t *) &x7, &mbox_error); 966 } else if (x3 == FCS_MODE_ENCRYPT) { 967 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 968 (uint32_t *) &x7, &mbox_error); 969 } else { 970 status = INTEL_SIP_SMC_STATUS_REJECTED; 971 } 972 973 SMC_RET4(handle, status, mbox_error, x6, x7); 974 975 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 976 status = intel_fcs_random_number_gen(x1, &retval64, 977 &mbox_error); 978 SMC_RET4(handle, status, mbox_error, x1, retval64); 979 980 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 981 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 982 &send_id); 983 SMC_RET1(handle, status); 984 985 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 986 status = intel_fcs_send_cert(x1, x2, &send_id); 987 SMC_RET1(handle, status); 988 989 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 990 status = intel_fcs_get_provision_data(&send_id); 991 SMC_RET1(handle, status); 992 993 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 994 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 995 &mbox_error); 996 SMC_RET2(handle, status, mbox_error); 997 998 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 999 status = intel_hps_set_bridges(x1, x2); 1000 SMC_RET1(handle, status); 1001 1002 case INTEL_SIP_SMC_HWMON_READTEMP: 1003 status = intel_hwmon_readtemp(x1, &retval); 1004 SMC_RET2(handle, status, retval); 1005 1006 case INTEL_SIP_SMC_HWMON_READVOLT: 1007 status = intel_hwmon_readvolt(x1, &retval); 1008 SMC_RET2(handle, status, retval); 1009 1010 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 1011 status = intel_fcs_sigma_teardown(x1, &mbox_error); 1012 SMC_RET2(handle, status, mbox_error); 1013 1014 case INTEL_SIP_SMC_FCS_CHIP_ID: 1015 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 1016 SMC_RET4(handle, status, mbox_error, retval, retval2); 1017 1018 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 1019 status = intel_fcs_attestation_subkey(x1, x2, x3, 1020 (uint32_t *) &x4, &mbox_error); 1021 SMC_RET4(handle, status, mbox_error, x3, x4); 1022 1023 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 1024 status = intel_fcs_get_measurement(x1, x2, x3, 1025 (uint32_t *) &x4, &mbox_error); 1026 SMC_RET4(handle, status, mbox_error, x3, x4); 1027 1028 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 1029 status = intel_fcs_get_attestation_cert(x1, x2, 1030 (uint32_t *) &x3, &mbox_error); 1031 SMC_RET4(handle, status, mbox_error, x2, x3); 1032 1033 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 1034 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 1035 SMC_RET2(handle, status, mbox_error); 1036 1037 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 1038 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 1039 SMC_RET3(handle, status, mbox_error, retval); 1040 1041 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 1042 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 1043 SMC_RET2(handle, status, mbox_error); 1044 1045 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 1046 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 1047 SMC_RET1(handle, status); 1048 1049 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1050 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1051 (uint32_t *) &x4, &mbox_error); 1052 SMC_RET4(handle, status, mbox_error, x3, x4); 1053 1054 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1055 status = intel_fcs_remove_crypto_service_key(x1, x2, 1056 &mbox_error); 1057 SMC_RET2(handle, status, mbox_error); 1058 1059 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 1060 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 1061 (uint32_t *) &x4, &mbox_error); 1062 SMC_RET4(handle, status, mbox_error, x3, x4); 1063 1064 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 1065 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1066 status = intel_fcs_get_digest_init(x1, x2, x3, 1067 x4, x5, &mbox_error); 1068 SMC_RET2(handle, status, mbox_error); 1069 1070 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 1071 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1072 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1073 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1074 x4, x5, (uint32_t *) &x6, false, 1075 &mbox_error); 1076 SMC_RET4(handle, status, mbox_error, x5, x6); 1077 1078 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1079 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1080 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1081 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1082 x4, x5, (uint32_t *) &x6, true, 1083 &mbox_error); 1084 SMC_RET4(handle, status, mbox_error, x5, x6); 1085 1086 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1087 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1088 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1089 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1090 x4, x5, (uint32_t *) &x6, false, 1091 &mbox_error, &send_id); 1092 SMC_RET4(handle, status, mbox_error, x5, x6); 1093 1094 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1095 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1096 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1097 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1098 x4, x5, (uint32_t *) &x6, true, 1099 &mbox_error, &send_id); 1100 SMC_RET4(handle, status, mbox_error, x5, x6); 1101 1102 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1103 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1104 status = intel_fcs_mac_verify_init(x1, x2, x3, 1105 x4, x5, &mbox_error); 1106 SMC_RET2(handle, status, mbox_error); 1107 1108 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1109 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1110 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1111 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1112 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1113 x4, x5, (uint32_t *) &x6, x7, 1114 false, &mbox_error); 1115 SMC_RET4(handle, status, mbox_error, x5, x6); 1116 1117 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1118 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1119 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1120 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1121 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1122 x4, x5, (uint32_t *) &x6, x7, 1123 true, &mbox_error); 1124 SMC_RET4(handle, status, mbox_error, x5, x6); 1125 1126 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1127 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1128 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1129 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1130 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1131 x4, x5, (uint32_t *) &x6, x7, 1132 false, &mbox_error, &send_id); 1133 SMC_RET4(handle, status, mbox_error, x5, x6); 1134 1135 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1136 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1137 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1138 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1139 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1140 x4, x5, (uint32_t *) &x6, x7, 1141 true, &mbox_error, &send_id); 1142 SMC_RET4(handle, status, mbox_error, x5, x6); 1143 1144 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1145 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1146 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1147 x4, x5, &mbox_error); 1148 SMC_RET2(handle, status, mbox_error); 1149 1150 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1151 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1152 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1153 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1154 x3, x4, x5, (uint32_t *) &x6, false, 1155 &mbox_error); 1156 SMC_RET4(handle, status, mbox_error, x5, x6); 1157 1158 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1159 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1160 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1161 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1162 x3, x4, x5, (uint32_t *) &x6, true, 1163 &mbox_error); 1164 SMC_RET4(handle, status, mbox_error, x5, x6); 1165 1166 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1167 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1168 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1169 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1170 x2, x3, x4, x5, (uint32_t *) &x6, false, 1171 &mbox_error, &send_id); 1172 SMC_RET4(handle, status, mbox_error, x5, x6); 1173 1174 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1175 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1176 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1177 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1178 x2, x3, x4, x5, (uint32_t *) &x6, true, 1179 &mbox_error, &send_id); 1180 SMC_RET4(handle, status, mbox_error, x5, x6); 1181 1182 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1183 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1184 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1185 x4, x5, &mbox_error); 1186 SMC_RET2(handle, status, mbox_error); 1187 1188 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1189 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1190 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1191 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1192 x4, x5, (uint32_t *) &x6, &mbox_error); 1193 SMC_RET4(handle, status, mbox_error, x5, x6); 1194 1195 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1196 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1197 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1198 x4, x5, &mbox_error); 1199 SMC_RET2(handle, status, mbox_error); 1200 1201 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1202 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1203 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1204 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1205 x4, x5, (uint32_t *) &x6, &mbox_error); 1206 SMC_RET4(handle, status, mbox_error, x5, x6); 1207 1208 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1209 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1210 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1211 x4, x5, &mbox_error); 1212 SMC_RET2(handle, status, mbox_error); 1213 1214 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1215 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1216 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1217 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1218 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1219 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1220 x7, false, &mbox_error); 1221 SMC_RET4(handle, status, mbox_error, x5, x6); 1222 1223 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1224 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1225 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1226 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1227 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1228 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1229 x7, false, &mbox_error, &send_id); 1230 SMC_RET4(handle, status, mbox_error, x5, x6); 1231 1232 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1233 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1234 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1235 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1236 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1237 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1238 x7, true, &mbox_error, &send_id); 1239 SMC_RET4(handle, status, mbox_error, x5, x6); 1240 1241 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1242 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1243 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1244 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1245 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1246 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1247 x7, true, &mbox_error); 1248 SMC_RET4(handle, status, mbox_error, x5, x6); 1249 1250 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1251 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1252 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1253 x4, x5, &mbox_error); 1254 SMC_RET2(handle, status, mbox_error); 1255 1256 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1257 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1258 (uint32_t *) &x4, &mbox_error); 1259 SMC_RET4(handle, status, mbox_error, x3, x4); 1260 1261 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1262 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1263 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1264 x4, x5, &mbox_error); 1265 SMC_RET2(handle, status, mbox_error); 1266 1267 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1268 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1269 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1270 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1271 x4, x5, (uint32_t *) &x6, &mbox_error); 1272 SMC_RET4(handle, status, mbox_error, x5, x6); 1273 1274 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1275 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1276 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1277 &mbox_error); 1278 SMC_RET2(handle, status, mbox_error); 1279 1280 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1281 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1282 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1283 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1284 x5, x6, false, &send_id); 1285 SMC_RET1(handle, status); 1286 1287 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1288 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1289 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1290 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1291 x5, x6, true, &send_id); 1292 SMC_RET1(handle, status); 1293 1294 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1295 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1296 &mbox_error); 1297 SMC_RET4(handle, status, mbox_error, x1, retval64); 1298 1299 case INTEL_SIP_SMC_SVC_VERSION: 1300 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1301 SIP_SVC_VERSION_MAJOR, 1302 SIP_SVC_VERSION_MINOR); 1303 1304 case INTEL_SIP_SMC_SEU_ERR_STATUS: 1305 status = intel_sdm_seu_err_read(seu_respbuf, 1306 ARRAY_SIZE(seu_respbuf)); 1307 if (status) { 1308 SMC_RET1(handle, status); 1309 } else { 1310 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 1311 } 1312 1313 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 1314 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 1315 SMC_RET1(handle, status); 1316 1317 default: 1318 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1319 cookie, handle, flags); 1320 } 1321 } 1322 1323 uintptr_t sip_smc_handler(uint32_t smc_fid, 1324 u_register_t x1, 1325 u_register_t x2, 1326 u_register_t x3, 1327 u_register_t x4, 1328 void *cookie, 1329 void *handle, 1330 u_register_t flags) 1331 { 1332 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1333 1334 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1335 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1336 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1337 cookie, handle, flags); 1338 } else { 1339 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1340 cookie, handle, flags); 1341 } 1342 } 1343 1344 DECLARE_RT_SVC( 1345 socfpga_sip_svc, 1346 OEN_SIP_START, 1347 OEN_SIP_END, 1348 SMC_TYPE_FAST, 1349 NULL, 1350 sip_smc_handler 1351 ); 1352 1353 DECLARE_RT_SVC( 1354 socfpga_sip_svc_std, 1355 OEN_SIP_START, 1356 OEN_SIP_END, 1357 SMC_TYPE_YIELD, 1358 NULL, 1359 sip_smc_handler 1360 ); 1361