1 /* 2 * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DDRPHY_PHYINIT_STRUCT_H 8 #define DDRPHY_PHYINIT_STRUCT_H 9 10 /* This file defines the internal data structures used in PhyInit to store user configuration */ 11 12 /* DIMM Type definitions */ 13 #define DDR_DIMMTYPE_NODIMM 4U /* No DIMM (Soldered-on) */ 14 15 /* 16 * Structure for basic user inputs 17 * 18 * The following basic data structure must be set and completed correctly so 19 * that the PhyInit software package can accurate program PHY registers. 20 */ 21 struct user_input_basic { 22 uint32_t dramtype; /* 23 * DRAM module type. 24 * 25 * Value | Description 26 * ----- | ------ 27 * 0x0 | DDR4 28 * 0x1 | DDR3 29 * 0x2 | LPDDR4 30 */ 31 32 uint32_t dimmtype; /* 33 * DIMM type. 34 * 35 * Value | Description 36 * ----- | ------ 37 * 0x4 | No DIMM (Soldered-on) (DDR_DIMMTYPE_NODIMM) 38 */ 39 40 uint32_t lp4xmode; /* 41 * LPDDR4X mode support. 42 * Only used for LPDDR4, but not valid here. 43 * 44 * Value | Description 45 * ----- | ------ 46 * 0x0 | LPDDR4 mode, when dramtype is LPDDR4 47 */ 48 49 uint32_t numdbyte; /* Number of dbytes physically instantiated */ 50 51 uint32_t numactivedbytedfi0; /* Number of active dbytes to be controlled by dfi0 */ 52 53 uint32_t numactivedbytedfi1; /* 54 * Number of active dbytes to be controlled by dfi1. 55 * Only used for LPDDR4. 56 */ 57 58 uint32_t numanib; /* Number of ANIBs physically instantiated */ 59 60 uint32_t numrank_dfi0; /* Number of ranks in DFI0 channel */ 61 62 uint32_t numrank_dfi1; /* Number of ranks in DFI1 channel (if DFI1 exists) */ 63 64 uint32_t dramdatawidth; /* 65 * Width of the DRAM device. 66 * 67 * Enter 4,8,16 or 32 depending on protocol and dram type 68 * according below table. 69 * 70 * Protocol | Valid Options | Default 71 * -------- | ------------- | --- 72 * DDR3 | 4,8,16 | 8 73 * DDR4 | 4,8,16 | 8 74 * LPDDR4 | 8,16 | 16 75 * 76 * For mixed x8 and x16 width devices, set variable to x8. 77 */ 78 79 uint32_t numpstates; /* Number of p-states used. Must be set to 1 */ 80 81 uint32_t frequency; /* 82 * Memclk frequency for each PState. 83 * Memclk frequency in MHz round up to next highest integer. 84 * Enter 334 for 333.333, etc. 85 */ 86 87 uint32_t pllbypass; /* 88 * Indicates if PLL should be in Bypass mode. 89 * If DDR datarate < 333, PLL must be in Bypass Mode. 90 * 91 * Value | Description 92 * ----- | ------ 93 * 0x1 | Enabled 94 * 0x0 | Disabled 95 */ 96 97 uint32_t dfifreqratio; /* 98 * Selected Dfi Frequency ratio. 99 * Used to program the dfifreqratio register. This register 100 * controls how dfi_freq_ratio input pin should be driven 101 * inaccordance with DFI Spec. 102 * 103 * Binary Value | Description 104 * ----- | ------ 105 * 2'b01 | 1:2 DFI Frequency Ratio (default) 106 */ 107 108 uint32_t dfi1exists; /* Indicates if the PHY configuration has Dfi1 channel */ 109 110 uint32_t train2d; /* Obsolete. Not used. */ 111 112 uint32_t hardmacrover; /* 113 * Hard Macro Family version in use. 114 * 115 * Value | Description 116 * ----- | ------ 117 * 3 | hardmacro family D 118 */ 119 120 uint32_t readdbienable; /* Obsolete. Not Used. */ 121 122 uint32_t dfimode; /* Obsolete. Not Used. */ 123 }; 124 125 /* 126 * Structure for advanced user inputs 127 */ 128 struct user_input_advanced { 129 uint32_t lp4rxpreamblemode; /* 130 * Selects between DRAM read static vs toggle preamble. 131 * Determine desired DRAM Read Preamble Mode based on SI 132 * Analysis and DRAM Part in use. 133 * The PHY training firmware will program DRAM mr1-OP[3] 134 * after training based on setting. 135 * 136 * Value | Description 137 * ----- | ------ 138 * 0x1 | toggling preamble 139 * 0x0 | static preamble 140 */ 141 142 uint32_t lp4postambleext; /* 143 * Extend write postamble in LPDDR4. 144 * Only used for LPDDR4. 145 * This variable is used to calculate LPDDR4 mr3-OP[1] set 146 * in the messageBlock. 147 * The training firmware will set DRAM MR according to MR 148 * value in the messageBlock at the end of training. 149 * Set value according to your SI analysis and DRAM 150 * requirement. 151 * 152 * Value | Description 153 * ----- | ------ 154 * 0x0 | half Memclk postamble 155 * 0x1 | 1.5 Memclk postabmle (default) 156 */ 157 158 uint32_t d4rxpreamblelength; /* 159 * Length of read preamble in DDR4 mode. 160 * Only used for DDR4. 161 * This variable is used to calculate DDR4 mr4-OP[11] set 162 * in the messageBlock. 163 * The training firmware will set DRAM MR according to MR 164 * value in the messageBlock at the end of training. 165 * Set value according to your SI analysis and DRAM 166 * requirement. 167 * 168 * Value | Description 169 * ----- | ------ 170 * 0x0 | 1 Tck 171 * 0x1 | 2 Tck (default) 172 */ 173 174 uint32_t d4txpreamblelength; /* 175 * Length of write preamble in DDR4 mode. 176 * Only used for DDR4. 177 * This variable is used to calculate DDR4 mr4-OP[12] set 178 * in the messageBlock. 179 * The training firmware will set DRAM MR according to MR 180 * value in the messageBlock at the end of training. 181 * Set value according to your SI analysis and DRAM 182 * requirement. 183 * 184 * Value | Description 185 * ----- | ------ 186 * 0x0 | 1 Tck (default) 187 * 0x1 | 2 Tck 188 */ 189 190 uint32_t extcalresval; /* 191 * External Impedance calibration pull-down resistor value 192 * select. 193 * Indicates value of impedance calibration pull-down 194 * resistor connected to BP_ZN pin of the PHY. 195 * Value | Description 196 * ----- | ------ 197 * 0x0 | 240 ohm (default) 198 */ 199 200 uint32_t is2ttiming; /* 201 * Set to 1 to use 2T timing for address/command, otherwise 202 * 1T timing will be used. 203 * Determine 1T or 2T Timing operation mode based on SI 204 * Analysis and DRAM Timing. 205 * - In 1T mode, CK, CS, CA all have the same nominal 206 * timing, ie. ATxDly[6:0] will have same value for all 207 * ANIBs. 208 * - In 2T mode, CK, CS,have the same nominal timing 209 * (e.g. AtxDly[6:0]=0x00), while CA is delayed by 1UI 210 * (e.g. ATxDly[6:0]=0x40) 211 * Used to program phycfg setting in messageBlock. 212 * 213 * Value | Description 214 * ----- | ------ 215 * 0x0 | 1T Timing (default) 216 * 0x1 | 2T Timing 217 */ 218 219 uint32_t odtimpedance; /* 220 * ODT impedance in ohm. 221 * Used for programming TxOdtDrvStren registers. 222 * Enter 0 for open/high-impedance. 223 * Default value: 60 224 */ 225 226 uint32_t tximpedance; /* 227 * Tx Drive Impedance for DQ/DQS in ohm. 228 * Used for programming TxImpedanceCtrl1 registers. 229 * Enter 0 for open/high-impedance. 230 * Default value: 60 231 */ 232 233 uint32_t atximpedance; /* 234 * Tx Drive Impedance for AC in ohm. 235 * Used for programming ATxImpedance register. 236 * Enter 0 for open/high-impedance 237 * Default value: 20 (HMA,HMB,HMC,HMD), 40 (HME) 238 */ 239 240 uint32_t memalerten; /* 241 * Enables BP_ALERT programming of PHY registers. 242 * Only used for DDR3 and DDR4. 243 * Used for programming MemAlertControl and MemAlertControl2 244 * registers. 245 * Program if you require using BP_ALERT pin (to receive or 246 * terminate signal) of the PHY otherwise leave at default 247 * value to save power. 248 * 249 * Value | Description 250 * ----- | ------ 251 * 0x0 | Disable BP_ALERT (default) 252 */ 253 254 uint32_t memalertpuimp; /* 255 * Specify MemAlert Pull-up Termination Impedance. 256 * Programs the pull-up termination on BP_ALERT. 257 * Not valid here (fixed 0 value). 258 */ 259 260 uint32_t memalertvreflevel; /* 261 * Specify the Vref level for BP_ALERT(MemAlert) Receiver. 262 * Not valid here (fixed 0 value). 263 */ 264 265 uint32_t memalertsyncbypass; /* 266 * When set, this bit bypasses the DfiClk synchronizer on 267 * dfi_alert_n. 268 * Not valid here (fixed 0 value). 269 */ 270 271 uint32_t disdynadrtri; /* 272 * Disable Dynamic Per-MEMCLK Address Tristate feature. 273 * Program this variable if you require to disable this 274 * feature. 275 * - In DDR3/2T and DDR4/2T/2N modes, the dynamic tristate 276 * feature should be disabled if the controller cannot 277 * follow the 2T PHY tristate protocol. 278 * - In LPDDR4 mode, the dynamic tristate feature should 279 * be disabled. 280 * 281 * Value | Description 282 * ----- | ------ 283 * 0x1 | Disable Dynamic Tristate 284 */ 285 286 uint32_t phymstrtraininterval; /* 287 * Specifies the how frequent dfi_phymstr_req is issued by 288 * PHY. 289 * Only required in LPDDR4. 290 * Based on SI analysis determine how frequent DRAM drift 291 * compensation and re-training is required. 292 * Determine if Memory controller supports DFI PHY Master 293 * Interface. 294 * Program based on desired setting for 295 * PPTTrainSetup.PhyMstrTrainInterval register. 296 * Default value: 0xa 297 * 298 * Example: 299 * Value | Description 300 * ----- | ------ 301 * 0xa | PPT Train Interval = 268435456 MEMCLKs (default) 302 */ 303 304 uint32_t phymstrmaxreqtoack; /* 305 * Max time from dfi_phymstr_req asserted to dfi_phymstr_ack 306 * asserted. 307 * Only required in LPDDR4. 308 * Based on your Memory controller's(MC) specification 309 * determine how long the PHY should wait for the assertion 310 * of dfi_phymstr_ack once dfi_phymstr_req has been issued 311 * by the PHY. If the MC does not ack the PHY's request, PHY 312 * may issue dfi_error. 313 * This value will be used to program 314 * PPTTrainSetup.PhyMstrMaxReqToAck register. 315 * Default value: 0x5 316 * 317 * Example: 318 * Value | Description 319 * ----- | ------ 320 * 0x5 | PPT Max. Req to Ack. = 8192 MEMCLKs (default) 321 */ 322 323 uint32_t wdqsext; /* 324 * Enable Write DQS Extension feature of PHY. 325 * 326 * Value | Description 327 * ----- | ------ 328 * 0x0 | Disable Write DQS Extension feature. (default) 329 * 0x1 | Enable Write DQS Extension feature. 330 */ 331 332 uint32_t calinterval; /* 333 * Specifies the interval between successive calibrations, 334 * in mS. 335 * Program variable based on desired setting for 336 * CalRate.CalInterval register. 337 * - Fixed 0x9 value (20mS interval) 338 */ 339 340 uint32_t calonce; /* 341 * This setting changes the behaviour of CalRun register. 342 * If you desire to manually trigger impedance calibration 343 * in mission mode set this variable to 1, and toggle CalRun 344 * in mission mode. 345 * 346 * Value | Description 347 * ----- | ------ 348 * 0x0 | Calibration will proceed at the rate determined 349 * | by CalInterval. This field should only be changed 350 * | while the calibrator is idle. ie before csr 351 * | CalRun is set. 352 */ 353 354 uint32_t lp4rl; /* 355 * LPDDR4 Dram Read Latency. 356 * Applicable only if dramtype == LPDDR4. 357 * This variable is used to calculate LPDDR4 mr2-OP[2:0] 358 * set in the messageBlock. 359 * The training firmware will set DRAM MR according to MR 360 * value in the messageBlock at the end of training. 361 * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for 362 * definition of MR. 363 * Determine values based on your DRAM part's supported 364 * speed and latency bin. 365 * Default: calculated based on user_input_basic.frequency 366 * and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write 367 * Latencies". 368 * Lowest latency selected when more than one latency can be 369 * used. For example given configuration for LPDDR4, x16, 370 * NoDbi and DDR533, RL=10 is selected rather than 14. 371 */ 372 373 uint32_t lp4wl; /* 374 * LPDDR4 Dram Write Latency. 375 * Applicable only if dramtype == LPDDR4. 376 * This variable is used to calculate LPDDR4 mr2-OP[5:3] 377 * set in the messageBlock. 378 * The training firmware will set DRAM MR according to MR 379 * value in the messageBlock at the end of training. 380 * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for 381 * definition of MR. 382 * Determine values based on your DRAM part's supported 383 * speed and latency bin. 384 * Default: calculated based on user_input_basic.frequency 385 * and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write 386 * Latencies". 387 * Lowest latency selected when more than one latency can be 388 * used. 389 */ 390 391 uint32_t lp4wls; /* 392 * LPDDR4 Dram WL Set. 393 * Applicable only if dramtype == LPDDR4. 394 * This variable is used to calculate LPDDR4 mr2-OP[6] set 395 * in the messageBlock. 396 * The training firmware will set DRAM MR according to MR 397 * value in the messageBlock at the end of training. 398 * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for 399 * definition of MR. 400 * Determine value based on Memory controllers requirement 401 * of DRAM State after PHY training. 402 * 403 * Value | Description 404 * --- | --- 405 * 0x0 | WL Set "A" (default) 406 */ 407 408 uint32_t lp4dbird; /* 409 * LPDDR4 Dram DBI-Read Enable. 410 * Applicable only if dramtype == LPDDR4. 411 * Determine if you require to using DBI for the given 412 * PState. 413 * If Read DBI is not used PHY receivers are turned off to 414 * save power. 415 * This variable is used to calculate LPDDR4 mr3-OP[6] set 416 * in the messageBlock. 417 * The training firmware will set DRAM MR according to MR 418 * value in the messageBlock at the end of training. 419 * PHY register DMIPinPresent is programmed based on this 420 * parameter. 421 * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for 422 * definition of MR. 423 * 424 * Value | Description 425 * --- | --- 426 * 0x0 | Disabled (default) 427 * 0x1 | Enabled 428 */ 429 430 uint32_t lp4dbiwr; /* 431 * LPDDR4 Dram DBI-Write Enable. 432 * Applicable only if dramtype == LPDDR4. 433 * This variable is used to calculate LPDDR4 mr3-OP[7] set 434 * in the messageBlock. 435 * The training firmware will set DRAM MR according to MR 436 * value in the messageBlock at the end of training. 437 * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for 438 * definition of MR. 439 * 440 * Value | Description 441 * --- | --- 442 * 0x0 | Disabled (default) 443 * 0x1 | Enabled 444 */ 445 446 uint32_t lp4nwr; /* 447 * LPDDR4 Write-Recovery for Auto- Pre-charge commands. 448 * Applicable only if dramtype == LPDDR4. 449 * This variable is used to calculate LPDDR4 mr1-OP[6:4] set 450 * in the messageBlock. 451 * The training firmware will set DRAM MR according to MR 452 * value in the messageBlock at the end of training. 453 * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for 454 * definition of MR. 455 * Determine values based on your DRAM part's supported 456 * speed and latency bin. 457 * Default: calculated based on user_input_basic.frequency 458 * and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write 459 * Latencies". 460 * Lowest latency selected when more than one latency can be 461 * used. 462 * 463 * Binary Value | Description 464 * --- | --- 465 * 000 | nWR = 6 (default) 466 * 001 | nWR = 10 467 * 010 | nWR = 16 468 * 011 | nWR = 20 469 * 100 | nWR = 24 470 * 101 | nWR = 30 471 * 110 | nWR = 34 472 * 111 | nWR = 40 473 */ 474 475 uint32_t lp4lowpowerdrv; /* 476 * Configure output Driver in Low power mode. 477 * Feature only supported for Hard Macro Family E (HME). 478 * Use NMOS Pull-up for Low-Power IO. 479 * Not valid here 480 */ 481 482 uint32_t drambyteswap; /* 483 * DRAM Oscillator count source mapping for skip_training. 484 * The PHY supports swapping of DRAM oscillator count values 485 * between paired DBytes for the purpose of tDQSDQ DRAM 486 * Drift Compensation(DDC). 487 * Each DByte has a register bit to control the source of 488 * the oscillator count value used to perform tDQSDQ Drift 489 * compensation. 490 * On silicon the training firmware will determine the DByte 491 * swap and program PptCtlStatic register to select 492 * oscillator count source. When skip_train is used, 493 * training firmware is skipped thus manual programming may 494 * be required depending on configuration. 495 * The default hardware configuration is for odd Dbyte 496 * instance n to use oscillator count values from its paired 497 * Dbyte instance n-1. So Dbyte1 will use the oscillator 498 * count values from Dbyte0, Dbyte3 will use Dbyte2 and so 499 * on. This is required for DRAM Data width =16. 500 * Each bit of this field corresponds to a DBYTE: 501 * - bit-0 = setting for DBYTE0 502 * - bit-1 = setting for DBYTE1 503 * - bit-2 = setting for DBYTE2 504 * - . . . 505 * - bit-n = setting for DBYTEn 506 * By setting the associated bit for each DByte to 1, PHY 507 * will use non-default source for count value. 508 * - for even Dbytes, non-default source is to use the odd 509 * pair count value. 510 * - for odd Dbytes, no-default source to use data 511 * received directly from the DRAM. 512 * Byte swapping must be the same across different ranks. 513 * Default value: 0x0 514 * If Byte mode devices are indicated via the x8mode 515 * messageBlock parameter, this variable is ignored as PHY 516 * only supports a limited configuration set based on Byte 517 * mode configuration. 518 * 519 * Example: 520 * DramByteSwap = 0x03 - Dbyte0: use count values from 521 * Dbyte1, Dbyte1 uses count values received directly 522 * received from DRAM. 523 * Rest of Dbytes have default source for DRAM oscilator 524 * count. 525 */ 526 527 uint32_t rxenbackoff; /* 528 * Determines the Placement of PHY Read Gate signal. 529 * Only used in LPDDR4 when lp4rxpreamblemode==0 (static 530 * preamble) for skip_train==true. 531 * For other dramtypes or LPDDR4-toggling-preamble no 532 * options are available and PhyInit will set position as 533 * required. See source code in 534 * ddrphy_phyinit_c_initphyconfig() to see how the 535 * RxEnBackOff register is set. 536 * For skip_train==false, FW will set the position based on 537 * Preamble. 538 * We recommend keeping this setting at default value. 539 * SI analysis is required to determine if default value 540 * needs to be changed. 541 * 542 * Value | Description 543 * ----- | --- 544 * 0x1 | Position read gate 1UI from the first valid edge 545 * | of DQS_t (LPDDR4 Static preamble only) (default) 546 */ 547 548 uint32_t trainsequencectrl; /* 549 * Firmware Training Sequence Control. 550 * This input is used to program sequencectrl in 551 * messageBlock. 552 * It controls the training stages executed by firmware. 553 * For production silicon we recommend to use default value 554 * programmed by PhyInit. 555 */ 556 557 uint32_t snpsumctlopt; /* 558 * Enable Fast Frequency Change (FFC) Optimizations 559 * specific to UMCTL2 (DDRCTRL). 560 * Not valid for dimmtype=NODIMM. 561 * Consult DDRCTRL documentation in Reference Manual to 562 * ensure when optimizations can be enabled. 563 * 564 * Value | Description 565 * ----- | --- 566 * 0 | Disable FFC MRW optimization (default) 567 */ 568 569 uint32_t snpsumctlf0rc5x; /* 570 * F0RX5x RCD Control Word when using Fast Frequency 571 * Change(FFC) optimizations specific to UMCTL2 572 * Not valid for dimmtype=NODIMM. 573 * Only valid for when SnpsUmctlOpt=1. 574 * When UMCTL2 optimizations are enabled PHY will perform 575 * RCD MRW during fast frequency change request. 576 * The correct RCD control word value for each PState must 577 * be programmed in this field. 578 * Consult the RCD spec and UMCTL documentation to 579 * determine the correct value based on DRAM configuration 580 * and operating speed. 581 */ 582 583 uint32_t txslewrisedq; /* 584 * Pull-up slew rate control for DBYTE Tx. 585 * Value specified here will be written to register 586 * TxSlewRate.TxPreP by PhyInit. 587 * See register description for more information. 588 */ 589 590 uint32_t txslewfalldq; /* 591 * Pull-down slew rate control for DBYTE Tx. 592 * Value specified here will be written to 593 * TxSlewRate.TxPreN by PhyInit. 594 * See register description for more information. 595 */ 596 597 uint32_t txslewriseac; /* 598 * Pull-up slew rate control for ANIB Tx. 599 * Value specified here will be written to 600 * ATxSlewRate.ATxPreP. 601 * See register description for more information. 602 */ 603 604 uint32_t txslewfallac; /* 605 * Pull-down slew rate control for ANIB Tx. 606 * Value specified here will be written to 607 * ATxSlewRate.ATxPreN. 608 * See register description for more information. 609 */ 610 611 uint32_t disableretraining; /* 612 * Disable PHY DRAM Drift compensation re-training. 613 * Only applied to LPDDR4. No retraining is required in 614 * DDR4/3. 615 * Disable PHY re-training during DFI frequency change 616 * requests in LPDDR4. 617 * The purpose of retraining is to compensate for drift in 618 * the DRAM. 619 * Determine based on SI analysis and DRAM datasheet if 620 * retraining can be disabled. 621 * 622 * Value | Description 623 * ----- | --- 624 * 0x1 | Disable retraining 625 * 0x0 | Enable retraining 626 */ 627 628 uint32_t disablephyupdate; /* 629 * Disable DFI PHY Update feature. 630 * Only effects LPDDR4. 631 * Disable DFI PHY Update feature. When set PHY will not 632 * assert dfi0/1_phyupd_req. 633 * 634 * Value | Description 635 * ----- | --- 636 * 0x1 | Disable DFI PHY Update 637 * 0x0 | Enable DFI PHY Update 638 */ 639 640 uint32_t enablehighclkskewfix; /* 641 * Enable alternative PIE program. 642 * If enabled the PIE reinitializes the FIFO pointers a 643 * second time due for designs with large skew between 644 * chiplet DfiClk branches. If enabled PIE latencies in all 645 * protocols are increased by 60 DfiClks. 646 * 647 * Value | Description 648 * ----- | --- 649 * 0x0 | Disable (default) 650 */ 651 652 uint32_t disableunusedaddrlns; /* 653 * Turn off or tristate Address Lanes when possible. 654 * 655 * When enabled, PHY will tristate unused address lanes to 656 * save power when possible by using Acx4AnibDis and 657 * AForceTriCont registers. 658 * This feature is only implemented for the default PHY 659 * Address bump mapping and Ranks must be populated in 660 * order. ie Rank1 cannot be used if Rank0 is unpopulated. 661 * For alternative bump mapping follow the following 662 * guideline to achieve maximum power savings: 663 * - For each unused BP_A bump program AForceTriCont[4:0] 664 * bits based on register description. 665 * - if all lanes of an Anib are unused _AND_ ANIB is not 666 * the first or last instance set bit associated with 667 * the instance in Acs4AnibDis registers. see register 668 * description for details. 669 * 670 * Value | Description 671 * ----- | --- 672 * 0x1 | Enable 673 */ 674 675 uint32_t phyinitsequencenum; /* 676 * Switches between supported phyinit training sequences. 677 * 678 * Value | Description 679 * ----- | --- 680 * 0x0 | Minimizes number of Imem/Dmem loads (default) 681 */ 682 683 uint32_t enabledficspolarityfix;/* 684 * Enable alternative PIE program. 685 * Set to 1 if PUB_VERSION <2.43a, otherwise set to 0. If 686 * enabled the PIE programs Dfi{Rd,Wr}DataCsDestMap CSR's 687 * to default values 0x00E4 before running PPT. 688 * Before exiting PPT, PIE will restore 689 * Dfi{Rd,Wr}DataCsDestMap CSR's to 0x00E1. 690 * 691 * Value | Description 692 * ----- | --- 693 * 0x0 | Disable (default) 694 */ 695 696 uint32_t phyvref; /* 697 * Must be programmed with the Vref level to be used by the 698 * PHY during reads. 699 * The units of this field are a percentage of VDDQ 700 * according to the following equation: 701 * Receiver Vref = VDDQ*phyvref[6:0]/128 702 * For example to set Vref at 0.75*VDDQ, set this field to 703 * 0x60. 704 * For digital simulation, any legal value can be used. For 705 * silicon, the users must calculate the analytical Vref by 706 * using the impedances, terminations, and series resistance 707 * present in the system. 708 */ 709 710 uint32_t sequencectrl; /* 711 * Controls the training steps to be run. Each bit 712 * corresponds to a training step. 713 * If the bit is set to 1, the training step will run. 714 * If the bit is set to 0, the training step will be 715 * skipped. 716 * Training step to bit mapping: 717 * sequencectrl[0] = Run DevInit - Device/phy 718 * initialization. Should always be set. 719 * sequencectrl[1] = Run WrLvl - Write leveling 720 * sequencectrl[2] = Run RxEn - Read gate training 721 * sequencectrl[3] = Run RdDQS1D - 1d read dqs training 722 * sequencectrl[4] = Run WrDQ1D - 1d write dq training 723 * sequencectrl[5] = RFU, must be zero 724 * sequencectrl[6] = RFU, must be zero 725 * sequencectrl[7] = RFU, must be zero 726 * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew 727 * training 728 * sequencectrl[9] = Run MxRdLat - Max read latency training 729 * sequencectrl[10] = RFU, must be zero 730 * sequencectrl[11] = RFU, must be zero 731 * sequencectrl[12] = RFU, must be zero 732 * sequencectrl[13] = RFU, must be zero 733 * sequencectrl[15-14] = RFU, must be zero 734 */ 735 }; 736 737 /* 738 * Structure for mode register user inputs 739 * 740 * The following data structure must be set and completed correctly so that the PhyInit software 741 * package can accurate fill message block structure. 742 * Only some mrx are used per DDR type, on related width: 743 * - DDR3: mr0..2 are used (16-bits values) 744 * - DDR4: mr0..6 are used (16-bits values) 745 * - LPDDR4: mr1..4 and mr11..22 are used (8-bits values) 746 */ 747 struct user_input_mode_register { 748 uint32_t mr0; 749 uint32_t mr1; 750 uint32_t mr2; 751 uint32_t mr3; 752 uint32_t mr4; 753 uint32_t mr5; 754 uint32_t mr6; 755 uint32_t mr11; 756 uint32_t mr12; 757 uint32_t mr13; 758 uint32_t mr14; 759 uint32_t mr22; 760 }; 761 762 /* 763 * Structure for swizzle user inputs 764 * 765 * The following data structure must be set and completed correctly sothat the PhyInit software 766 * package can accurate set swizzle (IO muxing) config. 767 * Only some swizzles are used per DDR type: 768 * - DDR3/DDR4: swizzle 0..32 are used 769 * - 26 for hwtswizzle 770 * - 7 for acswizzle 771 * - LPDDR4: swizzle 0..43 are used 772 * - 8 per byte for dqlnsel (total 32) 773 * - 6 for mapcaatodfi 774 * - 6 for mapcabtodfi 775 */ 776 #define NB_HWT_SWIZZLE 26U 777 #define NB_AC_SWIZZLE 7U 778 #define NB_DQLNSEL_SWIZZLE_PER_BYTE 8U 779 #define NB_MAPCAATODFI_SWIZZLE 6U 780 #define NB_MAPCABTODFI_SWIZZLE 6U 781 #define NB_SWIZZLE 44 782 struct user_input_swizzle { 783 uint32_t swizzle[NB_SWIZZLE]; 784 }; 785 786 #endif /* DDRPHY_PHYINIT_STRUCT_H */ 787