1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 30 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 31workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 32 33check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 34 35workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 36 /* Disable retention control for WFI and WFE. */ 37 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 38 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 39 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 40 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 41workaround_reset_end cortex_x3, ERRATUM(2615812) 42 43check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 44 45workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 46 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 47 sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 48 sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 49workaround_reset_end cortex_x3, ERRATUM(2742421) 50 51check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) 52 53workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 54#if IMAGE_BL31 55 override_vector_table wa_cve_vbar_cortex_x3 56#endif /* IMAGE_BL31 */ 57workaround_reset_end cortex_x3, CVE(2022, 23960) 58 59check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 60 61cpu_reset_func_start cortex_x3 62 /* Disable speculative loads */ 63 msr SSBS, xzr 64cpu_reset_func_end cortex_x3 65 66 /* ---------------------------------------------------- 67 * HW will do the cache maintenance while powering down 68 * ---------------------------------------------------- 69 */ 70func cortex_x3_core_pwr_dwn 71apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 72 /* --------------------------------------------------- 73 * Enable CPU power down bit in power control register 74 * --------------------------------------------------- 75 */ 76 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 77 isb 78 ret 79endfunc cortex_x3_core_pwr_dwn 80 81errata_report_shim cortex_x3 82 83 /* --------------------------------------------- 84 * This function provides Cortex-X3- 85 * specific register information for crash 86 * reporting. It needs to return with x6 87 * pointing to a list of register names in ascii 88 * and x8 - x15 having values of registers to be 89 * reported. 90 * --------------------------------------------- 91 */ 92.section .rodata.cortex_x3_regs, "aS" 93cortex_x3_regs: /* The ascii list of register names to be reported */ 94 .asciz "cpuectlr_el1", "" 95 96func cortex_x3_cpu_reg_dump 97 adr x6, cortex_x3_regs 98 mrs x8, CORTEX_X3_CPUECTLR_EL1 99 ret 100endfunc cortex_x3_cpu_reg_dump 101 102declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ 103 cortex_x3_reset_func, \ 104 cortex_x3_core_pwr_dwn 105