1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <cdefs.h> 8 #include <stdint.h> 9 10 #include <common/debug.h> 11 #include <drivers/clk.h> 12 #include <drivers/st/regulator_fixed.h> 13 #include <drivers/st/stm32mp2_ddr_helpers.h> 14 #include <lib/fconf/fconf.h> 15 #include <lib/fconf/fconf_dyn_cfg_getter.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_tables_v2.h> 18 #include <plat/common/platform.h> 19 20 #include <platform_def.h> 21 #include <stm32mp_common.h> 22 #include <stm32mp_dt.h> 23 24 #define BOOT_CTX_ADDR 0x0e000020UL 25 26 static void print_reset_reason(void) 27 { 28 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR); 29 30 if (rstsr == 0U) { 31 WARN("Reset reason unknown\n"); 32 return; 33 } 34 35 INFO("Reset reason (0x%x):\n", rstsr); 36 37 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) { 38 if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) { 39 INFO("System exits from Standby for CA35\n"); 40 return; 41 } 42 43 if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) { 44 INFO("D1 domain exits from DStandby\n"); 45 return; 46 } 47 } 48 49 if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) { 50 INFO(" Power-on Reset (rst_por)\n"); 51 return; 52 } 53 54 if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) { 55 INFO(" Brownout Reset (rst_bor)\n"); 56 return; 57 } 58 59 if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) { 60 INFO(" System reset (SYSRST) by M33\n"); 61 return; 62 } 63 64 if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) { 65 INFO(" System reset (SYSRST) by A35\n"); 66 return; 67 } 68 69 if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) { 70 INFO(" Clock failure on HSE\n"); 71 return; 72 } 73 74 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) { 75 INFO(" IWDG1 system reset (rst_iwdg1)\n"); 76 return; 77 } 78 79 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) { 80 INFO(" IWDG2 system reset (rst_iwdg2)\n"); 81 return; 82 } 83 84 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) { 85 INFO(" IWDG3 system reset (rst_iwdg3)\n"); 86 return; 87 } 88 89 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) { 90 INFO(" IWDG4 system reset (rst_iwdg4)\n"); 91 return; 92 } 93 94 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) { 95 INFO(" IWDG5 system reset (rst_iwdg5)\n"); 96 return; 97 } 98 99 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) { 100 INFO(" A35 processor core 1 reset\n"); 101 return; 102 } 103 104 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) { 105 INFO(" Pad Reset from NRST\n"); 106 return; 107 } 108 109 if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) { 110 INFO(" Reset due to a failure of VDD_CORE\n"); 111 return; 112 } 113 114 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) { 115 INFO(" A35 processor reset\n"); 116 return; 117 } 118 119 ERROR(" Unidentified reset reason\n"); 120 } 121 122 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 123 u_register_t arg1 __unused, 124 u_register_t arg2 __unused, 125 u_register_t arg3 __unused) 126 { 127 stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR); 128 } 129 130 void bl2_platform_setup(void) 131 { 132 } 133 134 static void reset_backup_domain(void) 135 { 136 uintptr_t pwr_base = stm32mp_pwr_base(); 137 uintptr_t rcc_base = stm32mp_rcc_base(); 138 139 /* 140 * Disable the backup domain write protection. 141 * The protection is enable at each reset by hardware 142 * and must be disabled by software. 143 */ 144 mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P); 145 146 while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) { 147 ; 148 } 149 150 /* Reset backup domain on cold boot cases */ 151 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) { 152 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 153 154 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) { 155 ; 156 } 157 158 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 159 } 160 } 161 162 void bl2_el3_plat_arch_setup(void) 163 { 164 const char *board_model; 165 boot_api_context_t *boot_context = 166 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 167 168 if (stm32_otp_probe() != 0U) { 169 EARLY_ERROR("OTP probe failed\n"); 170 panic(); 171 } 172 173 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 174 BL_CODE_END - BL_CODE_BASE, 175 MT_CODE | MT_SECURE); 176 177 configure_mmu(); 178 179 /* Prevent corruption of preloaded Device Tree */ 180 mmap_add_dynamic_region(DTB_BASE, DTB_BASE, 181 DTB_LIMIT - DTB_BASE, 182 MT_RO_DATA | MT_SECURE); 183 184 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 185 panic(); 186 } 187 188 reset_backup_domain(); 189 190 /* 191 * Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2), 192 * and so before stm32mp2_clk_init(). 193 */ 194 ddr_sub_system_clk_init(); 195 196 if (stm32mp2_clk_init() < 0) { 197 panic(); 198 } 199 200 stm32_save_boot_info(boot_context); 201 202 if (stm32mp_uart_console_setup() != 0) { 203 goto skip_console_init; 204 } 205 206 stm32mp_print_cpuinfo(); 207 208 board_model = dt_get_board_model(); 209 if (board_model != NULL) { 210 NOTICE("Model: %s\n", board_model); 211 } 212 213 stm32mp_print_boardinfo(); 214 215 print_reset_reason(); 216 217 skip_console_init: 218 if (fixed_regulator_register() != 0) { 219 panic(); 220 } 221 222 fconf_populate("TB_FW", STM32MP_DTB_BASE); 223 224 stm32mp_io_setup(); 225 } 226