1/* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/xlat_tables/xlat_tables_defs.h> 15 16 /* 17 * Helper macro to initialise EL3 registers we care about. 18 */ 19 .macro el3_arch_init_common 20 /* --------------------------------------------------------------------- 21 * SCTLR_EL3 has already been initialised - read current value before 22 * modifying. 23 * 24 * SCTLR_EL3.I: Enable the instruction cache. 25 * 26 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 27 * exception is generated if a load or store instruction executed at 28 * EL3 uses the SP as the base address and the SP is not aligned to a 29 * 16-byte boundary. 30 * 31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 32 * load or store one or more registers have an alignment check that the 33 * address being accessed is aligned to the size of the data element(s) 34 * being accessed. 35 * --------------------------------------------------------------------- 36 */ 37 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 38 mrs x0, sctlr_el3 39 orr x0, x0, x1 40 msr sctlr_el3, x0 41 isb 42 43#ifdef IMAGE_BL31 44 /* --------------------------------------------------------------------- 45 * Initialise the per-cpu cache pointer to the CPU. 46 * This is done early to enable crash reporting to have access to crash 47 * stack. Since crash reporting depends on cpu_data to report the 48 * unhandled exception, not doing so can lead to recursive exceptions 49 * due to a NULL TPIDR_EL3. 50 * --------------------------------------------------------------------- 51 */ 52 bl init_cpu_data_ptr 53#endif /* IMAGE_BL31 */ 54 55 /* --------------------------------------------------------------------- 56 * Initialise SCR_EL3, setting all fields rather than relying on hw. 57 * All fields are architecturally UNKNOWN on reset. The following fields 58 * do not change during the TF lifetime. The remaining fields are set to 59 * zero here but are updated ahead of transitioning to a lower EL in the 60 * function cm_init_context_common(). 61 * 62 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 63 * EL2, EL1 and EL0 are not trapped to EL3. 64 * 65 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 66 * EL2, EL1 and EL0 are not trapped to EL3. 67 * 68 * SCR_EL3.SIF: Set to one to disable instruction fetches from 69 * Non-secure memory. 70 * 71 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 72 * both Security states and both Execution states. 73 * 74 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 75 * to EL3 when executing at any EL. 76 * 77 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, 78 * disable traps to EL3 when accessing key registers or using pointer 79 * authentication instructions from lower ELs. 80 * --------------------------------------------------------------------- 81 */ 82 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ 83 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) 84#if CTX_INCLUDE_PAUTH_REGS 85 /* 86 * If the pointer authentication registers are saved during world 87 * switches, enable pointer authentication everywhere, as it is safe to 88 * do so. 89 */ 90 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 91#endif 92#if ENABLE_RME 93 /* 94 * TODO: Settting the EEL2 bit to allow EL3 access to secure only registers 95 * in context management. This will need to be refactored. 96 */ 97 orr x0, x0, #SCR_EEL2_BIT 98#endif 99 msr scr_el3, x0 100 101 /* --------------------------------------------------------------------- 102 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 103 * Some fields are architecturally UNKNOWN on reset. 104 * 105 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 106 * Debug exceptions, other than Breakpoint Instruction exceptions, are 107 * disabled from all ELs in Secure state. 108 * 109 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 110 * privileged debug from S-EL1. 111 * 112 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 113 * access to the powerdown debug registers do not trap to EL3. 114 * 115 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 116 * debug registers, other than those registers that are controlled by 117 * MDCR_EL3.TDOSA. 118 */ 119 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 120 MDCR_SPD32(MDCR_SPD32_DISABLE)) & \ 121 ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT)) 122 123 msr mdcr_el3, x0 124 125 /* --------------------------------------------------------------------- 126 * Enable External Aborts and SError Interrupts now that the exception 127 * vectors have been setup. 128 * --------------------------------------------------------------------- 129 */ 130 msr daifclr, #DAIF_ABT_BIT 131 132 /* --------------------------------------------------------------------- 133 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 134 * All fields are architecturally UNKNOWN on reset. 135 * 136 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, 137 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. 138 * 139 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 140 * by Advanced SIMD, floating-point or SVE instructions (if implemented) 141 * do not trap to EL3. 142 * 143 * CPTR_EL3.TAM: Set to one so that Activity Monitor access is 144 * trapped to EL3 by default. 145 * 146 * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped 147 * to EL3 by default. 148 * 149 * CPTR_EL3.ESM: Set to zero so that all SME functionality is trapped 150 * to EL3 by default. 151 */ 152 153 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT)) 154 msr cptr_el3, x0 155 156 /* 157 * If Data Independent Timing (DIT) functionality is implemented, 158 * always enable DIT in EL3. 159 * First assert that the FEAT_DIT build flag matches the feature id 160 * register value for DIT. 161 */ 162#if ENABLE_FEAT_DIT 163#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1 164 mrs x0, id_aa64pfr0_el1 165 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 166#if ENABLE_FEAT_DIT > 1 167 cbz x0, 1f 168#else 169 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 170 ASM_ASSERT(eq) 171#endif 172 173#endif /* ENABLE_ASSERTIONS */ 174 mov x0, #DIT_BIT 175 msr DIT, x0 1761: 177#endif 178 .endm 179 180/* ----------------------------------------------------------------------------- 181 * This is the super set of actions that need to be performed during a cold boot 182 * or a warm boot in EL3. This code is shared by BL1 and BL31. 183 * 184 * This macro will always perform reset handling, architectural initialisations 185 * and stack setup. The rest of the actions are optional because they might not 186 * be needed, depending on the context in which this macro is called. This is 187 * why this macro is parameterised ; each parameter allows to enable/disable 188 * some actions. 189 * 190 * _init_sctlr: 191 * Whether the macro needs to initialise SCTLR_EL3, including configuring 192 * the endianness of data accesses. 193 * 194 * _warm_boot_mailbox: 195 * Whether the macro needs to detect the type of boot (cold/warm). The 196 * detection is based on the platform entrypoint address : if it is zero 197 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 198 * this macro jumps on the platform entrypoint address. 199 * 200 * _secondary_cold_boot: 201 * Whether the macro needs to identify the CPU that is calling it: primary 202 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 203 * the platform initialisations, while the secondaries will be put in a 204 * platform-specific state in the meantime. 205 * 206 * If the caller knows this macro will only be called by the primary CPU 207 * then this parameter can be defined to 0 to skip this step. 208 * 209 * _init_memory: 210 * Whether the macro needs to initialise the memory. 211 * 212 * _init_c_runtime: 213 * Whether the macro needs to initialise the C runtime environment. 214 * 215 * _exception_vectors: 216 * Address of the exception vectors to program in the VBAR_EL3 register. 217 * 218 * _pie_fixup_size: 219 * Size of memory region to fixup Global Descriptor Table (GDT). 220 * 221 * A non-zero value is expected when firmware needs GDT to be fixed-up. 222 * 223 * ----------------------------------------------------------------------------- 224 */ 225 .macro el3_entrypoint_common \ 226 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 227 _init_memory, _init_c_runtime, _exception_vectors, \ 228 _pie_fixup_size 229 230 .if \_init_sctlr 231 /* ------------------------------------------------------------- 232 * This is the initialisation of SCTLR_EL3 and so must ensure 233 * that all fields are explicitly set rather than relying on hw. 234 * Some fields reset to an IMPLEMENTATION DEFINED value and 235 * others are architecturally UNKNOWN on reset. 236 * 237 * SCTLR.EE: Set the CPU endianness before doing anything that 238 * might involve memory reads or writes. Set to zero to select 239 * Little Endian. 240 * 241 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 242 * force all memory regions that are writeable to be treated as 243 * XN (Execute-never). Set to zero so that this control has no 244 * effect on memory access permissions. 245 * 246 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 247 * 248 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 249 * 250 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 251 * safe behaviour upon exception entry to EL3. 252 * ------------------------------------------------------------- 253 */ 254 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 255 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 256 msr sctlr_el3, x0 257 isb 258 .endif /* _init_sctlr */ 259 260 .if \_warm_boot_mailbox 261 /* ------------------------------------------------------------- 262 * This code will be executed for both warm and cold resets. 263 * Now is the time to distinguish between the two. 264 * Query the platform entrypoint address and if it is not zero 265 * then it means it is a warm boot so jump to this address. 266 * ------------------------------------------------------------- 267 */ 268 bl plat_get_my_entrypoint 269 cbz x0, do_cold_boot 270 br x0 271 272 do_cold_boot: 273 .endif /* _warm_boot_mailbox */ 274 275 .if \_pie_fixup_size 276#if ENABLE_PIE 277 /* 278 * ------------------------------------------------------------ 279 * If PIE is enabled fixup the Global descriptor Table only 280 * once during primary core cold boot path. 281 * 282 * Compile time base address, required for fixup, is calculated 283 * using "pie_fixup" label present within first page. 284 * ------------------------------------------------------------ 285 */ 286 pie_fixup: 287 ldr x0, =pie_fixup 288 and x0, x0, #~(PAGE_SIZE_MASK) 289 mov_imm x1, \_pie_fixup_size 290 add x1, x1, x0 291 bl fixup_gdt_reloc 292#endif /* ENABLE_PIE */ 293 .endif /* _pie_fixup_size */ 294 295 /* --------------------------------------------------------------------- 296 * Set the exception vectors. 297 * --------------------------------------------------------------------- 298 */ 299 adr x0, \_exception_vectors 300 msr vbar_el3, x0 301 isb 302 303#if !(defined(IMAGE_BL2) && ENABLE_RME) 304 /* --------------------------------------------------------------------- 305 * It is a cold boot. 306 * Perform any processor specific actions upon reset e.g. cache, TLB 307 * invalidations etc. 308 * --------------------------------------------------------------------- 309 */ 310 bl reset_handler 311#endif 312 313 el3_arch_init_common 314 315 .if \_secondary_cold_boot 316 /* ------------------------------------------------------------- 317 * Check if this is a primary or secondary CPU cold boot. 318 * The primary CPU will set up the platform while the 319 * secondaries are placed in a platform-specific state until the 320 * primary CPU performs the necessary actions to bring them out 321 * of that state and allows entry into the OS. 322 * ------------------------------------------------------------- 323 */ 324 bl plat_is_my_cpu_primary 325 cbnz w0, do_primary_cold_boot 326 327 /* This is a cold boot on a secondary CPU */ 328 bl plat_secondary_cold_boot_setup 329 /* plat_secondary_cold_boot_setup() is not supposed to return */ 330 bl el3_panic 331 332 do_primary_cold_boot: 333 .endif /* _secondary_cold_boot */ 334 335 /* --------------------------------------------------------------------- 336 * Initialize memory now. Secondary CPU initialization won't get to this 337 * point. 338 * --------------------------------------------------------------------- 339 */ 340 341 .if \_init_memory 342 bl platform_mem_init 343 .endif /* _init_memory */ 344 345 /* --------------------------------------------------------------------- 346 * Init C runtime environment: 347 * - Zero-initialise the NOBITS sections. There are 2 of them: 348 * - the .bss section; 349 * - the coherent memory section (if any). 350 * - Relocate the data section from ROM to RAM, if required. 351 * --------------------------------------------------------------------- 352 */ 353 .if \_init_c_runtime 354#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 355 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 356 /* ------------------------------------------------------------- 357 * Invalidate the RW memory used by the BL31 image. This 358 * includes the data and NOBITS sections. This is done to 359 * safeguard against possible corruption of this memory by 360 * dirty cache lines in a system cache as a result of use by 361 * an earlier boot loader stage. If PIE is enabled however, 362 * RO sections including the GOT may be modified during 363 * pie fixup. Therefore, to be on the safe side, invalidate 364 * the entire image region if PIE is enabled. 365 * ------------------------------------------------------------- 366 */ 367#if ENABLE_PIE 368#if SEPARATE_CODE_AND_RODATA 369 adrp x0, __TEXT_START__ 370 add x0, x0, :lo12:__TEXT_START__ 371#else 372 adrp x0, __RO_START__ 373 add x0, x0, :lo12:__RO_START__ 374#endif /* SEPARATE_CODE_AND_RODATA */ 375#else 376 adrp x0, __RW_START__ 377 add x0, x0, :lo12:__RW_START__ 378#endif /* ENABLE_PIE */ 379 adrp x1, __RW_END__ 380 add x1, x1, :lo12:__RW_END__ 381 sub x1, x1, x0 382 bl inv_dcache_range 383#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 384 adrp x0, __NOBITS_START__ 385 add x0, x0, :lo12:__NOBITS_START__ 386 adrp x1, __NOBITS_END__ 387 add x1, x1, :lo12:__NOBITS_END__ 388 sub x1, x1, x0 389 bl inv_dcache_range 390#endif 391#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 392 adrp x0, __BL2_NOLOAD_START__ 393 add x0, x0, :lo12:__BL2_NOLOAD_START__ 394 adrp x1, __BL2_NOLOAD_END__ 395 add x1, x1, :lo12:__BL2_NOLOAD_END__ 396 sub x1, x1, x0 397 bl inv_dcache_range 398#endif 399#endif 400 adrp x0, __BSS_START__ 401 add x0, x0, :lo12:__BSS_START__ 402 403 adrp x1, __BSS_END__ 404 add x1, x1, :lo12:__BSS_END__ 405 sub x1, x1, x0 406 bl zeromem 407 408#if USE_COHERENT_MEM 409 adrp x0, __COHERENT_RAM_START__ 410 add x0, x0, :lo12:__COHERENT_RAM_START__ 411 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 412 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 413 sub x1, x1, x0 414 bl zeromem 415#endif 416 417#if defined(IMAGE_BL1) || \ 418 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) 419 adrp x0, __DATA_RAM_START__ 420 add x0, x0, :lo12:__DATA_RAM_START__ 421 adrp x1, __DATA_ROM_START__ 422 add x1, x1, :lo12:__DATA_ROM_START__ 423 adrp x2, __DATA_RAM_END__ 424 add x2, x2, :lo12:__DATA_RAM_END__ 425 sub x2, x2, x0 426 bl memcpy16 427#endif 428 .endif /* _init_c_runtime */ 429 430 /* --------------------------------------------------------------------- 431 * Use SP_EL0 for the C runtime stack. 432 * --------------------------------------------------------------------- 433 */ 434 msr spsel, #0 435 436 /* --------------------------------------------------------------------- 437 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 438 * the MMU is enabled. There is no risk of reading stale stack memory 439 * after enabling the MMU as only the primary CPU is running at the 440 * moment. 441 * --------------------------------------------------------------------- 442 */ 443 bl plat_set_my_stack 444 445#if STACK_PROTECTOR_ENABLED 446 .if \_init_c_runtime 447 bl update_stack_protector_canary 448 .endif /* _init_c_runtime */ 449#endif 450 .endm 451 452 .macro apply_at_speculative_wa 453#if ERRATA_SPECULATIVE_AT 454 /* 455 * This function expects x30 has been saved. 456 * Also, save x29 which will be used in the called function. 457 */ 458 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 459 bl save_and_update_ptw_el1_sys_regs 460 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 461#endif 462 .endm 463 464 .macro restore_ptw_el1_sys_regs 465#if ERRATA_SPECULATIVE_AT 466 /* ----------------------------------------------------------- 467 * In case of ERRATA_SPECULATIVE_AT, must follow below order 468 * to ensure that page table walk is not enabled until 469 * restoration of all EL1 system registers. TCR_EL1 register 470 * should be updated at the end which restores previous page 471 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 472 * ensures that CPU does below steps in order. 473 * 474 * 1. Ensure all other system registers are written before 475 * updating SCTLR_EL1 using ISB. 476 * 2. Restore SCTLR_EL1 register. 477 * 3. Ensure SCTLR_EL1 written successfully using ISB. 478 * 4. Restore TCR_EL1 register. 479 * ----------------------------------------------------------- 480 */ 481 isb 482 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] 483 msr sctlr_el1, x28 484 isb 485 msr tcr_el1, x29 486#endif 487 .endm 488 489#endif /* EL3_COMMON_MACROS_S */ 490