1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <drivers/clk.h> 7 #include <s32cc-clk-drv.h> 8 #include <s32cc-clk-ids.h> 9 #include <s32cc-clk-utils.h> 10 11 #define S32CC_FXOSC_FREQ (40U * MHZ) 12 #define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ) 13 #define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ) 14 #define S32CC_A53_FREQ (1U * GHZ) 15 #define S32CC_XBAR_2X_FREQ (800U * MHZ) 16 17 static int enable_fxosc_clk(void) 18 { 19 int ret; 20 21 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL); 22 if (ret != 0) { 23 return ret; 24 } 25 26 ret = clk_enable(S32CC_CLK_FXOSC); 27 if (ret != 0) { 28 return ret; 29 } 30 31 return ret; 32 } 33 34 static int enable_arm_pll(void) 35 { 36 int ret; 37 38 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC); 39 if (ret != 0) { 40 return ret; 41 } 42 43 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL); 44 if (ret != 0) { 45 return ret; 46 } 47 48 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL); 49 if (ret != 0) { 50 return ret; 51 } 52 53 ret = clk_enable(S32CC_CLK_ARM_PLL_VCO); 54 if (ret != 0) { 55 return ret; 56 } 57 58 ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0); 59 if (ret != 0) { 60 return ret; 61 } 62 63 return ret; 64 } 65 66 static int enable_a53_clk(void) 67 { 68 int ret; 69 70 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0); 71 if (ret != 0) { 72 return ret; 73 } 74 75 ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL); 76 if (ret != 0) { 77 return ret; 78 } 79 80 ret = clk_enable(S32CC_CLK_A53_CORE); 81 if (ret != 0) { 82 return ret; 83 } 84 85 return ret; 86 } 87 88 static int enable_xbar_clk(void) 89 { 90 int ret; 91 92 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX0, S32CC_CLK_ARM_PLL_DFS1); 93 if (ret != 0) { 94 return ret; 95 } 96 97 ret = clk_set_rate(S32CC_CLK_XBAR_2X, S32CC_XBAR_2X_FREQ, NULL); 98 if (ret != 0) { 99 return ret; 100 } 101 102 ret = clk_enable(S32CC_CLK_ARM_PLL_DFS1); 103 if (ret != 0) { 104 return ret; 105 } 106 107 ret = clk_enable(S32CC_CLK_XBAR_2X); 108 if (ret != 0) { 109 return ret; 110 } 111 112 return ret; 113 } 114 115 int s32cc_init_early_clks(void) 116 { 117 int ret; 118 119 s32cc_clk_register_drv(); 120 121 ret = enable_fxosc_clk(); 122 if (ret != 0) { 123 return ret; 124 } 125 126 ret = enable_arm_pll(); 127 if (ret != 0) { 128 return ret; 129 } 130 131 ret = enable_a53_clk(); 132 if (ret != 0) { 133 return ret; 134 } 135 136 ret = enable_xbar_clk(); 137 if (ret != 0) { 138 return ret; 139 } 140 141 return ret; 142 } 143