feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec61

feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec6160bd794f48e3c41718ecce0ec88a

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feat(scmi): update version to 3.0

Update version to 3.0 to align with latest scmi spec implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-

feat(scmi): update version to 3.0

Update version to 3.0 to align with latest scmi spec implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I845e8863ca6e757b1da6f30833e6ec10e21b0667

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feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also move the driver out of css
into drivers/arm. Platforms can configure the
CLUSTERPWRCTLR and CLUSTERPWRDN registers [1] to improve
power efficiency.

These registers enable finer-grained control of
DSU power state transitions, including
powerdown and retention.

IMP_CLUSTERPWRCTLR_EL1 provides:
- Functional retention: Allows configuration of the
duration of inactivity before the DSU uses
CLUSTERPACTIVE to request functional retention.

- Cache power request: These bits are output on
CLUSTERPACTIVE[19:16] to indicate to the power controller
which cache portions must remain powered.

IMP_CLUSTERPWRDN_EL1 includes:
- Powerdown: Triggers full cluster powerdown, including
control logic.

- Memory retention: Requests memory retention mode,
keeping L3 RAM contents while powering off
the rest of the DSU.

The DSU-120 TRM [2] provides the full field definitions,
which are used as references in the `dsu_driver_data` structure.

References:
[1]: https://developer.arm.com/documentation/100453/latest/
[2]: https://developer.arm.com/documentation/102547/0201/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2eba808b8f2a27797782a333c65dd092b03208fe

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feat(tc): port BL2-BL31 interface to firmware handoff framework

Adding support for this framework at the handoff boundary between
firmware stage BL2 and BL31 on TC.

Signed-off-by: Jayanth Dodderi C

feat(tc): port BL2-BL31 interface to firmware handoff framework

Adding support for this framework at the handoff boundary between
firmware stage BL2 and BL31 on TC.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I8e29b859e57a732e53f7532a5869ed4c8665b161

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feat(arm): convert arm platforms to expect a wakeup

Newer cores in upcoming platforms may refuse to power down. The PSCI
library is already prepared for this so convert platform code to also
allow t

feat(arm): convert arm platforms to expect a wakeup

Newer cores in upcoming platforms may refuse to power down. The PSCI
library is already prepared for this so convert platform code to also
allow this. This is simple - drop the `wfi` + panic and let common code
deal with the fallout. The end result will be the same (sans the
message) except the platform will have fewer responsibilities. The only
exception is for cores being signalled to power off gracefully ahead of
system reset. That path must also be terminal so replace the end with
the same psci_pwrdown_cpu_end() to behave the same as the generic
implementation. It will handle wakeups and panic, hoping that the system
gets reset from under it. The dmb is upgraded to a dsb so no functional
change.

Change-Id: I381f96bec8532bda6ccdac65de57971aac42e7e8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(tc): add MHUv3 doorbell support on TC3

Enables the doorbell channels in MHUv3 for TC3.

Change-Id: Ib4f47df3e54f9182939ea6c1d8bc1a66a3c03094
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.

feat(tc): add MHUv3 doorbell support on TC3

Enables the doorbell channels in MHUv3 for TC3.

Change-Id: Ib4f47df3e54f9182939ea6c1d8bc1a66a3c03094
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(dsu): save/restore DSU PMU register

Adds driver support to preserve DSU PMU register values over a DSU
power cycle. This driver needs to be enabled by the platforms that
support DSU and also ne

feat(dsu): save/restore DSU PMU register

Adds driver support to preserve DSU PMU register values over a DSU
power cycle. This driver needs to be enabled by the platforms that
support DSU and also need it's PMU registers to be preserved

Change-Id: I7fc68a3d7d99ee369379aa5cd114fffc763fc0d2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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refactor(css): support multiple SDS regions

Extend the SDS driver to be able to handle multiple
SDS regions:
- AP-SCP
- AP-RSS

Change-Id: Id303840b248c383b3f960227cbf6333d1cc75e65
Signed-off-by:

refactor(css): support multiple SDS regions

Extend the SDS driver to be able to handle multiple
SDS regions:
- AP-SCP
- AP-RSS

Change-Id: Id303840b248c383b3f960227cbf6333d1cc75e65
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>

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fix(scmi): induce a delay in monitoring SCMI channel status

Reading the SCMI mailbox status in polling mode causes a burst of bus
accesses. On certain platforms, this would not be ideal as the share

fix(scmi): induce a delay in monitoring SCMI channel status

Reading the SCMI mailbox status in polling mode causes a burst of bus
accesses. On certain platforms, this would not be ideal as the shared
bus on the CPU subsystem might cause contentions across all the CPUs.
So allow platforms to specify a delay to be introduced while polling.

Change-Id: Ib90ad7b5954854071cfd543f4a27a178dde3d5c6
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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